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review.evervolv.com / android_kernel_htc_msm8960 / cc4ec158cad51839206825777975f021f33344fc / . / arch / arm / boot / dts / msm8974.dtsi
blob: edb86be1e70dcb221d2f8b21a859d8c438315022 [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]16/include/ "msm-gdsc.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]17
18/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]19 model = "Qualcomm MSM 8974";
20 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]21 interrupt-parent = <&intc>;
22
23 intc: interrupt-controller@F9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]26 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]27 reg = <0xF9000000 0x1000>,
28 <0xF9002000 0x1000>;
29 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]30
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]31 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]32 compatible = "qcom,msm-gpio";
33 interrupt-controller;
34 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]35 reg = <0xfd510000 0x4000>;
36 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]37 };
38
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]39 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]40 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]41 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]42 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]43 };
44
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]45 qcom,vidc@fdc00000 {
46 compatible = "qcom,msm-vidc";
47 reg = <0xfdc00000 0xff000>;
48 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]49 vidc-cp-map = <0x1000000 0x40000000>;
50 vidc-ns-map = <0x40000000 0x40000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]51 };
52
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]53 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]54 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]55 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]56 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]57 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]58
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]59 serial@f995e000 {
60 compatible = "qcom,msm-lsuart-v14";
61 reg = <0xf995e000 0x1000>;
62 interrupts = <0 114 0>;
63 };
64
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]65 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]66 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]67 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]68 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]69 HSUSB_VDDCX-supply = <&pm8841_s2>;
70 HSUSB_1p8-supply = <&pm8941_l6>;
71 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]72
73 qcom,hsusb-otg-phy-type = <2>;
74 qcom,hsusb-otg-mode = <1>;
75 qcom,hsusb-otg-otg-control = <1>;
76 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]77
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]78 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]79 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]80 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]81 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]82 interrupts = <0 123 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]83 vdd-supply = <&pm8941_l20>;
84 vdd-io-supply = <&pm8941_s3>;
85
86 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
87 qcom,sdcc-vdd-current_level = <800 500000>;
88
89 qcom,sdcc-vdd-io-always_on;
90 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
91 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]92
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]93 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
94 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
95 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
96 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
97
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]98 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
99 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]100 qcom,sdcc-bus-width = <8>;
101 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]102 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]103 };
104
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]105 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]106 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]107 compatible = "qcom,msm-sdcc";
108 reg = <0xf98a4000 0x1000>;
109 interrupts = <0 125 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]110 vdd-supply = <&pm8941_l21>;
111 vdd-io-supply = <&pm8941_l13>;
112
113 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
114 qcom,sdcc-vdd-current_level = <9000 800000>;
115
116 qcom,sdcc-vdd-io-always_on;
117 qcom,sdcc-vdd-io-lpm_sup;
118 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
119 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]120
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]121 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
122 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
123 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
124 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
125
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]126 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
127 qcom,sdcc-sup-voltages = <2950 2950>;
128 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]129 qcom,sdcc-xpc;
130 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
131 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]132 };
133
134 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]135 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]136 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]137 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]138 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]139
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]140 gpios = <&msmgpio 40 0>, /* CLK */
141 <&msmgpio 39 0>, /* CMD */
142 <&msmgpio 38 0>, /* DATA0 */
143 <&msmgpio 37 0>, /* DATA1 */
144 <&msmgpio 36 0>, /* DATA2 */
145 <&msmgpio 35 0>; /* DATA3 */
146 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
147
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]148 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
149 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]150 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]151 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]152 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]153 };
154
155 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]156 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]157 compatible = "qcom,msm-sdcc";
158 reg = <0xf98e4000 0x1000>;
159 interrupts = <0 129 0>;
160
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]161 gpios = <&msmgpio 93 0>, /* CLK */
162 <&msmgpio 91 0>, /* CMD */
163 <&msmgpio 96 0>, /* DATA0 */
164 <&msmgpio 95 0>, /* DATA1 */
165 <&msmgpio 94 0>, /* DATA2 */
166 <&msmgpio 92 0>; /* DATA3 */
167 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
168
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]169 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
170 qcom,sdcc-sup-voltages = <1800 1800>;
171 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]172 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]173 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]174 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]175
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]176 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]177 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]178 reg = <0xf9984000 0x15000>,
179 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]180 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]181
182 qcom,bam-dma-res-pipes = <6>;
183 };
184
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]185
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]186 spi@f9924000 {
187 compatible = "qcom,spi-qup-v2";
188 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]189 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]190 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]191 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]192
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]193 slim@fe12f000 {
194 cell-index = <1>;
195 compatible = "qcom,slim-msm";
196 reg = <0xfe12f000 0x35000>,
197 <0xfe104000 0x20000>;
198 reg-names = "slimbus_physical", "slimbus_bam_physical";
199 interrupts = <0 163 0 0 164 0>;
200 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
201 qcom,min-clk-gear = <10>;
202 };
203
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]204 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]205 cell-index = <0>;
206 compatible = "qcom,spmi-pmic-arb";
207 reg = <0xfc4cf000 0x1000>,
208 <0Xfc4cb000 0x1000>;
209 /* 190,ee0_krait_hlos_spmi_periph_irq */
210 /* 187,channel_0_krait_hlos_trans_done_irq */
211 interrupts = <0 190 0 0 187 0>;
212 qcom,pmic-arb-ee = <0>;
213 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]214 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
215 <0x13100001>, /* PM8941_LDO2 */
216 <0x13200002>, /* PM8941_LDO3 */
217 <0x13300003>, /* PM8941_LDO4 */
218 <0x13400004>, /* PM8941_LDO5 */
219 <0x13500005>, /* PM8941_LDO6 */
220 <0x13600006>, /* PM8941_LDO7 */
221 <0x13700007>, /* PM8941_LDO8 */
222 <0x13800008>, /* PM8941_LDO9 */
223 <0x13900009>, /* PM8941_LDO10 */
224 <0x13a0000a>, /* PM8941_LDO11 */
225 <0x13b0000b>, /* PM8941_LDO12 */
226 <0x13c0000c>, /* PM8941_LDO13 */
227 <0x13d0000d>, /* PM8941_LDO14 */
228 <0x13e0000e>, /* PM8941_LDO15 */
229 <0x13f0000f>, /* PM8941_LDO16 */
230 <0x14000010>, /* PM8941_LDO17 */
231 <0x14100011>, /* PM8941_LDO18 */
232 <0x14200012>, /* PM8941_LDO19 */
233 <0x14300013>, /* PM8941_LDO20 */
234 <0x14400014>, /* PM8941_LDO21 */
235 <0x14500015>, /* PM8941_LDO22 */
236 <0x14600016>, /* PM8941_LDO23 */
237 <0x14700017>, /* PM8941_LDO24 */
238 <0x14800018>, /* PM8941_LDO25 */
239 <0x14900019>, /* PM8941_LDO26 */
240 <0x0c00001a>, /* PM8941_GPIO1 */
241 <0x0c10001b>, /* PM8941_GPIO2 */
242 <0x0c20001c>, /* PM8941_GPIO3 */
243 <0x0c30001d>, /* PM8941_GPIO4 */
244 <0x0c40001e>, /* PM8941_GPIO5 */
245 <0x0c50001f>, /* PM8941_GPIO6 */
246 <0x0c600020>, /* PM8941_GPIO7 */
247 <0x0c700021>, /* PM8941_GPIO8 */
248 <0x0c800022>, /* PM8941_GPIO9 */
249 <0x0c900023>, /* PM8941_GPIO10 */
250 <0x0ca00024>, /* PM8941_GPIO11 */
251 <0x0cb00025>, /* PM8941_GPIO12 */
252 <0x0cc00026>, /* PM8941_GPIO13 */
253 <0x0cd00027>, /* PM8941_GPIO14 */
254 <0x0ce00028>, /* PM8941_GPIO15 */
255 <0x0cf00029>, /* PM8941_GPIO16 */
256 <0x0d00002a>, /* PM8941_GPIO17 */
257 <0x0d10002b>, /* PM8941_GPIO18 */
258 <0x0d20002c>, /* PM8941_GPIO19 */
259 <0x0d30002d>, /* PM8941_GPIO20 */
260 <0x0d40002e>, /* PM8941_GPIO21 */
261 <0x0d50002f>, /* PM8941_GPIO22 */
262 <0x0d600030>, /* PM8941_GPIO23 */
263 <0x0d700031>, /* PM8941_GPIO24 */
264 <0x0d800032>, /* PM8941_GPIO25 */
265 <0x0d900033>, /* PM8941_GPIO26 */
266 <0x0da00034>, /* PM8941_GPIO27 */
267 <0x0db00035>, /* PM8941_GPIO28 */
268 <0x0dc00036>, /* PM8941_GPIO29 */
269 <0x0dd00037>, /* PM8941_GPIO30 */
270 <0x0de00038>, /* PM8941_GPIO31 */
271 <0x0df00039>, /* PM8941_GPIO32 */
272 <0x0e00003a>, /* PM8941_GPIO33 */
273 <0x0e10003b>, /* PM8941_GPIO34 */
274 <0x0e20003c>, /* PM8941_GPIO35 */
275 <0x0e30003d>, /* PM8941_GPIO36 */
276 <0x0280003e>, /* COINCELL */
277 <0x0100003f>, /* SMBC_OVP */
278 <0x01100040>, /* SMBC_CHG */
279 <0x01200041>, /* SMBC_BIF */
280 <0x00500042>, /* INTERRUPT */
281 <0x00100043>, /* PM8941_0 */
282 <0x20100044>, /* PM8841_0 */
283 <0x10100045>, /* PM8941_1 */
284 <0x30100046>, /* PM8841_1 */
285 <0x00800047>, /* PON0 */
286 <0x20800048>, /* PON1 */
287 <0x11000049>, /* PM8941_SMPS1 */
288 <0x1110004a>, /* PM8941_SMPS2 */
289 <0x1120004b>, /* PM8941_SMPS3 */
290 <0x3100004c>, /* PM8841_SMPS1 */
291 <0x3110004d>, /* PM8841_SMPS2 */
292 <0x3120004e>, /* PM8841_SMPS3 */
293 <0x3130004f>, /* PM8841_SMPS4 */
294 <0x31400050>, /* PM8841_SMPS5 */
295 <0x31500051>, /* PM8841_SMPS6 */
296 <0x31600052>, /* PM8841_SMPS7 */
297 <0x31700053>, /* PM8841_SMPS8 */
298 <0x05000054>, /* SHARED_XO */
299 <0x05100055>, /* BB_CLK1 */
300 <0x05200056>, /* BB_CLK2 */
301 <0x05900057>, /* SLEEP_CLK */
302 <0x07000058>, /* PBS_CORE */
303 <0x07100059>, /* PBS_CLIENT1 */
304 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]305 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]306
307 i2c@f9966000 {
308 cell-index = <0>;
309 compatible = "qcom,i2c-qup";
310 reg = <0Xf9966000 0x1000>;
311 reg-names = "qup_phys_addr";
312 interrupts = <0 104 0>;
313 interrupt-names = "qup_err_intr";
314 qcom,i2c-bus-freq = <100000>;
315 qcom,i2c-src-freq = <24000000>;
316 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]317
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]318 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]319 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]320 krait0-supply = <&krait0_vreg>;
321 krait1-supply = <&krait1_vreg>;
322 krait2-supply = <&krait2_vreg>;
323 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]324 krait0_mem-supply = <&pm8841_s1_ao>;
325 krait1_mem-supply = <&pm8841_s1_ao>;
326 krait2_mem-supply = <&pm8841_s1_ao>;
327 krait3_mem-supply = <&pm8841_s1_ao>;
328 krait0_dig-supply = <&pm8841_s2_corner_ao>;
329 krait1_dig-supply = <&pm8841_s2_corner_ao>;
330 krait2_dig-supply = <&pm8841_s2_corner_ao>;
331 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]332 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
333 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
334 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
335 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
336 l2_hfpll_a-supply = <&pm8941_s2_ao>;
337 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
338 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
339 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
340 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
341 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]342 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]343
344 qcom,ssusb@F9200000 {
345 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530[diff] [blame]346 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]347 interrupts = <0 131 0 0 179 0>;
348 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]349 SSUSB_VDDCX-supply = <&pm8841_s2>;
350 SSUSB_1p8-supply = <&pm8941_l6>;
351 HSUSB_VDDCX-supply = <&pm8841_s2>;
352 HSUSB_1p8-supply = <&pm8941_l6>;
353 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]354 qcom,dwc-usb3-msm-dbm-eps = <4>;
355 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]356
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]357 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
358 parent-supply = <&pm8841_s4>;
359 };
360
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]361 qcom,lpass@fe200000 {
362 compatible = "qcom,pil-q6v5-lpass";
363 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]364 <0xfd485100 0x00010>;
365
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]366 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]367 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]368
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]369 qcom,msm-pcm {
370 compatible = "qcom,msm-pcm-dsp";
371 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]372
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]373 qcom,msm-pcm-routing {
374 compatible = "qcom,msm-pcm-routing";
375 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]376
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]377 qcom,msm-pcm-lpa {
378 compatible = "qcom,msm-pcm-lpa";
379 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]380
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]381 qcom,msm-compr-dsp {
382 compatible = "qcom,msm-compr-dsp";
383 };
384
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]385 qcom,msm-voip-dsp {
386 compatible = "qcom,msm-voip-dsp";
387 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]388
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]389 qcom,msm-stub-codec {
390 compatible = "qcom,msm-stub-codec";
391 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]392
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]393 qcom,msm-dai-fe {
394 compatible = "qcom,msm-dai-fe";
395 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]396
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]397 qcom,msm-auxpcm {
398 compatible = "qcom,msm-auxpcm-resource";
399 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
400 qcom,msm-cpudai-auxpcm-mode = <0>;
401 qcom,msm-cpudai-auxpcm-sync = <1>;
402 qcom,msm-cpudai-auxpcm-frame = <5>;
403 qcom,msm-cpudai-auxpcm-quant = <2>;
404 qcom,msm-cpudai-auxpcm-slot = <1>;
405 qcom,msm-cpudai-auxpcm-data = <0>;
406 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]407
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]408 qcom,msm-auxpcm-rx {
409 qcom,msm-auxpcm-dev-id = <4106>;
410 compatible = "qcom,msm-auxpcm-dev";
411 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]412
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]413 qcom,msm-auxpcm-tx {
414 qcom,msm-auxpcm-dev-id = <4107>;
415 compatible = "qcom,msm-auxpcm-dev";
416 };
417 };
418
419 qcom,msm-pcm-hostless {
420 compatible = "qcom,msm-pcm-hostless";
421 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]422
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]423 qcom,mss@fc880000 {
424 compatible = "qcom,pil-q6v5-mss";
425 reg = <0xfc880000 0x100>,
426 <0xfd485000 0x400>,
427 <0xfc820000 0x020>,
428 <0xfc401680 0x004>;
429 vdd_mss-supply = <&pm8841_s3>;
430
431 qcom,firmware-name = "mba";
432 qcom,pil-self-auth = <1>;
433 };
434
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]435 qcom,mba@fc820000 {
436 compatible = "qcom,pil-mba";
437 reg = <0xfc820000 0x0020>,
438 <0x0d1fc000 0x4000>;
439
440 qcom,firmware-name = "modem";
441 qcom,depends-on = "mba";
442 };
443
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]444 qcom,pronto@fb21b000 {
445 compatible = "qcom,pil-pronto";
446 reg = <0xfb21b000 0x3000>,
447 <0xfc401700 0x4>,
448 <0xfd485300 0xc>;
449 vdd_pronto_pll-supply = <&pm8941_l12>;
450
451 qcom,firmware-name = "wcnss";
452 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]453
454 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]455 compatible = "qcom,msm-ocmem";
456 reg = <0xfdd00000 0x2000>,
457 <0xfdd02000 0x2000>,
458 <0xfe039000 0x400>,
459 <0xfec00000 0x180000>;
460 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
461 interrupts = <0 76 0 0 77 0>;
462 interrupt-names = "ocmem_irq", "dm_irq";
463 qcom,ocmem-num-regions = <0x3>;
464 #address-cells = <1>;
465 #size-cells = <1>;
466 ranges = <0x0 0xfec00000 0x180000>;
467
468 partition@0 {
469 reg = <0x0 0x100000>;
470 qcom,ocmem-part-name = "graphics";
471 qcom,ocmem-part-min = <0x80000>;
472 };
473
474 partition@80000 {
475 reg = <0x80000 0xA0000>;
476 qcom,ocmem-part-name = "lp_audio";
477 qcom,ocmem-part-min = <0xA0000>;
478 };
479
480 partition@E0000 {
481 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame^]482 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]483 qcom,ocmem-part-min = <0x20000>;
484 };
485
486 partition@100000 {
487 reg = <0x100000 0x80000>;
488 qcom,ocmem-part-name = "video";
489 qcom,ocmem-part-min = <0x55000>;
490 };
491
492 partition@140000 {
493 reg = <0x140000 0x40000>;
494 qcom,ocmem-part-name = "sensors";
495 qcom,ocmem-part-min = <0x40000>;
496 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]497 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]498
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]499 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]500 compatible = "qcom,rpm-smd";
501 rpm-channel-name = "rpm_requests";
502 rpm-channel-type = <15>; /* SMD_APPS_RPM */
503 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]504
505 qcom,msm-rng@f9bff000 {
506 compatible = "qcom,msm-rng";
507 reg = <0xf9bff000 0x200>;
508 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]509
510 qcom,qseecom@fe806000 {
511 compatible = "qcom,qseecom";
512 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]513
514 qcom,mdss_mdp@fd900000 {
515 cell-index = <0>;
516 compatible = "qcom,mdss_mdp";
517 reg = <0xfd900000 0x22100>;
518 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]519 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]520 };
521
522 qcom,mdss_wb_panel {
523 cell-index = <1>;
524 compatible = "qcom,mdss_wb";
525 qcom,mdss_pan_res = <640 480>;
526 qcom,mdss_pan_bpp = <24>;
527 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]528
529 qcom,wdt@f9017000 {
530 compatible = "qcom,msm-watchdog";
531 reg = <0xf9017000 0x1000>;
532 interrupts = <0 3 0 0 4 0>;
533 qcom,bark-time = <11000>;
534 qcom,pet-time = <10000>;
535 qcom,ipi-ping = <1>;
536 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]537
538 qcom,tz-log@fe805720 {
539 compatible = "qcom,tz-log";
540 reg = <0xfe805720 0x1000>;
541 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]542
543 qcom,venus@fdce0000 {
544 compatible = "qcom,pil-venus";
545 reg = <0xfdce0000 0x4000>,
546 <0xfdc80208 0x8>;
547 vdd-supply = <&gdsc_venus>;
548
549 qcom,firmware-name = "venus";
550 qcom,firmware-min-paddr = <0xF500000>;
551 qcom,firmware-max-paddr = <0xFA00000>;
552 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]553
554 tsens@fc4a8000 {
555 compatible = "qcom,msm-tsens";
556 reg = <0xfc4a8000 0x2000>,
557 <0xfc4b80d0 0x5>;
558 reg-names = "tsens_physical", "tsens_eeprom_physical";
559 interrupts = <0 184 0>;
560 qcom,sensors = <11>;
561 qcom,slope = <1134 1122 1142 1123 1176 1176 1176 1186 1176
562 1176 1176>;
563 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]564};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]565
566/include/ "msm-pm8x41-rpm-regulator.dtsi"
567/include/ "msm-pm8841.dtsi"
568/include/ "msm-pm8941.dtsi"
569/include/ "msm8974-regulator.dtsi"
570/include/ "msm8974-gpio.dtsi"