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review.evervolv.com / android_kernel_htc_msm8960 / cd15e8c3313f2831d2d6c7951a93eb5de9621e5a / . / arch / mips / bcm63xx / cpu.c
blob: 6dc43f0483e80b8fa77f23694daa7ed7da51e9ef [file] [log] [blame]
Maxime Bizone7300d02009-08-18 13:23:37 +0100[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/cpu.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_regs.h>
15#include <bcm63xx_io.h>
16#include <bcm63xx_irq.h>
17
18const unsigned long *bcm63xx_regs_base;
19EXPORT_SYMBOL(bcm63xx_regs_base);
20
21const int *bcm63xx_irqs;
22EXPORT_SYMBOL(bcm63xx_irqs);
23
24static u16 bcm63xx_cpu_id;
25static u16 bcm63xx_cpu_rev;
26static unsigned int bcm63xx_cpu_freq;
27static unsigned int bcm63xx_memory_size;
28
29/*
30 * 6338 register sets and irqs
31 */
32static const unsigned long bcm96338_regs_base[] = {
33 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
34 [RSET_PERF] = BCM_6338_PERF_BASE,
35 [RSET_TIMER] = BCM_6338_TIMER_BASE,
36 [RSET_WDT] = BCM_6338_WDT_BASE,
37 [RSET_UART0] = BCM_6338_UART0_BASE,
38 [RSET_GPIO] = BCM_6338_GPIO_BASE,
39 [RSET_SPI] = BCM_6338_SPI_BASE,
40 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
41 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
42 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
43 [RSET_UDC0] = BCM_6338_UDC0_BASE,
44 [RSET_MPI] = BCM_6338_MPI_BASE,
45 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
46 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
47 [RSET_DSL] = BCM_6338_DSL_BASE,
48 [RSET_ENET0] = BCM_6338_ENET0_BASE,
49 [RSET_ENET1] = BCM_6338_ENET1_BASE,
50 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
51 [RSET_MEMC] = BCM_6338_MEMC_BASE,
52 [RSET_DDR] = BCM_6338_DDR_BASE,
53};
54
55static const int bcm96338_irqs[] = {
56 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
57 [IRQ_UART0] = BCM_6338_UART0_IRQ,
58 [IRQ_DSL] = BCM_6338_DSL_IRQ,
59 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
60 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
61 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
62 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
63};
64
65/*
66 * 6345 register sets and irqs
67 */
68static const unsigned long bcm96345_regs_base[] = {
69 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
70 [RSET_PERF] = BCM_6345_PERF_BASE,
71 [RSET_TIMER] = BCM_6345_TIMER_BASE,
72 [RSET_WDT] = BCM_6345_WDT_BASE,
73 [RSET_UART0] = BCM_6345_UART0_BASE,
74 [RSET_GPIO] = BCM_6345_GPIO_BASE,
75 [RSET_SPI] = BCM_6345_SPI_BASE,
76 [RSET_UDC0] = BCM_6345_UDC0_BASE,
77 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
78 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
79 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
80 [RSET_MPI] = BCM_6345_MPI_BASE,
81 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
82 [RSET_DSL] = BCM_6345_DSL_BASE,
83 [RSET_ENET0] = BCM_6345_ENET0_BASE,
84 [RSET_ENET1] = BCM_6345_ENET1_BASE,
85 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
86 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
87 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
88 [RSET_MEMC] = BCM_6345_MEMC_BASE,
89 [RSET_DDR] = BCM_6345_DDR_BASE,
90};
91
92static const int bcm96345_irqs[] = {
93 [IRQ_TIMER] = BCM_6345_TIMER_IRQ,
94 [IRQ_UART0] = BCM_6345_UART0_IRQ,
95 [IRQ_DSL] = BCM_6345_DSL_IRQ,
96 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
97 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
98 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
99 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
100};
101
102/*
103 * 6348 register sets and irqs
104 */
105static const unsigned long bcm96348_regs_base[] = {
106 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
107 [RSET_PERF] = BCM_6348_PERF_BASE,
108 [RSET_TIMER] = BCM_6348_TIMER_BASE,
109 [RSET_WDT] = BCM_6348_WDT_BASE,
110 [RSET_UART0] = BCM_6348_UART0_BASE,
111 [RSET_GPIO] = BCM_6348_GPIO_BASE,
112 [RSET_SPI] = BCM_6348_SPI_BASE,
113 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
114 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
115 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
116 [RSET_MPI] = BCM_6348_MPI_BASE,
117 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
118 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
119 [RSET_DSL] = BCM_6348_DSL_BASE,
120 [RSET_ENET0] = BCM_6348_ENET0_BASE,
121 [RSET_ENET1] = BCM_6348_ENET1_BASE,
122 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
123 [RSET_MEMC] = BCM_6348_MEMC_BASE,
124 [RSET_DDR] = BCM_6348_DDR_BASE,
125};
126
127static const int bcm96348_irqs[] = {
128 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
129 [IRQ_UART0] = BCM_6348_UART0_IRQ,
130 [IRQ_DSL] = BCM_6348_DSL_IRQ,
131 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
132 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
133 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
134 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
135 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
136 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
137 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
138 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
139 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
140 [IRQ_PCI] = BCM_6348_PCI_IRQ,
141};
142
143/*
144 * 6358 register sets and irqs
145 */
146static const unsigned long bcm96358_regs_base[] = {
147 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
148 [RSET_PERF] = BCM_6358_PERF_BASE,
149 [RSET_TIMER] = BCM_6358_TIMER_BASE,
150 [RSET_WDT] = BCM_6358_WDT_BASE,
151 [RSET_UART0] = BCM_6358_UART0_BASE,
152 [RSET_GPIO] = BCM_6358_GPIO_BASE,
153 [RSET_SPI] = BCM_6358_SPI_BASE,
154 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
155 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
156 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
157 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
158 [RSET_MPI] = BCM_6358_MPI_BASE,
159 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
160 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
161 [RSET_DSL] = BCM_6358_DSL_BASE,
162 [RSET_ENET0] = BCM_6358_ENET0_BASE,
163 [RSET_ENET1] = BCM_6358_ENET1_BASE,
164 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
165 [RSET_MEMC] = BCM_6358_MEMC_BASE,
166 [RSET_DDR] = BCM_6358_DDR_BASE,
167};
168
169static const int bcm96358_irqs[] = {
170 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
171 [IRQ_UART0] = BCM_6358_UART0_IRQ,
172 [IRQ_DSL] = BCM_6358_DSL_IRQ,
173 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
174 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
175 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
176 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
177 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
178 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
179 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
180 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
181 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
182 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
183 [IRQ_PCI] = BCM_6358_PCI_IRQ,
184};
185
186u16 __bcm63xx_get_cpu_id(void)
187{
188 return bcm63xx_cpu_id;
189}
190
191EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
192
193u16 bcm63xx_get_cpu_rev(void)
194{
195 return bcm63xx_cpu_rev;
196}
197
198EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
199
200unsigned int bcm63xx_get_cpu_freq(void)
201{
202 return bcm63xx_cpu_freq;
203}
204
205unsigned int bcm63xx_get_memory_size(void)
206{
207 return bcm63xx_memory_size;
208}
209
210static unsigned int detect_cpu_clock(void)
211{
212 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
213
214 /* BCM6338 has a fixed 240 Mhz frequency */
215 if (BCMCPU_IS_6338())
216 return 240000000;
217
218 /* BCM6345 has a fixed 140Mhz frequency */
219 if (BCMCPU_IS_6345())
220 return 140000000;
221
222 /*
223 * frequency depends on PLL configuration:
224 */
225 if (BCMCPU_IS_6348()) {
226 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
227 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
228 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
229 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
230 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
231 n1 += 1;
232 n2 += 2;
233 m1 += 1;
234 }
235
236 if (BCMCPU_IS_6358()) {
237 /* 16MHz * N1 * N2 / M1_CPU */
238 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
239 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
240 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
241 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
242 }
243
244 return (16 * 1000000 * n1 * n2) / m1;
245}
246
247/*
248 * attempt to detect the amount of memory installed
249 */
250static unsigned int detect_memory_size(void)
251{
252 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
253 u32 val;
254
255 if (BCMCPU_IS_6345())
256 return (8 * 1024 * 1024);
257
258 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
259 val = bcm_sdram_readl(SDRAM_CFG_REG);
260 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
261 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
262 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
263 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
264 }
265
266 if (BCMCPU_IS_6358()) {
267 val = bcm_memc_readl(MEMC_CFG_REG);
268 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
269 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
270 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
271 banks = 2;
272 }
273
274 /* 0 => 11 address bits ... 2 => 13 address bits */
275 rows += 11;
276
277 /* 0 => 8 address bits ... 2 => 10 address bits */
278 cols += 8;
279
280 return 1 << (cols + rows + (is_32bits + 1) + banks);
281}
282
283void __init bcm63xx_cpu_init(void)
284{
285 unsigned int tmp, expected_cpu_id;
286 struct cpuinfo_mips *c = &current_cpu_data;
287
288 /* soc registers location depends on cpu type */
289 expected_cpu_id = 0;
290
291 switch (c->cputype) {
292 /*
293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
294 */
295 case CPU_BCM3302:
296 expected_cpu_id = BCM6338_CPU_ID;
297 bcm63xx_regs_base = bcm96338_regs_base;
298 bcm63xx_irqs = bcm96338_irqs;
299 break;
300 case CPU_BCM6345:
301 expected_cpu_id = BCM6345_CPU_ID;
302 bcm63xx_regs_base = bcm96345_regs_base;
303 bcm63xx_irqs = bcm96345_irqs;
304 break;
305 case CPU_BCM6348:
306 expected_cpu_id = BCM6348_CPU_ID;
307 bcm63xx_regs_base = bcm96348_regs_base;
308 bcm63xx_irqs = bcm96348_irqs;
309 break;
310 case CPU_BCM6358:
311 expected_cpu_id = BCM6358_CPU_ID;
312 bcm63xx_regs_base = bcm96358_regs_base;
313 bcm63xx_irqs = bcm96358_irqs;
314 break;
315 }
316
317 /*
318 * really early to panic, but delaying panic would not help since we
319 * will never get any working console
320 */
321 if (!expected_cpu_id)
322 panic("unsupported Broadcom CPU");
323
324 /*
325 * bcm63xx_regs_base is set, we can access soc registers
326 */
327
328 /* double check CPU type */
329 tmp = bcm_perf_readl(PERF_REV_REG);
330 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
331 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
332
333 if (bcm63xx_cpu_id != expected_cpu_id)
334 panic("bcm63xx CPU id mismatch");
335
336 bcm63xx_cpu_freq = detect_cpu_clock();
337 bcm63xx_memory_size = detect_memory_size();
338
339 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
340 bcm63xx_cpu_id, bcm63xx_cpu_rev);
341 printk(KERN_INFO "CPU frequency is %u MHz\n",
342 bcm63xx_cpu_freq / 1000000);
343 printk(KERN_INFO "%uMB of RAM installed\n",
344 bcm63xx_memory_size >> 20);
345}