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review.evervolv.com / android_kernel_htc_msm8960 / cee9e8c5cb1554e9e85ad764d27b6c808555ed89 / . / drivers / pci / pcie / aer / aerdrv.h
blob: bf655dbaf8e25b8b53e3a2dc303b560e0f31a8e7 [file] [log] [blame]
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]1/*
2 * Copyright (C) 2006 Intel Corp.
3 * Tom Long Nguyen (tom.l.nguyen@intel.com)
4 * Zhang Yanmin (yanmin.zhang@intel.com)
5 *
6 */
7
8#ifndef _AERDRV_H_
9#define _AERDRV_H_
10
11#include <linux/pcieport_if.h>
12#include <linux/aer.h>
13
14#define AER_NONFATAL 0
15#define AER_FATAL 1
16#define AER_CORRECTABLE 2
17#define AER_UNCORRECTABLE 4
18#define AER_ERROR_MASK 0x001fffff
19#define AER_ERROR(d) (d & AER_ERROR_MASK)
20
21#define OSC_METHOD_RUN_SUCCESS 0
22#define OSC_METHOD_NOT_SUPPORTED 1
23#define OSC_METHOD_RUN_FAILURE 2
24
25/* Root Error Status Register Bits */
26#define ROOT_ERR_STATUS_MASKS 0x0f
27
28#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
29 PCI_EXP_RTCTL_SENFEE| \
30 PCI_EXP_RTCTL_SEFEE)
31#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
32 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
33 PCI_ERR_ROOT_CMD_FATAL_EN)
34#define ERR_COR_ID(d) (d & 0xffff)
35#define ERR_UNCOR_ID(d) (d >> 16)
36
37#define AER_SUCCESS 0
38#define AER_UNSUCCESS 1
39#define AER_ERROR_SOURCES_MAX 100
40
41#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
42 PCI_ERR_UNC_ECRC| \
43 PCI_ERR_UNC_UNSUP| \
44 PCI_ERR_UNC_COMP_ABORT| \
45 PCI_ERR_UNC_UNX_COMP| \
46 PCI_ERR_UNC_MALF_TLP)
47
48/* AER Error Info Flags */
49#define AER_TLP_HEADER_VALID_FLAG 0x00000001
50#define AER_MULTI_ERROR_VALID_FLAG 0x00000002
51
52#define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
53#define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
54
55struct header_log_regs {
56 unsigned int dw0;
57 unsigned int dw1;
58 unsigned int dw2;
59 unsigned int dw3;
60};
61
62struct aer_err_info {
63 int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
64 int flags;
65 unsigned int status; /* COR/UNCOR Error Status */
66 struct header_log_regs tlp; /* TLP Header */
67};
68
69struct aer_err_source {
70 unsigned int status;
71 unsigned int id;
72};
73
74struct aer_rpc {
75 struct pcie_device *rpd; /* Root Port device */
76 struct work_struct dpc_handler;
77 struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
78 unsigned short prod_idx; /* Error Producer Index */
79 unsigned short cons_idx; /* Error Consumer Index */
80 int isr;
81 spinlock_t e_lock; /*
82 * Lock access to Error Status/ID Regs
83 * and error producer/consumer index
84 */
85 struct mutex rpc_mutex; /*
86 * only one thread could do
87 * recovery on the same
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100[diff] [blame]88 * root port hierarchy
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]89 */
90 wait_queue_head_t wait_release;
91};
92
93struct aer_broadcast_data {
94 enum pci_channel_state state;
95 enum pci_ers_result result;
96};
97
98static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
99 enum pci_ers_result new)
100{
101 switch (orig) {
102 case PCI_ERS_RESULT_CAN_RECOVER:
103 case PCI_ERS_RESULT_RECOVERED:
104 orig = new;
105 break;
106 case PCI_ERS_RESULT_DISCONNECT:
107 if (new == PCI_ERS_RESULT_NEED_RESET)
108 orig = new;
109 break;
110 default:
111 break;
112 }
113
114 return orig;
115}
116
117extern struct bus_type pcie_port_bus_type;
118extern void aer_enable_rootport(struct aer_rpc *rpc);
119extern void aer_delete_rootport(struct aer_rpc *rpc);
120extern int aer_init(struct pcie_device *dev);
David Howells65f27f32006-11-22 14:55:48 +0000[diff] [blame]121extern void aer_isr(struct work_struct *work);
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]122extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
123extern int aer_osc_setup(struct pci_dev *dev);
124
125#endif //_AERDRV_H_