| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: vac-ops.h,v 1.13 1998/01/30 10:59:59 jj Exp $ */ | 
 | 2 | #ifndef _SPARC_VAC_OPS_H | 
 | 3 | #define _SPARC_VAC_OPS_H | 
 | 4 |  | 
 | 5 | /* vac-ops.h: Inline assembly routines to do operations on the Sparc | 
 | 6 |  *            VAC (virtual address cache) for the sun4c. | 
 | 7 |  * | 
 | 8 |  * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu) | 
 | 9 |  */ | 
 | 10 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <asm/sysen.h> | 
 | 12 | #include <asm/contregs.h> | 
 | 13 | #include <asm/asi.h> | 
 | 14 |  | 
 | 15 | /* The SUN4C models have a virtually addressed write-through | 
 | 16 |  * cache. | 
 | 17 |  * | 
 | 18 |  * The cache tags are directly accessible through an ASI and | 
 | 19 |  * each have the form: | 
 | 20 |  * | 
 | 21 |  * ------------------------------------------------------------ | 
 | 22 |  * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ | | 
 | 23 |  * ------------------------------------------------------------ | 
 | 24 |  *  31 25  24   22     21     20     19    18 16  15   2  1  0 | 
 | 25 |  * | 
 | 26 |  * MBZ: These bits are either unused and/or reserved and should | 
 | 27 |  *      be written as zeroes. | 
 | 28 |  * | 
 | 29 |  * CONTEXT: Records the context to which this cache line belongs. | 
 | 30 |  * | 
 | 31 |  * WRITE: A copy of the writable bit from the mmu pte access bits. | 
 | 32 |  * | 
 | 33 |  * PRIV: A copy of the privileged bit from the pte access bits. | 
 | 34 |  * | 
 | 35 |  * VALID: If set, this line is valid, else invalid. | 
 | 36 |  * | 
 | 37 |  * TagID: Fourteen bits of tag ID. | 
 | 38 |  * | 
 | 39 |  * Every virtual address is seen by the cache like this: | 
 | 40 |  * | 
 | 41 |  * ---------------------------------------- | 
 | 42 |  * |  RESV  | TagID | LINE | BYTE-in-LINE | | 
 | 43 |  * ---------------------------------------- | 
 | 44 |  *  31    30 29   16 15   4 3            0 | 
 | 45 |  * | 
 | 46 |  * RESV: Unused/reserved. | 
 | 47 |  * | 
 | 48 |  * TagID: Used to match the Tag-ID in that vac tags. | 
 | 49 |  * | 
 | 50 |  * LINE: Which line within the cache | 
 | 51 |  * | 
 | 52 |  * BYTE-in-LINE: Which byte within the cache line. | 
 | 53 |  */ | 
 | 54 |  | 
 | 55 | /* Sun4c VAC Tags */ | 
 | 56 | #define S4CVACTAG_CID      0x01c00000 | 
 | 57 | #define S4CVACTAG_W        0x00200000 | 
 | 58 | #define S4CVACTAG_P        0x00100000 | 
 | 59 | #define S4CVACTAG_V        0x00080000 | 
 | 60 | #define S4CVACTAG_TID      0x0000fffc | 
 | 61 |  | 
 | 62 | /* Sun4c VAC Virtual Address */ | 
 | 63 | /* These aren't used, why bother? (Anton) */ | 
 | 64 | #if 0 | 
 | 65 | #define S4CVACVA_TID       0x3fff0000 | 
 | 66 | #define S4CVACVA_LINE      0x0000fff0 | 
 | 67 | #define S4CVACVA_BIL       0x0000000f | 
 | 68 | #endif | 
 | 69 |  | 
 | 70 | /* The indexing of cache lines creates a problem.  Because the line | 
 | 71 |  * field of a virtual address extends past the page offset within | 
 | 72 |  * the virtual address it is possible to have what are called | 
 | 73 |  * 'bad aliases' which will create inconsistencies.  So we must make | 
 | 74 |  * sure that within a context that if a physical page is mapped | 
 | 75 |  * more than once, that 'extra' line bits are the same.  If this is | 
 | 76 |  * not the case, and thus is a 'bad alias' we must turn off the | 
 | 77 |  * cacheable bit in the pte's of all such pages. | 
 | 78 |  */ | 
 | 79 |  | 
 | 80 | #ifdef CONFIG_SUN4 | 
 | 81 | #define S4CVAC_BADBITS     0x0001e000 | 
 | 82 | #else | 
 | 83 | #define S4CVAC_BADBITS    0x0000f000 | 
 | 84 | #endif | 
 | 85 |  | 
 | 86 | /* The following is true if vaddr1 and vaddr2 would cause | 
 | 87 |  * a 'bad alias'. | 
 | 88 |  */ | 
 | 89 | #define S4CVAC_BADALIAS(vaddr1, vaddr2) \ | 
 | 90 |         ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \ | 
 | 91 | 	 (S4CVAC_BADBITS)) | 
 | 92 |  | 
 | 93 | /* The following structure describes the characteristics of a sun4c | 
 | 94 |  * VAC as probed from the prom during boot time. | 
 | 95 |  */ | 
 | 96 | struct sun4c_vac_props { | 
 | 97 | 	unsigned int num_bytes;     /* Size of the cache */ | 
 | 98 | 	unsigned int num_lines;     /* Number of cache lines */ | 
 | 99 | 	unsigned int do_hwflushes;  /* Hardware flushing available? */ | 
 | 100 | 	enum { VAC_NONE, VAC_WRITE_THROUGH, | 
 | 101 | 	    VAC_WRITE_BACK } type;  /* What type of VAC? */ | 
 | 102 | 	unsigned int linesize;      /* Size of each line in bytes */ | 
 | 103 | 	unsigned int log2lsize;     /* log2(linesize) */ | 
 | 104 | 	unsigned int on;            /* VAC is enabled */ | 
 | 105 | }; | 
 | 106 |  | 
 | 107 | extern struct sun4c_vac_props sun4c_vacinfo; | 
 | 108 |  | 
 | 109 | /* sun4c_enable_vac() enables the sun4c virtual address cache. */ | 
 | 110 | static inline void sun4c_enable_vac(void) | 
 | 111 | { | 
 | 112 | 	__asm__ __volatile__("lduba [%0] %1, %%g1\n\t" | 
 | 113 | 			     "or    %%g1, %2, %%g1\n\t" | 
 | 114 | 			     "stba  %%g1, [%0] %1\n\t" | 
 | 115 | 			     : /* no outputs */ | 
 | 116 | 			     : "r" ((unsigned int) AC_SENABLE), | 
 | 117 | 			     "i" (ASI_CONTROL), "i" (SENABLE_CACHE) | 
 | 118 | 			     : "g1", "memory"); | 
 | 119 | 	sun4c_vacinfo.on = 1; | 
 | 120 | } | 
 | 121 |  | 
 | 122 | /* sun4c_disable_vac() disables the virtual address cache. */ | 
 | 123 | static inline void sun4c_disable_vac(void) | 
 | 124 | { | 
 | 125 | 	__asm__ __volatile__("lduba [%0] %1, %%g1\n\t" | 
 | 126 | 			     "andn  %%g1, %2, %%g1\n\t" | 
 | 127 | 			     "stba  %%g1, [%0] %1\n\t" | 
 | 128 | 			     : /* no outputs */ | 
 | 129 | 			     : "r" ((unsigned int) AC_SENABLE), | 
 | 130 | 			     "i" (ASI_CONTROL), "i" (SENABLE_CACHE) | 
 | 131 | 			     : "g1", "memory"); | 
 | 132 | 	sun4c_vacinfo.on = 0; | 
 | 133 | } | 
 | 134 |  | 
 | 135 | #endif /* !(_SPARC_VAC_OPS_H) */ |