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Kumar Galad0fc2ea2008-07-07 11:28:33 -05001* Board Control and Status (BCSR)
2
3Required properties:
4
Anton Vorontsovfd657ef2008-10-18 04:23:52 +04005 - compatible : Should be "fsl,<board>-bcsr"
Kumar Galad0fc2ea2008-07-07 11:28:33 -05006 - reg : Offset and length of the register set for the device
7
8Example:
9
10 bcsr@f8000000 {
Anton Vorontsovfd657ef2008-10-18 04:23:52 +040011 compatible = "fsl,mpc8360mds-bcsr";
Kumar Galad0fc2ea2008-07-07 11:28:33 -050012 reg = <f8000000 8000>;
13 };
14
15* Freescale on board FPGA
16
17This is the memory-mapped registers for on board FPGA.
18
19Required properities:
20- compatible : should be "fsl,fpga-pixis".
Anton Vorontsov94409d62008-12-18 19:37:23 +030021- reg : should contain the address and the length of the FPPGA register
Kumar Galad0fc2ea2008-07-07 11:28:33 -050022 set.
23
24Example (MPC8610HPCD):
25
26 board-control@e8000000 {
27 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>;
29 };
Anton Vorontsov94409d62008-12-18 19:37:23 +030030
31* Freescale BCSR GPIO banks
32
33Some BCSR registers act as simple GPIO controllers, each such
34register can be represented by the gpio-controller node.
35
36Required properities:
37- compatible : Should be "fsl,<board>-bcsr-gpio".
38- reg : Should contain the address and the length of the GPIO bank
39 register.
40- #gpio-cells : Should be two. The first cell is the pin number and the
Martin Olsson98a17082009-04-22 18:21:29 +020041 second cell is used to specify optional parameters (currently unused).
Anton Vorontsov94409d62008-12-18 19:37:23 +030042- gpio-controller : Marks the port as GPIO controller.
43
44Example:
45
46 bcsr@1,0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8360mds-bcsr";
50 reg = <1 0 0x8000>;
51 ranges = <0 1 0 0x8000>;
52
53 bcsr13: gpio-controller@d {
54 #gpio-cells = <2>;
55 compatible = "fsl,mpc8360mds-bcsr-gpio";
56 reg = <0xd 1>;
57 gpio-controller;
58 };
59 };