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David Gibsonea20ff52007-05-08 14:09:18 +10001/*
2 * Device Tree Source for IBM Ebony
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
David Gibsonea20ff52007-05-08 14:09:18 +100012 */
13
David Gibson71f34972008-05-15 16:46:39 +100014/dts-v1/;
15
David Gibsonea20ff52007-05-08 14:09:18 +100016/ {
17 #address-cells = <2>;
18 #size-cells = <1>;
19 model = "ibm,ebony";
20 compatible = "ibm,ebony";
David Gibson71f34972008-05-15 16:46:39 +100021 dcr-parent = <&{/cpus/cpu@0}>;
David Gibsonea20ff52007-05-08 14:09:18 +100022
Stefan Roese8aaed982007-12-15 18:55:16 +110023 aliases {
24 ethernet0 = &EMAC0;
25 ethernet1 = &EMAC1;
26 serial0 = &UART0;
27 serial1 = &UART1;
28 };
29
David Gibsonea20ff52007-05-08 14:09:18 +100030 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
Josh Boyer72fda112007-12-06 13:20:05 -060034 cpu@0 {
David Gibsonea20ff52007-05-08 14:09:18 +100035 device_type = "cpu";
Josh Boyer72fda112007-12-06 13:20:05 -060036 model = "PowerPC,440GP";
David Gibson71f34972008-05-15 16:46:39 +100037 reg = <0x00000000>;
David Gibsonea20ff52007-05-08 14:09:18 +100038 clock-frequency = <0>; // Filled in by zImage
39 timebase-frequency = <0>; // Filled in by zImage
David Gibson71f34972008-05-15 16:46:39 +100040 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>; /* 32 kB */
43 d-cache-size = <32768>; /* 32 kB */
David Gibsonea20ff52007-05-08 14:09:18 +100044 dcr-controller;
45 dcr-access-method = "native";
46 };
47 };
48
49 memory {
50 device_type = "memory";
David Gibson71f34972008-05-15 16:46:39 +100051 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
David Gibsonea20ff52007-05-08 14:09:18 +100052 };
53
54 UIC0: interrupt-controller0 {
David Gibsonea20ff52007-05-08 14:09:18 +100055 compatible = "ibm,uic-440gp", "ibm,uic";
56 interrupt-controller;
57 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +100058 dcr-reg = <0x0c0 0x009>;
David Gibsonea20ff52007-05-08 14:09:18 +100059 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62
63 };
64
65 UIC1: interrupt-controller1 {
David Gibsonea20ff52007-05-08 14:09:18 +100066 compatible = "ibm,uic-440gp", "ibm,uic";
67 interrupt-controller;
68 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +100069 dcr-reg = <0x0d0 0x009>;
David Gibsonea20ff52007-05-08 14:09:18 +100070 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100073 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
David Gibsonea20ff52007-05-08 14:09:18 +100074 interrupt-parent = <&UIC0>;
75 };
76
77 CPC0: cpc {
David Gibsonea20ff52007-05-08 14:09:18 +100078 compatible = "ibm,cpc-440gp";
David Gibson71f34972008-05-15 16:46:39 +100079 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
David Gibsonea20ff52007-05-08 14:09:18 +100080 // FIXME: anything else?
81 };
82
83 plb {
David Gibsonea20ff52007-05-08 14:09:18 +100084 compatible = "ibm,plb-440gp", "ibm,plb4";
85 #address-cells = <2>;
86 #size-cells = <1>;
87 ranges;
88 clock-frequency = <0>; // Filled in by zImage
89
David Gibsonc72ea772007-05-16 13:48:50 +100090 SDRAM0: memory-controller {
91 compatible = "ibm,sdram-440gp";
David Gibson71f34972008-05-15 16:46:39 +100092 dcr-reg = <0x010 0x002>;
David Gibsonea20ff52007-05-08 14:09:18 +100093 // FIXME: anything else?
94 };
95
David Gibsonc72ea772007-05-16 13:48:50 +100096 SRAM0: sram {
97 compatible = "ibm,sram-440gp";
David Gibson71f34972008-05-15 16:46:39 +100098 dcr-reg = <0x020 0x008 0x00a 0x001>;
David Gibsonc72ea772007-05-16 13:48:50 +100099 };
100
David Gibsonea20ff52007-05-08 14:09:18 +1000101 DMA0: dma {
102 // FIXME: ???
David Gibsonc72ea772007-05-16 13:48:50 +1000103 compatible = "ibm,dma-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000104 dcr-reg = <0x100 0x027>;
David Gibsonea20ff52007-05-08 14:09:18 +1000105 };
106
107 MAL0: mcmal {
David Gibsonea20ff52007-05-08 14:09:18 +1000108 compatible = "ibm,mcmal-440gp", "ibm,mcmal";
David Gibson71f34972008-05-15 16:46:39 +1000109 dcr-reg = <0x180 0x062>;
David Gibsonea20ff52007-05-08 14:09:18 +1000110 num-tx-chans = <4>;
111 num-rx-chans = <4>;
112 interrupt-parent = <&MAL0>;
David Gibson71f34972008-05-15 16:46:39 +1000113 interrupts = <0x0 0x1 0x2 0x3 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000114 #interrupt-cells = <1>;
115 #address-cells = <0>;
116 #size-cells = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000117 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
118 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
119 /*SERR*/ 0x2 &UIC1 0x0 0x4
120 /*TXDE*/ 0x3 &UIC1 0x1 0x4
121 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
122 interrupt-map-mask = <0xffffffff>;
David Gibsonea20ff52007-05-08 14:09:18 +1000123 };
124
125 POB0: opb {
David Gibsonea20ff52007-05-08 14:09:18 +1000126 compatible = "ibm,opb-440gp", "ibm,opb";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 /* Wish there was a nicer way of specifying a full 32-bit
130 range */
David Gibson71f34972008-05-15 16:46:39 +1000131 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
132 0x80000000 0x00000001 0x80000000 0x80000000>;
133 dcr-reg = <0x090 0x00b>;
David Gibsonea20ff52007-05-08 14:09:18 +1000134 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000135 interrupts = <0x7 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000136 clock-frequency = <0>; // Filled in by zImage
137
138 EBC0: ebc {
David Gibsonc72ea772007-05-16 13:48:50 +1000139 compatible = "ibm,ebc-440gp", "ibm,ebc";
David Gibson71f34972008-05-15 16:46:39 +1000140 dcr-reg = <0x012 0x002>;
David Gibsonea20ff52007-05-08 14:09:18 +1000141 #address-cells = <2>;
142 #size-cells = <1>;
143 clock-frequency = <0>; // Filled in by zImage
David Gibsonb2ba34f2007-06-13 14:52:59 +1000144 // ranges property is supplied by zImage
145 // based on firmware's configuration of the
146 // EBC bridge
David Gibson71f34972008-05-15 16:46:39 +1000147 interrupts = <0x5 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000148 interrupt-parent = <&UIC1>;
149
David Gibsonc72ea772007-05-16 13:48:50 +1000150 small-flash@0,80000 {
David Gibson20991722007-09-07 13:23:53 +1000151 compatible = "jedec-flash";
David Gibsonea20ff52007-05-08 14:09:18 +1000152 bank-width = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000153 reg = <0x00000000 0x00080000 0x00080000>;
David Gibson20991722007-09-07 13:23:53 +1000154 #address-cells = <1>;
155 #size-cells = <1>;
156 partition@0 {
157 label = "OpenBIOS";
David Gibson71f34972008-05-15 16:46:39 +1000158 reg = <0x00000000 0x00080000>;
David Gibson20991722007-09-07 13:23:53 +1000159 read-only;
160 };
David Gibsonea20ff52007-05-08 14:09:18 +1000161 };
162
David Gibson22258fa2008-01-11 14:25:34 +1100163 nvram@1,0 {
David Gibsonea20ff52007-05-08 14:09:18 +1000164 /* NVRAM & RTC */
David Gibson22258fa2008-01-11 14:25:34 +1100165 compatible = "ds1743-nvram";
David Gibson71f34972008-05-15 16:46:39 +1000166 #bytes = <0x2000>;
167 reg = <0x00000001 0x00000000 0x00002000>;
David Gibsonea20ff52007-05-08 14:09:18 +1000168 };
169
170 large-flash@2,0 {
David Gibson20991722007-09-07 13:23:53 +1000171 compatible = "jedec-flash";
David Gibsonea20ff52007-05-08 14:09:18 +1000172 bank-width = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000173 reg = <0x00000002 0x00000000 0x00400000>;
David Gibson20991722007-09-07 13:23:53 +1000174 #address-cells = <1>;
175 #size-cells = <1>;
176 partition@0 {
177 label = "fs";
David Gibson71f34972008-05-15 16:46:39 +1000178 reg = <0x00000000 0x00380000>;
David Gibson20991722007-09-07 13:23:53 +1000179 };
180 partition@380000 {
181 label = "firmware";
David Gibson71f34972008-05-15 16:46:39 +1000182 reg = <0x00380000 0x00080000>;
David Gibson20991722007-09-07 13:23:53 +1000183 };
David Gibsonea20ff52007-05-08 14:09:18 +1000184 };
185
186 ir@3,0 {
David Gibson71f34972008-05-15 16:46:39 +1000187 reg = <0x00000003 0x00000000 0x00000010>;
David Gibsonea20ff52007-05-08 14:09:18 +1000188 };
189
190 fpga@7,0 {
191 compatible = "Ebony-FPGA";
David Gibson71f34972008-05-15 16:46:39 +1000192 reg = <0x00000007 0x00000000 0x00000010>;
193 virtual-reg = <0xe8300000>;
David Gibsonea20ff52007-05-08 14:09:18 +1000194 };
195 };
196
197 UART0: serial@40000200 {
198 device_type = "serial";
199 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000200 reg = <0x40000200 0x00000008>;
201 virtual-reg = <0xe0000200>;
202 clock-frequency = <11059200>;
203 current-speed = <9600>;
David Gibsonea20ff52007-05-08 14:09:18 +1000204 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000205 interrupts = <0x0 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000206 };
207
208 UART1: serial@40000300 {
209 device_type = "serial";
210 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000211 reg = <0x40000300 0x00000008>;
212 virtual-reg = <0xe0000300>;
213 clock-frequency = <11059200>;
214 current-speed = <9600>;
David Gibsonea20ff52007-05-08 14:09:18 +1000215 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000216 interrupts = <0x1 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000217 };
218
219 IIC0: i2c@40000400 {
220 /* FIXME */
David Gibsonea20ff52007-05-08 14:09:18 +1000221 compatible = "ibm,iic-440gp", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000222 reg = <0x40000400 0x00000014>;
David Gibsonea20ff52007-05-08 14:09:18 +1000223 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000224 interrupts = <0x2 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000225 };
226 IIC1: i2c@40000500 {
227 /* FIXME */
David Gibsonea20ff52007-05-08 14:09:18 +1000228 compatible = "ibm,iic-440gp", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000229 reg = <0x40000500 0x00000014>;
David Gibsonea20ff52007-05-08 14:09:18 +1000230 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000231 interrupts = <0x3 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000232 };
233
234 GPIO0: gpio@40000700 {
235 /* FIXME */
David Gibsonea20ff52007-05-08 14:09:18 +1000236 compatible = "ibm,gpio-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000237 reg = <0x40000700 0x00000020>;
David Gibsonea20ff52007-05-08 14:09:18 +1000238 };
239
240 ZMII0: emac-zmii@40000780 {
David Gibsonea20ff52007-05-08 14:09:18 +1000241 compatible = "ibm,zmii-440gp", "ibm,zmii";
David Gibson71f34972008-05-15 16:46:39 +1000242 reg = <0x40000780 0x0000000c>;
David Gibsonea20ff52007-05-08 14:09:18 +1000243 };
244
245 EMAC0: ethernet@40000800 {
David Gibsonea20ff52007-05-08 14:09:18 +1000246 device_type = "network";
247 compatible = "ibm,emac-440gp", "ibm,emac";
248 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000249 interrupts = <0x1c 0x4 0x1d 0x4>;
250 reg = <0x40000800 0x00000070>;
David Gibsonea20ff52007-05-08 14:09:18 +1000251 local-mac-address = [000000000000]; // Filled in by zImage
252 mal-device = <&MAL0>;
253 mal-tx-channel = <0 1>;
254 mal-rx-channel = <0>;
255 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000256 max-frame-size = <1500>;
257 rx-fifo-size = <4096>;
258 tx-fifo-size = <2048>;
David Gibsonea20ff52007-05-08 14:09:18 +1000259 phy-mode = "rmii";
David Gibson71f34972008-05-15 16:46:39 +1000260 phy-map = <0x00000001>;
David Gibsonea20ff52007-05-08 14:09:18 +1000261 zmii-device = <&ZMII0>;
262 zmii-channel = <0>;
263 };
264 EMAC1: ethernet@40000900 {
David Gibsonea20ff52007-05-08 14:09:18 +1000265 device_type = "network";
266 compatible = "ibm,emac-440gp", "ibm,emac";
267 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000268 interrupts = <0x1e 0x4 0x1f 0x4>;
269 reg = <0x40000900 0x00000070>;
David Gibsonea20ff52007-05-08 14:09:18 +1000270 local-mac-address = [000000000000]; // Filled in by zImage
271 mal-device = <&MAL0>;
272 mal-tx-channel = <2 3>;
273 mal-rx-channel = <1>;
274 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000275 max-frame-size = <1500>;
276 rx-fifo-size = <4096>;
277 tx-fifo-size = <2048>;
David Gibsonea20ff52007-05-08 14:09:18 +1000278 phy-mode = "rmii";
David Gibson71f34972008-05-15 16:46:39 +1000279 phy-map = <0x00000001>;
David Gibsonea20ff52007-05-08 14:09:18 +1000280 zmii-device = <&ZMII0>;
281 zmii-channel = <1>;
282 };
283
284
285 GPT0: gpt@40000a00 {
286 /* FIXME */
David Gibson71f34972008-05-15 16:46:39 +1000287 reg = <0x40000a00 0x000000d4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000288 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000289 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
David Gibsonea20ff52007-05-08 14:09:18 +1000290 };
291
292 };
293
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100294 PCIX0: pci@20ec00000 {
David Gibsonea20ff52007-05-08 14:09:18 +1000295 device_type = "pci";
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100296 #interrupt-cells = <1>;
297 #size-cells = <2>;
298 #address-cells = <3>;
299 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
300 primary;
David Gibson71f34972008-05-15 16:46:39 +1000301 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
302 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
303 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
304 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
305 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100306
307 /* Outbound ranges, one memory and one IO,
308 * later cannot be changed
309 */
David Gibson71f34972008-05-15 16:46:39 +1000310 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
311 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100312
313 /* Inbound 2GB range starting at 0 */
David Gibson71f34972008-05-15 16:46:39 +1000314 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100315
316 /* Ebony has all 4 IRQ pins tied together per slot */
David Gibson71f34972008-05-15 16:46:39 +1000317 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100318 interrupt-map = <
319 /* IDSEL 1 */
David Gibson71f34972008-05-15 16:46:39 +1000320 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100321
322 /* IDSEL 2 */
David Gibson71f34972008-05-15 16:46:39 +1000323 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100324
325 /* IDSEL 3 */
David Gibson71f34972008-05-15 16:46:39 +1000326 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100327
328 /* IDSEL 4 */
David Gibson71f34972008-05-15 16:46:39 +1000329 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
Benjamin Herrenschmidt69c07852007-12-21 15:39:25 +1100330 >;
David Gibsonea20ff52007-05-08 14:09:18 +1000331 };
332 };
333
334 chosen {
335 linux,stdout-path = "/plb/opb/serial@40000200";
David Gibsonea20ff52007-05-08 14:09:18 +1000336 };
337};