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review.evervolv.com / android_kernel_htc_msm8960 / d463003b56776576b071c4fcfdf391f4bb32d21c / . / drivers / media / video / ov2640.c
blob: 78bf602296f743dbd0e2834e4b34c40ea6c3fdce [file] [log] [blame]
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]1/*
2 * ov2640 Camera Driver
3 *
4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 *
6 * Based on ov772x, ov9640 drivers and previous non merged implementations.
7 *
8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright (C) 2006, OmniVision
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/i2c.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/videodev2.h>
Guennadi Liakhovetskid4630032011-07-26 11:59:53 -0300[diff] [blame^]22
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]23#include <media/soc_camera.h>
24#include <media/soc_mediabus.h>
Guennadi Liakhovetskid4630032011-07-26 11:59:53 -0300[diff] [blame^]25#include <media/v4l2-chip-ident.h>
26#include <media/v4l2-subdev.h>
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]27
28#define VAL_SET(x, mask, rshift, lshift) \
29 ((((x) >> rshift) & mask) << lshift)
30/*
31 * DSP registers
32 * register offset for BANK_SEL == BANK_SEL_DSP
33 */
34#define R_BYPASS 0x05 /* Bypass DSP */
35#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
36#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
37#define QS 0x44 /* Quantization Scale Factor */
38#define CTRLI 0x50
39#define CTRLI_LP_DP 0x80
40#define CTRLI_ROUND 0x40
41#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
42#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
43#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
44#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
45#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
46#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
47#define XOFFL 0x53 /* OFFSET_X[7:0] */
48#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
49#define YOFFL 0x54 /* OFFSET_Y[7:0] */
50#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
51#define VHYX 0x55 /* Offset and size completion */
52#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
53#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
54#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
55#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
56#define DPRP 0x56
57#define TEST 0x57 /* Horizontal size completion */
58#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
59#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
60#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
61#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
62#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
63#define ZMHH 0x5C /* Zoom: Speed and H&W completion */
64#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
65#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
66#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
67#define BPADDR 0x7C /* SDE Indirect Register Access: Address */
68#define BPDATA 0x7D /* SDE Indirect Register Access: Data */
69#define CTRL2 0x86 /* DSP Module enable 2 */
70#define CTRL2_DCW_EN 0x20
71#define CTRL2_SDE_EN 0x10
72#define CTRL2_UV_ADJ_EN 0x08
73#define CTRL2_UV_AVG_EN 0x04
74#define CTRL2_CMX_EN 0x01
75#define CTRL3 0x87 /* DSP Module enable 3 */
76#define CTRL3_BPC_EN 0x80
77#define CTRL3_WPC_EN 0x40
78#define SIZEL 0x8C /* Image Size Completion */
79#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
80#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
81#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
82#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
83#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
84#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
85#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
86#define CTRL0 0xC2 /* DSP Module enable 0 */
87#define CTRL0_AEC_EN 0x80
88#define CTRL0_AEC_SEL 0x40
89#define CTRL0_STAT_SEL 0x20
90#define CTRL0_VFIRST 0x10
91#define CTRL0_YUV422 0x08
92#define CTRL0_YUV_EN 0x04
93#define CTRL0_RGB_EN 0x02
94#define CTRL0_RAW_EN 0x01
95#define CTRL1 0xC3 /* DSP Module enable 1 */
96#define CTRL1_CIP 0x80
97#define CTRL1_DMY 0x40
98#define CTRL1_RAW_GMA 0x20
99#define CTRL1_DG 0x10
100#define CTRL1_AWB 0x08
101#define CTRL1_AWB_GAIN 0x04
102#define CTRL1_LENC 0x02
103#define CTRL1_PRE 0x01
104#define R_DVP_SP 0xD3 /* DVP output speed control */
105#define R_DVP_SP_AUTO_MODE 0x80
106#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
107 * = sysclk (48)/(2*[6:0]) (RAW);*/
108#define IMAGE_MODE 0xDA /* Image Output Format Select */
109#define IMAGE_MODE_Y8_DVP_EN 0x40
110#define IMAGE_MODE_JPEG_EN 0x10
111#define IMAGE_MODE_YUV422 0x00
112#define IMAGE_MODE_RAW10 0x04 /* (DVP) */
113#define IMAGE_MODE_RGB565 0x08
114#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
115 * mode (0 for HREF is same as sensor) */
116#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
117 * 1: Low byte first UYVY (C2[4] =0)
118 * VYUY (C2[4] =1)
119 * 0: High byte first YUYV (C2[4]=0)
120 * YVYU (C2[4] = 1) */
121#define RESET 0xE0 /* Reset */
122#define RESET_MICROC 0x40
123#define RESET_SCCB 0x20
124#define RESET_JPEG 0x10
125#define RESET_DVP 0x04
126#define RESET_IPU 0x02
127#define RESET_CIF 0x01
128#define REGED 0xED /* Register ED */
129#define REGED_CLK_OUT_DIS 0x10
130#define MS_SP 0xF0 /* SCCB Master Speed */
131#define SS_ID 0xF7 /* SCCB Slave ID */
132#define SS_CTRL 0xF8 /* SCCB Slave Control */
133#define SS_CTRL_ADD_AUTO_INC 0x20
134#define SS_CTRL_EN 0x08
135#define SS_CTRL_DELAY_CLK 0x04
136#define SS_CTRL_ACC_EN 0x02
137#define SS_CTRL_SEN_PASS_THR 0x01
138#define MC_BIST 0xF9 /* Microcontroller misc register */
139#define MC_BIST_RESET 0x80 /* Microcontroller Reset */
140#define MC_BIST_BOOT_ROM_SEL 0x40
141#define MC_BIST_12KB_SEL 0x20
142#define MC_BIST_12KB_MASK 0x30
143#define MC_BIST_512KB_SEL 0x08
144#define MC_BIST_512KB_MASK 0x0C
145#define MC_BIST_BUSY_BIT_R 0x02
146#define MC_BIST_MC_RES_ONE_SH_W 0x02
147#define MC_BIST_LAUNCH 0x01
148#define BANK_SEL 0xFF /* Register Bank Select */
149#define BANK_SEL_DSP 0x00
150#define BANK_SEL_SENS 0x01
151
152/*
153 * Sensor registers
154 * register offset for BANK_SEL == BANK_SEL_SENS
155 */
156#define GAIN 0x00 /* AGC - Gain control gain setting */
157#define COM1 0x03 /* Common control 1 */
158#define COM1_1_DUMMY_FR 0x40
159#define COM1_3_DUMMY_FR 0x80
160#define COM1_7_DUMMY_FR 0xC0
161#define COM1_VWIN_LSB_UXGA 0x0F
162#define COM1_VWIN_LSB_SVGA 0x0A
163#define COM1_VWIN_LSB_CIF 0x06
164#define REG04 0x04 /* Register 04 */
165#define REG04_DEF 0x20 /* Always set */
166#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
167#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
168#define REG04_VREF_EN 0x10
169#define REG04_HREF_EN 0x08
170#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
171#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
172#define COM2 0x09 /* Common control 2 */
173#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
174 /* Output drive capability */
175#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
176#define PID 0x0A /* Product ID Number MSB */
177#define VER 0x0B /* Product ID Number LSB */
178#define COM3 0x0C /* Common control 3 */
179#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
180#define COM3_BAND_AUTO 0x02 /* Auto Banding */
181#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
182 * snapshot sequence*/
183#define AEC 0x10 /* AEC[9:2] Exposure Value */
184#define CLKRC 0x11 /* Internal clock */
185#define CLKRC_EN 0x80
186#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
187#define COM7 0x12 /* Common control 7 */
188#define COM7_SRST 0x80 /* Initiates system reset. All registers are
189 * set to factory default values after which
190 * the chip resumes normal operation */
191#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
192#define COM7_RES_SVGA 0x40 /* SVGA */
193#define COM7_RES_CIF 0x20 /* CIF */
194#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
195#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
196#define COM8 0x13 /* Common control 8 */
197#define COM8_DEF 0xC0 /* Banding filter ON/OFF */
198#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
199#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
200#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
201#define COM9 0x14 /* Common control 9
202 * Automatic gain ceiling - maximum AGC value [7:5]*/
203#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
204#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
205#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
206#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
207#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
208#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
209#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
210#define COM10 0x15 /* Common control 10 */
211#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
212#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
213 * PCLK (user can latch data at the next
214 * falling edge of PCLK).
215 * 0 otherwise. */
216#define COM10_HREF_INV 0x08 /* Invert HREF polarity:
217 * HREF negative for valid data*/
218#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
219#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
220#define HEND 0x18 /* Horizontal Window end MSB 8 bit */
221#define VSTART 0x19 /* Vertical Window start MSB 8 bit */
222#define VEND 0x1A /* Vertical Window end MSB 8 bit */
223#define MIDH 0x1C /* Manufacturer ID byte - high */
224#define MIDL 0x1D /* Manufacturer ID byte - low */
225#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
226#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
227#define VV 0x26 /* AGC/AEC Fast mode operating region */
228#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
229#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
230#define REG2A 0x2A /* Dummy pixel insert MSB */
231#define FRARL 0x2B /* Dummy pixel insert LSB */
232#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
233#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
234#define YAVG 0x2F /* Y/G Channel Average value */
235#define REG32 0x32 /* Common Control 32 */
236#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
237#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
238#define ARCOM2 0x34 /* Zoom: Horizontal start point */
239#define REG45 0x45 /* Register 45 */
240#define FLL 0x46 /* Frame Length Adjustment LSBs */
241#define FLH 0x47 /* Frame Length Adjustment MSBs */
242#define COM19 0x48 /* Zoom: Vertical start point */
243#define ZOOMS 0x49 /* Zoom: Vertical start point */
244#define COM22 0x4B /* Flash light control */
245#define COM25 0x4E /* For Banding operations */
246#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
247#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
248#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
249#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
250#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
251#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
252#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
253#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
254
255/*
256 * ID
257 */
258#define MANUFACTURER_ID 0x7FA2
259#define PID_OV2640 0x2642
260#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
261
262/*
263 * Struct
264 */
265struct regval_list {
266 u8 reg_num;
267 u8 value;
268};
269
270/* Supported resolutions */
271enum ov2640_width {
272 W_QCIF = 176,
273 W_QVGA = 320,
274 W_CIF = 352,
275 W_VGA = 640,
276 W_SVGA = 800,
277 W_XGA = 1024,
278 W_SXGA = 1280,
279 W_UXGA = 1600,
280};
281
282enum ov2640_height {
283 H_QCIF = 144,
284 H_QVGA = 240,
285 H_CIF = 288,
286 H_VGA = 480,
287 H_SVGA = 600,
288 H_XGA = 768,
289 H_SXGA = 1024,
290 H_UXGA = 1200,
291};
292
293struct ov2640_win_size {
294 char *name;
295 enum ov2640_width width;
296 enum ov2640_height height;
297 const struct regval_list *regs;
298};
299
300
301struct ov2640_priv {
302 struct v4l2_subdev subdev;
303 struct ov2640_camera_info *info;
304 enum v4l2_mbus_pixelcode cfmt_code;
305 const struct ov2640_win_size *win;
306 int model;
307 u16 flag_vflip:1;
308 u16 flag_hflip:1;
309};
310
311/*
312 * Registers settings
313 */
314
315#define ENDMARKER { 0xff, 0xff }
316
317static const struct regval_list ov2640_init_regs[] = {
318 { BANK_SEL, BANK_SEL_DSP },
319 { 0x2c, 0xff },
320 { 0x2e, 0xdf },
321 { BANK_SEL, BANK_SEL_SENS },
322 { 0x3c, 0x32 },
323 { CLKRC, CLKRC_DIV_SET(1) },
324 { COM2, COM2_OCAP_Nx_SET(3) },
325 { REG04, REG04_DEF | REG04_HREF_EN },
326 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
327 { COM9, COM9_AGC_GAIN_8x | 0x08},
328 { 0x2c, 0x0c },
329 { 0x33, 0x78 },
330 { 0x3a, 0x33 },
331 { 0x3b, 0xfb },
332 { 0x3e, 0x00 },
333 { 0x43, 0x11 },
334 { 0x16, 0x10 },
335 { 0x39, 0x02 },
336 { 0x35, 0x88 },
337 { 0x22, 0x0a },
338 { 0x37, 0x40 },
339 { 0x23, 0x00 },
340 { ARCOM2, 0xa0 },
341 { 0x06, 0x02 },
342 { 0x06, 0x88 },
343 { 0x07, 0xc0 },
344 { 0x0d, 0xb7 },
345 { 0x0e, 0x01 },
346 { 0x4c, 0x00 },
347 { 0x4a, 0x81 },
348 { 0x21, 0x99 },
349 { AEW, 0x40 },
350 { AEB, 0x38 },
351 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
352 { 0x5c, 0x00 },
353 { 0x63, 0x00 },
354 { FLL, 0x22 },
355 { COM3, 0x38 | COM3_BAND_AUTO },
356 { REG5D, 0x55 },
357 { REG5E, 0x7d },
358 { REG5F, 0x7d },
359 { REG60, 0x55 },
360 { HISTO_LOW, 0x70 },
361 { HISTO_HIGH, 0x80 },
362 { 0x7c, 0x05 },
363 { 0x20, 0x80 },
364 { 0x28, 0x30 },
365 { 0x6c, 0x00 },
366 { 0x6d, 0x80 },
367 { 0x6e, 0x00 },
368 { 0x70, 0x02 },
369 { 0x71, 0x94 },
370 { 0x73, 0xc1 },
371 { 0x3d, 0x34 },
372 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
373 { 0x5a, 0x57 },
374 { BD50, 0xbb },
375 { BD60, 0x9c },
376 { BANK_SEL, BANK_SEL_DSP },
377 { 0xe5, 0x7f },
378 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
379 { 0x41, 0x24 },
380 { RESET, RESET_JPEG | RESET_DVP },
381 { 0x76, 0xff },
382 { 0x33, 0xa0 },
383 { 0x42, 0x20 },
384 { 0x43, 0x18 },
385 { 0x4c, 0x00 },
386 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
387 { 0x88, 0x3f },
388 { 0xd7, 0x03 },
389 { 0xd9, 0x10 },
390 { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
391 { 0xc8, 0x08 },
392 { 0xc9, 0x80 },
393 { BPADDR, 0x00 },
394 { BPDATA, 0x00 },
395 { BPADDR, 0x03 },
396 { BPDATA, 0x48 },
397 { BPDATA, 0x48 },
398 { BPADDR, 0x08 },
399 { BPDATA, 0x20 },
400 { BPDATA, 0x10 },
401 { BPDATA, 0x0e },
402 { 0x90, 0x00 },
403 { 0x91, 0x0e },
404 { 0x91, 0x1a },
405 { 0x91, 0x31 },
406 { 0x91, 0x5a },
407 { 0x91, 0x69 },
408 { 0x91, 0x75 },
409 { 0x91, 0x7e },
410 { 0x91, 0x88 },
411 { 0x91, 0x8f },
412 { 0x91, 0x96 },
413 { 0x91, 0xa3 },
414 { 0x91, 0xaf },
415 { 0x91, 0xc4 },
416 { 0x91, 0xd7 },
417 { 0x91, 0xe8 },
418 { 0x91, 0x20 },
419 { 0x92, 0x00 },
420 { 0x93, 0x06 },
421 { 0x93, 0xe3 },
422 { 0x93, 0x03 },
423 { 0x93, 0x03 },
424 { 0x93, 0x00 },
425 { 0x93, 0x02 },
426 { 0x93, 0x00 },
427 { 0x93, 0x00 },
428 { 0x93, 0x00 },
429 { 0x93, 0x00 },
430 { 0x93, 0x00 },
431 { 0x93, 0x00 },
432 { 0x93, 0x00 },
433 { 0x96, 0x00 },
434 { 0x97, 0x08 },
435 { 0x97, 0x19 },
436 { 0x97, 0x02 },
437 { 0x97, 0x0c },
438 { 0x97, 0x24 },
439 { 0x97, 0x30 },
440 { 0x97, 0x28 },
441 { 0x97, 0x26 },
442 { 0x97, 0x02 },
443 { 0x97, 0x98 },
444 { 0x97, 0x80 },
445 { 0x97, 0x00 },
446 { 0x97, 0x00 },
447 { 0xa4, 0x00 },
448 { 0xa8, 0x00 },
449 { 0xc5, 0x11 },
450 { 0xc6, 0x51 },
451 { 0xbf, 0x80 },
452 { 0xc7, 0x10 },
453 { 0xb6, 0x66 },
454 { 0xb8, 0xA5 },
455 { 0xb7, 0x64 },
456 { 0xb9, 0x7C },
457 { 0xb3, 0xaf },
458 { 0xb4, 0x97 },
459 { 0xb5, 0xFF },
460 { 0xb0, 0xC5 },
461 { 0xb1, 0x94 },
462 { 0xb2, 0x0f },
463 { 0xc4, 0x5c },
464 { 0xa6, 0x00 },
465 { 0xa7, 0x20 },
466 { 0xa7, 0xd8 },
467 { 0xa7, 0x1b },
468 { 0xa7, 0x31 },
469 { 0xa7, 0x00 },
470 { 0xa7, 0x18 },
471 { 0xa7, 0x20 },
472 { 0xa7, 0xd8 },
473 { 0xa7, 0x19 },
474 { 0xa7, 0x31 },
475 { 0xa7, 0x00 },
476 { 0xa7, 0x18 },
477 { 0xa7, 0x20 },
478 { 0xa7, 0xd8 },
479 { 0xa7, 0x19 },
480 { 0xa7, 0x31 },
481 { 0xa7, 0x00 },
482 { 0xa7, 0x18 },
483 { 0x7f, 0x00 },
484 { 0xe5, 0x1f },
485 { 0xe1, 0x77 },
486 { 0xdd, 0x7f },
487 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
488 ENDMARKER,
489};
490
491/*
492 * Register settings for window size
493 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
494 * Then the different zooming configurations will setup the output image size.
495 */
496static const struct regval_list ov2640_size_change_preamble_regs[] = {
497 { BANK_SEL, BANK_SEL_DSP },
498 { RESET, RESET_DVP },
499 { HSIZE8, HSIZE8_SET(W_UXGA) },
500 { VSIZE8, VSIZE8_SET(H_UXGA) },
501 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
502 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
503 { HSIZE, HSIZE_SET(W_UXGA) },
504 { VSIZE, VSIZE_SET(H_UXGA) },
505 { XOFFL, XOFFL_SET(0) },
506 { YOFFL, YOFFL_SET(0) },
507 { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) |
508 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
509 { TEST, TEST_HSIZE_SET(W_UXGA) },
510 ENDMARKER,
511};
512
513#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
514 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
515 CTRLI_H_DIV_SET(h_div)}, \
516 { ZMOW, ZMOW_OUTW_SET(x) }, \
517 { ZMOH, ZMOH_OUTH_SET(y) }, \
518 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
519 { R_DVP_SP, pclk_div }, \
520 { RESET, 0x00}
521
522static const struct regval_list ov2640_qcif_regs[] = {
523 PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4),
524 ENDMARKER,
525};
526
527static const struct regval_list ov2640_qvga_regs[] = {
528 PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4),
529 ENDMARKER,
530};
531
532static const struct regval_list ov2640_cif_regs[] = {
533 PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8),
534 ENDMARKER,
535};
536
537static const struct regval_list ov2640_vga_regs[] = {
538 PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2),
539 ENDMARKER,
540};
541
542static const struct regval_list ov2640_svga_regs[] = {
543 PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2),
544 ENDMARKER,
545};
546
547static const struct regval_list ov2640_xga_regs[] = {
548 PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2),
549 { CTRLI, 0x00},
550 ENDMARKER,
551};
552
553static const struct regval_list ov2640_sxga_regs[] = {
554 PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2),
555 { CTRLI, 0x00},
556 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
557 ENDMARKER,
558};
559
560static const struct regval_list ov2640_uxga_regs[] = {
561 PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0),
562 { CTRLI, 0x00},
563 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
564 ENDMARKER,
565};
566
567#define OV2640_SIZE(n, w, h, r) \
568 {.name = n, .width = w , .height = h, .regs = r }
569
570static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
571 OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs),
572 OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs),
573 OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs),
574 OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs),
575 OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs),
576 OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs),
577 OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs),
578 OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs),
579};
580
581/*
582 * Register settings for pixel formats
583 */
584static const struct regval_list ov2640_format_change_preamble_regs[] = {
585 { BANK_SEL, BANK_SEL_DSP },
586 { R_BYPASS, R_BYPASS_USE_DSP },
587 ENDMARKER,
588};
589
590static const struct regval_list ov2640_yuv422_regs[] = {
591 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
592 { 0xD7, 0x01 },
593 { 0x33, 0xa0 },
594 { 0xe1, 0x67 },
595 { RESET, 0x00 },
596 { R_BYPASS, R_BYPASS_USE_DSP },
597 ENDMARKER,
598};
599
600static const struct regval_list ov2640_rgb565_regs[] = {
601 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
602 { 0xd7, 0x03 },
603 { RESET, 0x00 },
604 { R_BYPASS, R_BYPASS_USE_DSP },
605 ENDMARKER,
606};
607
608static enum v4l2_mbus_pixelcode ov2640_codes[] = {
609 V4L2_MBUS_FMT_UYVY8_2X8,
610 V4L2_MBUS_FMT_RGB565_2X8_LE,
611};
612
613/*
614 * Supported controls
615 */
616static const struct v4l2_queryctrl ov2640_controls[] = {
617 {
618 .id = V4L2_CID_VFLIP,
619 .type = V4L2_CTRL_TYPE_BOOLEAN,
620 .name = "Flip Vertically",
621 .minimum = 0,
622 .maximum = 1,
623 .step = 1,
624 .default_value = 0,
625 }, {
626 .id = V4L2_CID_HFLIP,
627 .type = V4L2_CTRL_TYPE_BOOLEAN,
628 .name = "Flip Horizontally",
629 .minimum = 0,
630 .maximum = 1,
631 .step = 1,
632 .default_value = 0,
633 },
634};
635
636/*
637 * General functions
638 */
639static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
640{
641 return container_of(i2c_get_clientdata(client), struct ov2640_priv,
642 subdev);
643}
644
645static int ov2640_write_array(struct i2c_client *client,
646 const struct regval_list *vals)
647{
648 int ret;
649
650 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
651 ret = i2c_smbus_write_byte_data(client,
652 vals->reg_num, vals->value);
653 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
654 vals->reg_num, vals->value);
655
656 if (ret < 0)
657 return ret;
658 vals++;
659 }
660 return 0;
661}
662
663static int ov2640_mask_set(struct i2c_client *client,
664 u8 reg, u8 mask, u8 set)
665{
666 s32 val = i2c_smbus_read_byte_data(client, reg);
667 if (val < 0)
668 return val;
669
670 val &= ~mask;
671 val |= set & mask;
672
673 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
674
675 return i2c_smbus_write_byte_data(client, reg, val);
676}
677
678static int ov2640_reset(struct i2c_client *client)
679{
680 int ret;
681 const struct regval_list reset_seq[] = {
682 {BANK_SEL, BANK_SEL_SENS},
683 {COM7, COM7_SRST},
684 ENDMARKER,
685 };
686
687 ret = ov2640_write_array(client, reset_seq);
688 if (ret)
689 goto err;
690
691 msleep(5);
692err:
693 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
694 return ret;
695}
696
697/*
698 * soc_camera_ops functions
699 */
700static int ov2640_s_stream(struct v4l2_subdev *sd, int enable)
701{
702 return 0;
703}
704
705static int ov2640_set_bus_param(struct soc_camera_device *icd,
706 unsigned long flags)
707{
708 struct soc_camera_link *icl = to_soc_camera_link(icd);
709 unsigned long width_flag = flags & SOCAM_DATAWIDTH_MASK;
710
711 /* Only one width bit may be set */
712 if (!is_power_of_2(width_flag))
713 return -EINVAL;
714
715 if (icl->set_bus_param)
716 return icl->set_bus_param(icl, width_flag);
717
718 /*
719 * Without board specific bus width settings we support only the
720 * sensors native bus width witch are tested working
721 */
722 if (width_flag & (SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8))
723 return 0;
724
725 return 0;
726}
727
728static unsigned long ov2640_query_bus_param(struct soc_camera_device *icd)
729{
730 struct soc_camera_link *icl = to_soc_camera_link(icd);
731 unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
732 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
733 SOCAM_DATA_ACTIVE_HIGH;
734
735 if (icl->query_bus_param)
736 flags |= icl->query_bus_param(icl) & SOCAM_DATAWIDTH_MASK;
737 else
738 flags |= SOCAM_DATAWIDTH_10;
739
740 return soc_camera_apply_sensor_flags(icl, flags);
741}
742
743static int ov2640_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
744{
745 struct i2c_client *client = v4l2_get_subdevdata(sd);
746 struct ov2640_priv *priv = to_ov2640(client);
747
748 switch (ctrl->id) {
749 case V4L2_CID_VFLIP:
750 ctrl->value = priv->flag_vflip;
751 break;
752 case V4L2_CID_HFLIP:
753 ctrl->value = priv->flag_hflip;
754 break;
755 }
756 return 0;
757}
758
759static int ov2640_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
760{
761 struct i2c_client *client = v4l2_get_subdevdata(sd);
762 struct ov2640_priv *priv = to_ov2640(client);
763 int ret = 0;
764 u8 val;
765
766 switch (ctrl->id) {
767 case V4L2_CID_VFLIP:
768 val = ctrl->value ? REG04_VFLIP_IMG : 0x00;
769 priv->flag_vflip = ctrl->value ? 1 : 0;
770 ret = ov2640_mask_set(client, REG04, REG04_VFLIP_IMG, val);
771 break;
772 case V4L2_CID_HFLIP:
773 val = ctrl->value ? REG04_HFLIP_IMG : 0x00;
774 priv->flag_hflip = ctrl->value ? 1 : 0;
775 ret = ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
776 break;
777 }
778
779 return ret;
780}
781
782static int ov2640_g_chip_ident(struct v4l2_subdev *sd,
783 struct v4l2_dbg_chip_ident *id)
784{
785 struct i2c_client *client = v4l2_get_subdevdata(sd);
786 struct ov2640_priv *priv = to_ov2640(client);
787
788 id->ident = priv->model;
789 id->revision = 0;
790
791 return 0;
792}
793
794#ifdef CONFIG_VIDEO_ADV_DEBUG
795static int ov2640_g_register(struct v4l2_subdev *sd,
796 struct v4l2_dbg_register *reg)
797{
798 struct i2c_client *client = v4l2_get_subdevdata(sd);
799 int ret;
800
801 reg->size = 1;
802 if (reg->reg > 0xff)
803 return -EINVAL;
804
805 ret = i2c_smbus_read_byte_data(client, reg->reg);
806 if (ret < 0)
807 return ret;
808
809 reg->val = ret;
810
811 return 0;
812}
813
814static int ov2640_s_register(struct v4l2_subdev *sd,
815 struct v4l2_dbg_register *reg)
816{
817 struct i2c_client *client = v4l2_get_subdevdata(sd);
818
819 if (reg->reg > 0xff ||
820 reg->val > 0xff)
821 return -EINVAL;
822
823 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
824}
825#endif
826
827/* Select the nearest higher resolution for capture */
828static const struct ov2640_win_size *ov2640_select_win(u32 *width, u32 *height)
829{
830 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
831
832 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
833 if (ov2640_supported_win_sizes[i].width >= *width &&
834 ov2640_supported_win_sizes[i].height >= *height) {
835 *width = ov2640_supported_win_sizes[i].width;
836 *height = ov2640_supported_win_sizes[i].height;
837 return &ov2640_supported_win_sizes[i];
838 }
839 }
840
841 *width = ov2640_supported_win_sizes[default_size].width;
842 *height = ov2640_supported_win_sizes[default_size].height;
843 return &ov2640_supported_win_sizes[default_size];
844}
845
846static int ov2640_set_params(struct i2c_client *client, u32 *width, u32 *height,
847 enum v4l2_mbus_pixelcode code)
848{
849 struct ov2640_priv *priv = to_ov2640(client);
850 const struct regval_list *selected_cfmt_regs;
851 int ret;
852
853 /* select win */
854 priv->win = ov2640_select_win(width, height);
855
856 /* select format */
857 priv->cfmt_code = 0;
858 switch (code) {
859 case V4L2_MBUS_FMT_RGB565_2X8_LE:
860 dev_dbg(&client->dev, "%s: Selected cfmt RGB565", __func__);
861 selected_cfmt_regs = ov2640_rgb565_regs;
862 break;
863 default:
864 case V4L2_MBUS_FMT_UYVY8_2X8:
865 dev_dbg(&client->dev, "%s: Selected cfmt YUV422", __func__);
866 selected_cfmt_regs = ov2640_yuv422_regs;
867 }
868
869 /* reset hardware */
870 ov2640_reset(client);
871
872 /* initialize the sensor with default data */
873 dev_dbg(&client->dev, "%s: Init default", __func__);
874 ret = ov2640_write_array(client, ov2640_init_regs);
875 if (ret < 0)
876 goto err;
877
878 /* select preamble */
879 dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name);
880 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
881 if (ret < 0)
882 goto err;
883
884 /* set size win */
885 ret = ov2640_write_array(client, priv->win->regs);
886 if (ret < 0)
887 goto err;
888
889 /* cfmt preamble */
890 dev_dbg(&client->dev, "%s: Set cfmt", __func__);
891 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
892 if (ret < 0)
893 goto err;
894
895 /* set cfmt */
896 ret = ov2640_write_array(client, selected_cfmt_regs);
897 if (ret < 0)
898 goto err;
899
900 priv->cfmt_code = code;
901 *width = priv->win->width;
902 *height = priv->win->height;
903
904 return 0;
905
906err:
907 dev_err(&client->dev, "%s: Error %d", __func__, ret);
908 ov2640_reset(client);
909 priv->win = NULL;
910
911 return ret;
912}
913
914static int ov2640_g_fmt(struct v4l2_subdev *sd,
915 struct v4l2_mbus_framefmt *mf)
916{
917 struct i2c_client *client = v4l2_get_subdevdata(sd);
918 struct ov2640_priv *priv = to_ov2640(client);
919
920 if (!priv->win) {
921 u32 width = W_SVGA, height = H_SVGA;
922 int ret = ov2640_set_params(client, &width, &height,
923 V4L2_MBUS_FMT_UYVY8_2X8);
924 if (ret < 0)
925 return ret;
926 }
927
928 mf->width = priv->win->width;
929 mf->height = priv->win->height;
930 mf->code = priv->cfmt_code;
931
932 switch (mf->code) {
933 case V4L2_MBUS_FMT_RGB565_2X8_LE:
934 mf->colorspace = V4L2_COLORSPACE_SRGB;
935 break;
936 default:
937 case V4L2_MBUS_FMT_UYVY8_2X8:
938 mf->colorspace = V4L2_COLORSPACE_JPEG;
939 }
940 mf->field = V4L2_FIELD_NONE;
941
942 return 0;
943}
944
945static int ov2640_s_fmt(struct v4l2_subdev *sd,
946 struct v4l2_mbus_framefmt *mf)
947{
948 struct i2c_client *client = v4l2_get_subdevdata(sd);
949 int ret;
950
951
952 switch (mf->code) {
953 case V4L2_MBUS_FMT_RGB565_2X8_LE:
954 mf->colorspace = V4L2_COLORSPACE_SRGB;
955 break;
956 default:
957 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
958 case V4L2_MBUS_FMT_UYVY8_2X8:
959 mf->colorspace = V4L2_COLORSPACE_JPEG;
960 }
961
962 ret = ov2640_set_params(client, &mf->width, &mf->height, mf->code);
963
964 return ret;
965}
966
967static int ov2640_try_fmt(struct v4l2_subdev *sd,
968 struct v4l2_mbus_framefmt *mf)
969{
970 const struct ov2640_win_size *win;
971
972 /*
973 * select suitable win
974 */
975 win = ov2640_select_win(&mf->width, &mf->height);
976
977 mf->field = V4L2_FIELD_NONE;
978
979 switch (mf->code) {
980 case V4L2_MBUS_FMT_RGB565_2X8_LE:
981 mf->colorspace = V4L2_COLORSPACE_SRGB;
982 break;
983 default:
984 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
985 case V4L2_MBUS_FMT_UYVY8_2X8:
986 mf->colorspace = V4L2_COLORSPACE_JPEG;
987 }
988
989 return 0;
990}
991
992static int ov2640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
993 enum v4l2_mbus_pixelcode *code)
994{
995 if (index >= ARRAY_SIZE(ov2640_codes))
996 return -EINVAL;
997
998 *code = ov2640_codes[index];
999 return 0;
1000}
1001
1002static int ov2640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
1003{
1004 a->c.left = 0;
1005 a->c.top = 0;
1006 a->c.width = W_UXGA;
1007 a->c.height = H_UXGA;
1008 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1009
1010 return 0;
1011}
1012
1013static int ov2640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
1014{
1015 a->bounds.left = 0;
1016 a->bounds.top = 0;
1017 a->bounds.width = W_UXGA;
1018 a->bounds.height = H_UXGA;
1019 a->defrect = a->bounds;
1020 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1021 a->pixelaspect.numerator = 1;
1022 a->pixelaspect.denominator = 1;
1023
1024 return 0;
1025}
1026
1027static int ov2640_video_probe(struct soc_camera_device *icd,
1028 struct i2c_client *client)
1029{
1030 struct ov2640_priv *priv = to_ov2640(client);
1031 u8 pid, ver, midh, midl;
1032 const char *devname;
1033 int ret;
1034
Guennadi Liakhovetski7dfff952011-07-15 20:03:38 -0300[diff] [blame]1035 /* We must have a parent by now. And it cannot be a wrong one. */
1036 BUG_ON(!icd->parent ||
1037 to_soc_camera_host(icd->parent)->nr != icd->iface);
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]1038
1039 /*
1040 * check and show product ID and manufacturer ID
1041 */
1042 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
1043 pid = i2c_smbus_read_byte_data(client, PID);
1044 ver = i2c_smbus_read_byte_data(client, VER);
1045 midh = i2c_smbus_read_byte_data(client, MIDH);
1046 midl = i2c_smbus_read_byte_data(client, MIDL);
1047
1048 switch (VERSION(pid, ver)) {
1049 case PID_OV2640:
1050 devname = "ov2640";
1051 priv->model = V4L2_IDENT_OV2640;
1052 break;
1053 default:
1054 dev_err(&client->dev,
1055 "Product ID error %x:%x\n", pid, ver);
1056 ret = -ENODEV;
1057 goto err;
1058 }
1059
1060 dev_info(&client->dev,
1061 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1062 devname, pid, ver, midh, midl);
1063
1064 return 0;
1065
1066err:
1067 return ret;
1068}
1069
1070static struct soc_camera_ops ov2640_ops = {
1071 .set_bus_param = ov2640_set_bus_param,
1072 .query_bus_param = ov2640_query_bus_param,
1073 .controls = ov2640_controls,
1074 .num_controls = ARRAY_SIZE(ov2640_controls),
1075};
1076
1077static struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
1078 .g_ctrl = ov2640_g_ctrl,
1079 .s_ctrl = ov2640_s_ctrl,
1080 .g_chip_ident = ov2640_g_chip_ident,
1081#ifdef CONFIG_VIDEO_ADV_DEBUG
1082 .g_register = ov2640_g_register,
1083 .s_register = ov2640_s_register,
1084#endif
1085};
1086
Guennadi Liakhovetskid4630032011-07-26 11:59:53 -0300[diff] [blame^]1087static int ov2640_g_mbus_config(struct v4l2_subdev *sd,
1088 struct v4l2_mbus_config *cfg)
1089{
1090 struct i2c_client *client = v4l2_get_subdevdata(sd);
1091 struct soc_camera_device *icd = client->dev.platform_data;
1092 struct soc_camera_link *icl = to_soc_camera_link(icd);
1093
1094 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1095 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1096 V4L2_MBUS_DATA_ACTIVE_HIGH;
1097 cfg->type = V4L2_MBUS_PARALLEL;
1098 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1099
1100 return 0;
1101}
1102
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]1103static struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1104 .s_stream = ov2640_s_stream,
1105 .g_mbus_fmt = ov2640_g_fmt,
1106 .s_mbus_fmt = ov2640_s_fmt,
1107 .try_mbus_fmt = ov2640_try_fmt,
1108 .cropcap = ov2640_cropcap,
1109 .g_crop = ov2640_g_crop,
1110 .enum_mbus_fmt = ov2640_enum_fmt,
Guennadi Liakhovetskid4630032011-07-26 11:59:53 -0300[diff] [blame^]1111 .g_mbus_config = ov2640_g_mbus_config,
Alberto Panizzo3153ac92010-12-02 11:53:28 -0300[diff] [blame]1112};
1113
1114static struct v4l2_subdev_ops ov2640_subdev_ops = {
1115 .core = &ov2640_subdev_core_ops,
1116 .video = &ov2640_subdev_video_ops,
1117};
1118
1119/*
1120 * i2c_driver functions
1121 */
1122static int ov2640_probe(struct i2c_client *client,
1123 const struct i2c_device_id *did)
1124{
1125 struct ov2640_priv *priv;
1126 struct soc_camera_device *icd = client->dev.platform_data;
1127 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1128 struct soc_camera_link *icl;
1129 int ret;
1130
1131 if (!icd) {
1132 dev_err(&adapter->dev, "OV2640: missing soc-camera data!\n");
1133 return -EINVAL;
1134 }
1135
1136 icl = to_soc_camera_link(icd);
1137 if (!icl) {
1138 dev_err(&adapter->dev,
1139 "OV2640: Missing platform_data for driver\n");
1140 return -EINVAL;
1141 }
1142
1143 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1144 dev_err(&adapter->dev,
1145 "OV2640: I2C-Adapter doesn't support SMBUS\n");
1146 return -EIO;
1147 }
1148
1149 priv = kzalloc(sizeof(struct ov2640_priv), GFP_KERNEL);
1150 if (!priv) {
1151 dev_err(&adapter->dev,
1152 "Failed to allocate memory for private data!\n");
1153 return -ENOMEM;
1154 }
1155
1156 priv->info = icl->priv;
1157
1158 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
1159
1160 icd->ops = &ov2640_ops;
1161
1162 ret = ov2640_video_probe(icd, client);
1163 if (ret) {
1164 icd->ops = NULL;
1165 kfree(priv);
1166 } else {
1167 dev_info(&adapter->dev, "OV2640 Probed\n");
1168 }
1169
1170 return ret;
1171}
1172
1173static int ov2640_remove(struct i2c_client *client)
1174{
1175 struct ov2640_priv *priv = to_ov2640(client);
1176 struct soc_camera_device *icd = client->dev.platform_data;
1177
1178 icd->ops = NULL;
1179 kfree(priv);
1180 return 0;
1181}
1182
1183static const struct i2c_device_id ov2640_id[] = {
1184 { "ov2640", 0 },
1185 { }
1186};
1187MODULE_DEVICE_TABLE(i2c, ov2640_id);
1188
1189static struct i2c_driver ov2640_i2c_driver = {
1190 .driver = {
1191 .name = "ov2640",
1192 },
1193 .probe = ov2640_probe,
1194 .remove = ov2640_remove,
1195 .id_table = ov2640_id,
1196};
1197
1198/*
1199 * Module functions
1200 */
1201static int __init ov2640_module_init(void)
1202{
1203 return i2c_add_driver(&ov2640_i2c_driver);
1204}
1205
1206static void __exit ov2640_module_exit(void)
1207{
1208 i2c_del_driver(&ov2640_i2c_driver);
1209}
1210
1211module_init(ov2640_module_init);
1212module_exit(ov2640_module_exit);
1213
1214MODULE_DESCRIPTION("SoC Camera driver for Omni Vision 2640 sensor");
1215MODULE_AUTHOR("Alberto Panizzo");
1216MODULE_LICENSE("GPL v2");