| Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
| 4 | Copyright(c) 2007 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #ifndef _E1000_PHY_H_ |
| 29 | #define _E1000_PHY_H_ |
| 30 | |
| 31 | enum e1000_ms_type { |
| 32 | e1000_ms_hw_default = 0, |
| 33 | e1000_ms_force_master, |
| 34 | e1000_ms_force_slave, |
| 35 | e1000_ms_auto |
| 36 | }; |
| 37 | |
| 38 | enum e1000_smart_speed { |
| 39 | e1000_smart_speed_default = 0, |
| 40 | e1000_smart_speed_on, |
| 41 | e1000_smart_speed_off |
| 42 | }; |
| 43 | |
| 44 | s32 igb_check_downshift(struct e1000_hw *hw); |
| 45 | s32 igb_check_reset_block(struct e1000_hw *hw); |
| 46 | s32 igb_copper_link_autoneg(struct e1000_hw *hw); |
| 47 | s32 igb_phy_force_speed_duplex(struct e1000_hw *hw); |
| 48 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw); |
| 49 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw); |
| 50 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); |
| 51 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
| 52 | s32 igb_get_cable_length_m88(struct e1000_hw *hw); |
| 53 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); |
| 54 | s32 igb_get_phy_id(struct e1000_hw *hw); |
| 55 | s32 igb_get_phy_info_igp(struct e1000_hw *hw); |
| 56 | s32 igb_get_phy_info_m88(struct e1000_hw *hw); |
| 57 | s32 igb_phy_sw_reset(struct e1000_hw *hw); |
| 58 | s32 igb_phy_hw_reset(struct e1000_hw *hw); |
| 59 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
| 60 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
| 61 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
| 62 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, |
| 63 | u32 usec_interval, bool *success); |
| 64 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw); |
| 65 | |
| 66 | /* IGP01E1000 Specific Registers */ |
| 67 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ |
| 68 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ |
| 69 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ |
| 70 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
| 71 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
| 72 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
| 73 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
| 74 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
| 75 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
| 76 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ |
| 77 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
| 78 | |
| 79 | /* Enable flexible speed on link-up */ |
| 80 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ |
| 81 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ |
| 82 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
| 83 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
| 84 | #define IGP01E1000_PSSR_MDIX 0x0008 |
| 85 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
| 86 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
| 87 | #define IGP02E1000_PHY_CHANNEL_NUM 4 |
| 88 | #define IGP02E1000_PHY_AGC_A 0x11B1 |
| 89 | #define IGP02E1000_PHY_AGC_B 0x12B1 |
| 90 | #define IGP02E1000_PHY_AGC_C 0x14B1 |
| 91 | #define IGP02E1000_PHY_AGC_D 0x18B1 |
| 92 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ |
| 93 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
| 94 | #define IGP02E1000_AGC_RANGE 15 |
| 95 | |
| 96 | #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
| 97 | |
| 98 | #endif |