Blame - arch/arm/lib/delay.S - android_kernel_htc_msm8960

blob: 3c9a05c8d20b27a8054bebc5fed19f89ca03500e [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
				2	* linux/arch/arm/lib/delay.S
				3	*
				4	* Copyright (C) 1995, 1996 Russell King
				5	*
				6	* This program is free software; you can redistribute it and/or modify
				7	* it under the terms of the GNU General Public License version 2 as
				8	* published by the Free Software Foundation.
				9	*/
				10	#include <linux/linkage.h>
				11	#include <asm/assembler.h>
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	12	#include <asm/param.h>
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	13	.text
				14
Nicolas Pitre	8adbb37	2005-11-11 21:51:49 +0000	[diff] [blame]	15	.LC0: .word loops_per_jiffy
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	16	.LC1: .word (2199023*HZ)>>11
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	17
				18	/*
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	19	* r0 <= 2000
				20	* lpj <= 0x01ffffff (max. 3355 bogomips)
				21	* HZ <= 1000
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	22	*/
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	23
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	24	ENTRY(__udelay)
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	25	ldr r2, .LC1
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	26	mul r0, r2, r0
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	27	ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
Russell King	56949d4	2011-01-10 23:55:59 +0000	[diff] [blame]	28	mov r1, #-1
Nicolas Pitre	8adbb37	2005-11-11 21:51:49 +0000	[diff] [blame]	29	ldr r2, .LC0
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	30	ldr r2, [r2] @ max = 0x01ffffff
Russell King	56949d4	2011-01-10 23:55:59 +0000	[diff] [blame]	31	add r0, r0, r1, lsr #32-14
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	32	mov r0, r0, lsr #14 @ max = 0x0001ffff
Russell King	56949d4	2011-01-10 23:55:59 +0000	[diff] [blame]	33	add r2, r2, r1, lsr #32-10
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	34	mov r2, r2, lsr #10 @ max = 0x00007fff
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	35	mul r0, r2, r0 @ max = 2^32-1
Russell King	56949d4	2011-01-10 23:55:59 +0000	[diff] [blame]	36	add r0, r0, r1, lsr #32-6
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	37	movs r0, r0, lsr #6
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	38	moveq pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	39
				40	/*
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	41	* loops = r0 * HZ * loops_per_jiffy / 1000000
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	42	*
				43	* Oh, if only we had a cycle counter...
				44	*/
				45
				46	@ Delay routine
				47	ENTRY(__delay)
				48	subs r0, r0, #1
				49	#if 0
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	50	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	51	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	52	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	53	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	54	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	55	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	56	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	57	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	58	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	59	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	60	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	61	subs r0, r0, #1
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	62	movls pc, lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	63	subs r0, r0, #1
				64	#endif
				65	bhi __delay
Russell King	7999d8d	2006-06-25 11:17:23 +0100	[diff] [blame]	66	mov pc, lr
Catalin Marinas	93ed397	2008-08-28 11:22:32 +0100	[diff] [blame]	67	ENDPROC(__udelay)
				68	ENDPROC(__const_udelay)
				69	ENDPROC(__delay)