blob: 69f07b25b3c9d752b364c718fbfc859a0c0d419e [file] [log] [blame]
Dan Williams285f5fa2006-12-07 02:59:39 +01001/*
2 * iop13xx IRQ handling / support functions
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/sysctl.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/irq.h>
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/arch/irqs.h>
Daniel Wolstenholme2fd02372007-05-10 22:33:02 -070029#include <asm/arch/msi.h>
Dan Williams285f5fa2006-12-07 02:59:39 +010030
31/* INTCTL0 CP6 R0 Page 4
32 */
Dan Williamsd73d8012007-05-15 01:03:36 +010033static u32 read_intctl_0(void)
Dan Williams285f5fa2006-12-07 02:59:39 +010034{
35 u32 val;
36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
37 return val;
38}
Dan Williamsd73d8012007-05-15 01:03:36 +010039static void write_intctl_0(u32 val)
Dan Williams285f5fa2006-12-07 02:59:39 +010040{
41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
42}
43
44/* INTCTL1 CP6 R1 Page 4
45 */
Dan Williamsd73d8012007-05-15 01:03:36 +010046static u32 read_intctl_1(void)
Dan Williams285f5fa2006-12-07 02:59:39 +010047{
48 u32 val;
49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
50 return val;
51}
Dan Williamsd73d8012007-05-15 01:03:36 +010052static void write_intctl_1(u32 val)
Dan Williams285f5fa2006-12-07 02:59:39 +010053{
54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
55}
56
57/* INTCTL2 CP6 R2 Page 4
58 */
Dan Williamsd73d8012007-05-15 01:03:36 +010059static u32 read_intctl_2(void)
Dan Williams285f5fa2006-12-07 02:59:39 +010060{
61 u32 val;
62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
63 return val;
64}
Dan Williamsd73d8012007-05-15 01:03:36 +010065static void write_intctl_2(u32 val)
Dan Williams285f5fa2006-12-07 02:59:39 +010066{
67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
68}
69
70/* INTCTL3 CP6 R3 Page 4
71 */
Dan Williamsd73d8012007-05-15 01:03:36 +010072static u32 read_intctl_3(void)
Dan Williams285f5fa2006-12-07 02:59:39 +010073{
74 u32 val;
75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
76 return val;
77}
Dan Williamsd73d8012007-05-15 01:03:36 +010078static void write_intctl_3(u32 val)
Dan Williams285f5fa2006-12-07 02:59:39 +010079{
80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
81}
82
83/* INTSTR0 CP6 R0 Page 5
84 */
Dan Williamsd73d8012007-05-15 01:03:36 +010085static void write_intstr_0(u32 val)
Dan Williams285f5fa2006-12-07 02:59:39 +010086{
87 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
88}
89
90/* INTSTR1 CP6 R1 Page 5
91 */
Dan Williams285f5fa2006-12-07 02:59:39 +010092static void write_intstr_1(u32 val)
93{
94 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
95}
96
97/* INTSTR2 CP6 R2 Page 5
98 */
Dan Williams285f5fa2006-12-07 02:59:39 +010099static void write_intstr_2(u32 val)
100{
101 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
102}
103
104/* INTSTR3 CP6 R3 Page 5
105 */
Dan Williams285f5fa2006-12-07 02:59:39 +0100106static void write_intstr_3(u32 val)
107{
108 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
109}
110
111/* INTBASE CP6 R0 Page 2
112 */
Dan Williams285f5fa2006-12-07 02:59:39 +0100113static void write_intbase(u32 val)
114{
115 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
116}
117
118/* INTSIZE CP6 R2 Page 2
119 */
Dan Williams285f5fa2006-12-07 02:59:39 +0100120static void write_intsize(u32 val)
121{
122 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
123}
124
125/* 0 = Interrupt Masked and 1 = Interrupt not masked */
126static void
127iop13xx_irq_mask0 (unsigned int irq)
128{
Dan Williams285f5fa2006-12-07 02:59:39 +0100129 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100130}
131
132static void
133iop13xx_irq_mask1 (unsigned int irq)
134{
Dan Williams285f5fa2006-12-07 02:59:39 +0100135 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100136}
137
138static void
139iop13xx_irq_mask2 (unsigned int irq)
140{
Dan Williams285f5fa2006-12-07 02:59:39 +0100141 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100142}
143
144static void
145iop13xx_irq_mask3 (unsigned int irq)
146{
Dan Williams285f5fa2006-12-07 02:59:39 +0100147 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100148}
149
150static void
151iop13xx_irq_unmask0(unsigned int irq)
152{
Dan Williams285f5fa2006-12-07 02:59:39 +0100153 write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100154}
155
156static void
157iop13xx_irq_unmask1(unsigned int irq)
158{
Dan Williams285f5fa2006-12-07 02:59:39 +0100159 write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100160}
161
162static void
163iop13xx_irq_unmask2(unsigned int irq)
164{
Dan Williams285f5fa2006-12-07 02:59:39 +0100165 write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100166}
167
168static void
169iop13xx_irq_unmask3(unsigned int irq)
170{
Dan Williams285f5fa2006-12-07 02:59:39 +0100171 write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
Dan Williams285f5fa2006-12-07 02:59:39 +0100172}
173
Dan Williams3a2aeda2006-12-14 23:31:20 +0100174static struct irq_chip iop13xx_irqchip1 = {
175 .name = "IOP13xx-1",
Dan Williams285f5fa2006-12-07 02:59:39 +0100176 .ack = iop13xx_irq_mask0,
177 .mask = iop13xx_irq_mask0,
178 .unmask = iop13xx_irq_unmask0,
179};
180
Dan Williams3a2aeda2006-12-14 23:31:20 +0100181static struct irq_chip iop13xx_irqchip2 = {
182 .name = "IOP13xx-2",
Dan Williams285f5fa2006-12-07 02:59:39 +0100183 .ack = iop13xx_irq_mask1,
184 .mask = iop13xx_irq_mask1,
185 .unmask = iop13xx_irq_unmask1,
186};
187
Dan Williams3a2aeda2006-12-14 23:31:20 +0100188static struct irq_chip iop13xx_irqchip3 = {
189 .name = "IOP13xx-3",
Dan Williams285f5fa2006-12-07 02:59:39 +0100190 .ack = iop13xx_irq_mask2,
191 .mask = iop13xx_irq_mask2,
192 .unmask = iop13xx_irq_unmask2,
193};
194
Dan Williams3a2aeda2006-12-14 23:31:20 +0100195static struct irq_chip iop13xx_irqchip4 = {
196 .name = "IOP13xx-4",
Dan Williams285f5fa2006-12-07 02:59:39 +0100197 .ack = iop13xx_irq_mask3,
198 .mask = iop13xx_irq_mask3,
199 .unmask = iop13xx_irq_unmask3,
200};
201
Dan Williams588ef762007-02-13 17:12:04 +0100202extern void iop_init_cp6_handler(void);
203
Dan Williams285f5fa2006-12-07 02:59:39 +0100204void __init iop13xx_init_irq(void)
205{
206 unsigned int i;
207
Dan Williams588ef762007-02-13 17:12:04 +0100208 iop_init_cp6_handler();
Dan Williams285f5fa2006-12-07 02:59:39 +0100209
210 /* disable all interrupts */
211 write_intctl_0(0);
212 write_intctl_1(0);
213 write_intctl_2(0);
214 write_intctl_3(0);
215
216 /* treat all as IRQ */
217 write_intstr_0(0);
218 write_intstr_1(0);
219 write_intstr_2(0);
220 write_intstr_3(0);
221
222 /* initialize the interrupt vector generator */
223 write_intbase(INTBASE);
224 write_intsize(INTSIZE_4);
225
Daniel Wolstenholme2fd02372007-05-10 22:33:02 -0700226 for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
Dan Williams285f5fa2006-12-07 02:59:39 +0100227 if (i < 32)
Dan Williams285f5fa2006-12-07 02:59:39 +0100228 set_irq_chip(i, &iop13xx_irqchip1);
Dan Williams3a2aeda2006-12-14 23:31:20 +0100229 else if (i < 64)
Dan Williams285f5fa2006-12-07 02:59:39 +0100230 set_irq_chip(i, &iop13xx_irqchip2);
Dan Williams3a2aeda2006-12-14 23:31:20 +0100231 else if (i < 96)
Dan Williams285f5fa2006-12-07 02:59:39 +0100232 set_irq_chip(i, &iop13xx_irqchip3);
Dan Williams3a2aeda2006-12-14 23:31:20 +0100233 else
234 set_irq_chip(i, &iop13xx_irqchip4);
Dan Williams285f5fa2006-12-07 02:59:39 +0100235
Dan Williams3a2aeda2006-12-14 23:31:20 +0100236 set_irq_handler(i, handle_level_irq);
Dan Williams285f5fa2006-12-07 02:59:39 +0100237 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
238 }
Daniel Wolstenholme2fd02372007-05-10 22:33:02 -0700239
240 iop13xx_msi_init();
Dan Williams285f5fa2006-12-07 02:59:39 +0100241}