blob: 489e82b5282a9e0d77cae4da08690cf48364a12d [file] [log] [blame]
Olof Johansson85940b42011-02-19 16:26:18 -08001/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19
20#include <linux/resource.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/fsl_devices.h>
24#include <linux/serial_8250.h>
Colin Cross78702e42011-07-10 14:37:22 -070025#include <linux/i2c-tegra.h>
Colin Cross681e6ed2011-07-10 14:59:45 -070026#include <linux/platform_data/tegra_usb.h>
Olof Johansson85940b42011-02-19 16:26:18 -080027#include <asm/pmu.h>
28#include <mach/irqs.h>
29#include <mach/iomap.h>
30#include <mach/dma.h>
Colin Cross681e6ed2011-07-10 14:59:45 -070031#include <mach/usb_phy.h>
Olof Johanssond8e9c002011-10-12 17:56:33 -070032
Colin Cross681e6ed2011-07-10 14:59:45 -070033#include "gpio-names.h"
Olof Johanssond8e9c002011-10-12 17:56:33 -070034#include "devices.h"
Olof Johansson85940b42011-02-19 16:26:18 -080035
36static struct resource i2c_resource1[] = {
37 [0] = {
38 .start = INT_I2C,
39 .end = INT_I2C,
40 .flags = IORESOURCE_IRQ,
41 },
42 [1] = {
43 .start = TEGRA_I2C_BASE,
44 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
45 .flags = IORESOURCE_MEM,
46 },
47};
48
49static struct resource i2c_resource2[] = {
50 [0] = {
51 .start = INT_I2C2,
52 .end = INT_I2C2,
53 .flags = IORESOURCE_IRQ,
54 },
55 [1] = {
56 .start = TEGRA_I2C2_BASE,
57 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
58 .flags = IORESOURCE_MEM,
59 },
60};
61
62static struct resource i2c_resource3[] = {
63 [0] = {
64 .start = INT_I2C3,
65 .end = INT_I2C3,
66 .flags = IORESOURCE_IRQ,
67 },
68 [1] = {
69 .start = TEGRA_I2C3_BASE,
70 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
71 .flags = IORESOURCE_MEM,
72 },
73};
74
75static struct resource i2c_resource4[] = {
76 [0] = {
77 .start = INT_DVC,
78 .end = INT_DVC,
79 .flags = IORESOURCE_IRQ,
80 },
81 [1] = {
82 .start = TEGRA_DVC_BASE,
83 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
84 .flags = IORESOURCE_MEM,
85 },
86};
87
Colin Cross78702e42011-07-10 14:37:22 -070088static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
89 .bus_clk_rate = 400000,
90};
91
92static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
93 .bus_clk_rate = 400000,
94};
95
96static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
97 .bus_clk_rate = 400000,
98};
99
100static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
101 .bus_clk_rate = 400000,
102};
103
Olof Johansson85940b42011-02-19 16:26:18 -0800104struct platform_device tegra_i2c_device1 = {
105 .name = "tegra-i2c",
106 .id = 0,
107 .resource = i2c_resource1,
108 .num_resources = ARRAY_SIZE(i2c_resource1),
109 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700110 .platform_data = &tegra_i2c1_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800111 },
112};
113
114struct platform_device tegra_i2c_device2 = {
115 .name = "tegra-i2c",
116 .id = 1,
117 .resource = i2c_resource2,
118 .num_resources = ARRAY_SIZE(i2c_resource2),
119 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700120 .platform_data = &tegra_i2c2_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800121 },
122};
123
124struct platform_device tegra_i2c_device3 = {
125 .name = "tegra-i2c",
126 .id = 2,
127 .resource = i2c_resource3,
128 .num_resources = ARRAY_SIZE(i2c_resource3),
129 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700130 .platform_data = &tegra_i2c3_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800131 },
132};
133
134struct platform_device tegra_i2c_device4 = {
135 .name = "tegra-i2c",
136 .id = 3,
137 .resource = i2c_resource4,
138 .num_resources = ARRAY_SIZE(i2c_resource4),
139 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700140 .platform_data = &tegra_dvc_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800141 },
142};
143
144static struct resource spi_resource1[] = {
145 [0] = {
146 .start = INT_S_LINK1,
147 .end = INT_S_LINK1,
148 .flags = IORESOURCE_IRQ,
149 },
150 [1] = {
151 .start = TEGRA_SPI1_BASE,
152 .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
153 .flags = IORESOURCE_MEM,
154 },
155};
156
157static struct resource spi_resource2[] = {
158 [0] = {
159 .start = INT_SPI_2,
160 .end = INT_SPI_2,
161 .flags = IORESOURCE_IRQ,
162 },
163 [1] = {
164 .start = TEGRA_SPI2_BASE,
165 .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
166 .flags = IORESOURCE_MEM,
167 },
168};
169
170static struct resource spi_resource3[] = {
171 [0] = {
172 .start = INT_SPI_3,
173 .end = INT_SPI_3,
174 .flags = IORESOURCE_IRQ,
175 },
176 [1] = {
177 .start = TEGRA_SPI3_BASE,
178 .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
179 .flags = IORESOURCE_MEM,
180 },
181};
182
183static struct resource spi_resource4[] = {
184 [0] = {
185 .start = INT_SPI_4,
186 .end = INT_SPI_4,
187 .flags = IORESOURCE_IRQ,
188 },
189 [1] = {
190 .start = TEGRA_SPI4_BASE,
191 .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
192 .flags = IORESOURCE_MEM,
193 },
194};
195
196struct platform_device tegra_spi_device1 = {
197 .name = "spi_tegra",
198 .id = 0,
199 .resource = spi_resource1,
200 .num_resources = ARRAY_SIZE(spi_resource1),
201 .dev = {
202 .coherent_dma_mask = 0xffffffff,
203 },
204};
205
206struct platform_device tegra_spi_device2 = {
207 .name = "spi_tegra",
208 .id = 1,
209 .resource = spi_resource2,
210 .num_resources = ARRAY_SIZE(spi_resource2),
211 .dev = {
212 .coherent_dma_mask = 0xffffffff,
213 },
214};
215
216struct platform_device tegra_spi_device3 = {
217 .name = "spi_tegra",
218 .id = 2,
219 .resource = spi_resource3,
220 .num_resources = ARRAY_SIZE(spi_resource3),
221 .dev = {
222 .coherent_dma_mask = 0xffffffff,
223 },
224};
225
226struct platform_device tegra_spi_device4 = {
227 .name = "spi_tegra",
228 .id = 3,
229 .resource = spi_resource4,
230 .num_resources = ARRAY_SIZE(spi_resource4),
231 .dev = {
232 .coherent_dma_mask = 0xffffffff,
233 },
234};
235
236
237static struct resource sdhci_resource1[] = {
238 [0] = {
239 .start = INT_SDMMC1,
240 .end = INT_SDMMC1,
241 .flags = IORESOURCE_IRQ,
242 },
243 [1] = {
244 .start = TEGRA_SDMMC1_BASE,
245 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct resource sdhci_resource2[] = {
251 [0] = {
252 .start = INT_SDMMC2,
253 .end = INT_SDMMC2,
254 .flags = IORESOURCE_IRQ,
255 },
256 [1] = {
257 .start = TEGRA_SDMMC2_BASE,
258 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
259 .flags = IORESOURCE_MEM,
260 },
261};
262
263static struct resource sdhci_resource3[] = {
264 [0] = {
265 .start = INT_SDMMC3,
266 .end = INT_SDMMC3,
267 .flags = IORESOURCE_IRQ,
268 },
269 [1] = {
270 .start = TEGRA_SDMMC3_BASE,
271 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
272 .flags = IORESOURCE_MEM,
273 },
274};
275
276static struct resource sdhci_resource4[] = {
277 [0] = {
278 .start = INT_SDMMC4,
279 .end = INT_SDMMC4,
280 .flags = IORESOURCE_IRQ,
281 },
282 [1] = {
283 .start = TEGRA_SDMMC4_BASE,
284 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
285 .flags = IORESOURCE_MEM,
286 },
287};
288
289/* board files should fill in platform_data register the devices themselvs.
290 * See board-harmony.c for an example
291 */
292struct platform_device tegra_sdhci_device1 = {
293 .name = "sdhci-tegra",
294 .id = 0,
295 .resource = sdhci_resource1,
296 .num_resources = ARRAY_SIZE(sdhci_resource1),
297};
298
299struct platform_device tegra_sdhci_device2 = {
300 .name = "sdhci-tegra",
301 .id = 1,
302 .resource = sdhci_resource2,
303 .num_resources = ARRAY_SIZE(sdhci_resource2),
304};
305
306struct platform_device tegra_sdhci_device3 = {
307 .name = "sdhci-tegra",
308 .id = 2,
309 .resource = sdhci_resource3,
310 .num_resources = ARRAY_SIZE(sdhci_resource3),
311};
312
313struct platform_device tegra_sdhci_device4 = {
314 .name = "sdhci-tegra",
315 .id = 3,
316 .resource = sdhci_resource4,
317 .num_resources = ARRAY_SIZE(sdhci_resource4),
318};
319
320static struct resource tegra_usb1_resources[] = {
321 [0] = {
322 .start = TEGRA_USB_BASE,
323 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 [1] = {
327 .start = INT_USB,
328 .end = INT_USB,
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333static struct resource tegra_usb2_resources[] = {
334 [0] = {
335 .start = TEGRA_USB2_BASE,
336 .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
337 .flags = IORESOURCE_MEM,
338 },
339 [1] = {
340 .start = INT_USB2,
341 .end = INT_USB2,
342 .flags = IORESOURCE_IRQ,
343 },
344};
345
346static struct resource tegra_usb3_resources[] = {
347 [0] = {
348 .start = TEGRA_USB3_BASE,
349 .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
350 .flags = IORESOURCE_MEM,
351 },
352 [1] = {
353 .start = INT_USB3,
354 .end = INT_USB3,
355 .flags = IORESOURCE_IRQ,
356 },
357};
358
Colin Cross681e6ed2011-07-10 14:59:45 -0700359static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
360 /* All existing boards use GPIO PV0 for phy reset */
361 .reset_gpio = TEGRA_GPIO_PV0,
362 .clk = "cdev2",
363};
364
365static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
366 .operating_mode = TEGRA_USB_OTG,
367 .power_down_on_bus_suspend = 1,
368};
369
370static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
371 .phy_config = &tegra_ehci2_ulpi_phy_config,
372 .operating_mode = TEGRA_USB_HOST,
373 .power_down_on_bus_suspend = 1,
374};
375
376static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
377 .operating_mode = TEGRA_USB_HOST,
378 .power_down_on_bus_suspend = 1,
379};
380
Olof Johansson85940b42011-02-19 16:26:18 -0800381static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
382
383struct platform_device tegra_ehci1_device = {
384 .name = "tegra-ehci",
385 .id = 0,
386 .dev = {
387 .dma_mask = &tegra_ehci_dmamask,
388 .coherent_dma_mask = DMA_BIT_MASK(32),
Colin Cross681e6ed2011-07-10 14:59:45 -0700389 .platform_data = &tegra_ehci1_pdata,
Olof Johansson85940b42011-02-19 16:26:18 -0800390 },
391 .resource = tegra_usb1_resources,
392 .num_resources = ARRAY_SIZE(tegra_usb1_resources),
393};
394
395struct platform_device tegra_ehci2_device = {
396 .name = "tegra-ehci",
397 .id = 1,
398 .dev = {
399 .dma_mask = &tegra_ehci_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
Colin Cross681e6ed2011-07-10 14:59:45 -0700401 .platform_data = &tegra_ehci2_pdata,
Olof Johansson85940b42011-02-19 16:26:18 -0800402 },
403 .resource = tegra_usb2_resources,
404 .num_resources = ARRAY_SIZE(tegra_usb2_resources),
405};
406
407struct platform_device tegra_ehci3_device = {
408 .name = "tegra-ehci",
409 .id = 2,
410 .dev = {
411 .dma_mask = &tegra_ehci_dmamask,
412 .coherent_dma_mask = DMA_BIT_MASK(32),
Colin Cross681e6ed2011-07-10 14:59:45 -0700413 .platform_data = &tegra_ehci3_pdata,
Olof Johansson85940b42011-02-19 16:26:18 -0800414 },
415 .resource = tegra_usb3_resources,
416 .num_resources = ARRAY_SIZE(tegra_usb3_resources),
417};
418
419static struct resource tegra_pmu_resources[] = {
420 [0] = {
421 .start = INT_CPU0_PMU_INTR,
422 .end = INT_CPU0_PMU_INTR,
423 .flags = IORESOURCE_IRQ,
424 },
425 [1] = {
426 .start = INT_CPU1_PMU_INTR,
427 .end = INT_CPU1_PMU_INTR,
428 .flags = IORESOURCE_IRQ,
429 },
430};
431
432struct platform_device tegra_pmu_device = {
433 .name = "arm-pmu",
434 .id = ARM_PMU_DEVICE_CPU,
435 .num_resources = ARRAY_SIZE(tegra_pmu_resources),
436 .resource = tegra_pmu_resources,
437};
438
439static struct resource tegra_uarta_resources[] = {
440 [0] = {
441 .start = TEGRA_UARTA_BASE,
442 .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
443 .flags = IORESOURCE_MEM,
444 },
445 [1] = {
446 .start = INT_UARTA,
447 .end = INT_UARTA,
448 .flags = IORESOURCE_IRQ,
449 },
450};
451
452static struct resource tegra_uartb_resources[] = {
453 [0] = {
454 .start = TEGRA_UARTB_BASE,
455 .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
456 .flags = IORESOURCE_MEM,
457 },
458 [1] = {
459 .start = INT_UARTB,
460 .end = INT_UARTB,
461 .flags = IORESOURCE_IRQ,
462 },
463};
464
465static struct resource tegra_uartc_resources[] = {
466 [0] = {
467 .start = TEGRA_UARTC_BASE,
468 .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 [1] = {
472 .start = INT_UARTC,
473 .end = INT_UARTC,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct resource tegra_uartd_resources[] = {
479 [0] = {
480 .start = TEGRA_UARTD_BASE,
481 .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
482 .flags = IORESOURCE_MEM,
483 },
484 [1] = {
485 .start = INT_UARTD,
486 .end = INT_UARTD,
487 .flags = IORESOURCE_IRQ,
488 },
489};
490
491static struct resource tegra_uarte_resources[] = {
492 [0] = {
493 .start = TEGRA_UARTE_BASE,
494 .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
495 .flags = IORESOURCE_MEM,
496 },
497 [1] = {
498 .start = INT_UARTE,
499 .end = INT_UARTE,
500 .flags = IORESOURCE_IRQ,
501 },
502};
503
504struct platform_device tegra_uarta_device = {
505 .name = "tegra_uart",
506 .id = 0,
507 .num_resources = ARRAY_SIZE(tegra_uarta_resources),
508 .resource = tegra_uarta_resources,
509 .dev = {
510 .coherent_dma_mask = DMA_BIT_MASK(32),
511 },
512};
513
514struct platform_device tegra_uartb_device = {
515 .name = "tegra_uart",
516 .id = 1,
517 .num_resources = ARRAY_SIZE(tegra_uartb_resources),
518 .resource = tegra_uartb_resources,
519 .dev = {
520 .coherent_dma_mask = DMA_BIT_MASK(32),
521 },
522};
523
524struct platform_device tegra_uartc_device = {
525 .name = "tegra_uart",
526 .id = 2,
527 .num_resources = ARRAY_SIZE(tegra_uartc_resources),
528 .resource = tegra_uartc_resources,
529 .dev = {
530 .coherent_dma_mask = DMA_BIT_MASK(32),
531 },
532};
533
534struct platform_device tegra_uartd_device = {
535 .name = "tegra_uart",
536 .id = 3,
537 .num_resources = ARRAY_SIZE(tegra_uartd_resources),
538 .resource = tegra_uartd_resources,
539 .dev = {
540 .coherent_dma_mask = DMA_BIT_MASK(32),
541 },
542};
543
544struct platform_device tegra_uarte_device = {
545 .name = "tegra_uart",
546 .id = 4,
547 .num_resources = ARRAY_SIZE(tegra_uarte_resources),
548 .resource = tegra_uarte_resources,
549 .dev = {
550 .coherent_dma_mask = DMA_BIT_MASK(32),
551 },
552};
Stephen Warrenb9652c22011-03-04 22:44:27 -0700553
554static struct resource i2s_resource1[] = {
555 [0] = {
556 .start = INT_I2S1,
557 .end = INT_I2S1,
558 .flags = IORESOURCE_IRQ
559 },
560 [1] = {
561 .start = TEGRA_DMA_REQ_SEL_I2S_1,
562 .end = TEGRA_DMA_REQ_SEL_I2S_1,
563 .flags = IORESOURCE_DMA
564 },
565 [2] = {
566 .start = TEGRA_I2S1_BASE,
567 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
568 .flags = IORESOURCE_MEM
569 }
570};
571
572static struct resource i2s_resource2[] = {
573 [0] = {
574 .start = INT_I2S2,
575 .end = INT_I2S2,
576 .flags = IORESOURCE_IRQ
577 },
578 [1] = {
579 .start = TEGRA_DMA_REQ_SEL_I2S2_1,
580 .end = TEGRA_DMA_REQ_SEL_I2S2_1,
581 .flags = IORESOURCE_DMA
582 },
583 [2] = {
584 .start = TEGRA_I2S2_BASE,
585 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
586 .flags = IORESOURCE_MEM
587 }
588};
589
590struct platform_device tegra_i2s_device1 = {
591 .name = "tegra-i2s",
592 .id = 0,
593 .resource = i2s_resource1,
594 .num_resources = ARRAY_SIZE(i2s_resource1),
595};
596
597struct platform_device tegra_i2s_device2 = {
598 .name = "tegra-i2s",
599 .id = 1,
600 .resource = i2s_resource2,
601 .num_resources = ARRAY_SIZE(i2s_resource2),
602};
603
604static struct resource tegra_das_resources[] = {
605 [0] = {
606 .start = TEGRA_APB_MISC_DAS_BASE,
607 .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
608 .flags = IORESOURCE_MEM,
609 },
610};
611
612struct platform_device tegra_das_device = {
613 .name = "tegra-das",
614 .id = -1,
615 .num_resources = ARRAY_SIZE(tegra_das_resources),
616 .resource = tegra_das_resources,
617};
618
619struct platform_device tegra_pcm_device = {
620 .name = "tegra-pcm-audio",
621 .id = -1,
622};