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review.evervolv.com / android_kernel_htc_msm8960 / d9040ad20570c394de4104d151a50cb1944cb756 / . / arch / arm / mach-msm / devices-8960.c
blob: 772b0e639a74b1acab82f07ebfb22a5e41342dcd [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/gpio.h>
19#include <asm/clkdev.h>
20#include <linux/msm_kgsl.h>
21#include <linux/android_pmem.h>
22#include <mach/irqs-8960.h>
23#include <mach/board.h>
24#include <mach/msm_iomap.h>
25#include <mach/msm_hsusb.h>
26#include <mach/msm_sps.h>
27#include <mach/rpm.h>
28#include <mach/msm_bus_board.h>
29#include <mach/msm_memtypes.h>
30#include "clock.h"
31#include "devices.h"
32#include "devices-msm8x60.h"
33#include "footswitch.h"
34
35#ifdef CONFIG_MSM_MPM
36#include "mpm.h"
37#endif
38#ifdef CONFIG_MSM_DSPS
39#include <mach/msm_dsps.h>
40#endif
41
42
43/* Address of GSBI blocks */
44#define MSM_GSBI1_PHYS 0x16000000
45#define MSM_GSBI2_PHYS 0x16100000
46#define MSM_GSBI3_PHYS 0x16200000
47#define MSM_GSBI4_PHYS 0x16300000
48#define MSM_GSBI5_PHYS 0x16400000
49#define MSM_GSBI6_PHYS 0x16500000
50#define MSM_GSBI7_PHYS 0x16600000
51#define MSM_GSBI8_PHYS 0x1A000000
52#define MSM_GSBI9_PHYS 0x1A100000
53#define MSM_GSBI10_PHYS 0x1A200000
54#define MSM_GSBI11_PHYS 0x12440000
55#define MSM_GSBI12_PHYS 0x12480000
56
57#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000)
58#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
59
60/* GSBI QUP devices */
61#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
62#define MSM_GSBI2_QUP_PHYS (MSM_GSBI2_PHYS + 0x80000)
63#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
64#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
65#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
66#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
67#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
68#define MSM_GSBI8_QUP_PHYS (MSM_GSBI8_PHYS + 0x80000)
69#define MSM_GSBI9_QUP_PHYS (MSM_GSBI9_PHYS + 0x80000)
70#define MSM_GSBI10_QUP_PHYS (MSM_GSBI10_PHYS + 0x80000)
71#define MSM_GSBI11_QUP_PHYS (MSM_GSBI11_PHYS + 0x20000)
72#define MSM_GSBI12_QUP_PHYS (MSM_GSBI12_PHYS + 0x20000)
73#define MSM_QUP_SIZE SZ_4K
74
75#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
76#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
77#define MSM_PMIC_SSBI_SIZE SZ_4K
78
79static struct resource resources_otg[] = {
80 {
81 .start = MSM8960_HSUSB_PHYS,
82 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
83 .flags = IORESOURCE_MEM,
84 },
85 {
86 .start = USB1_HS_IRQ,
87 .end = USB1_HS_IRQ,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92struct platform_device msm_device_otg = {
93 .name = "msm_otg",
94 .id = -1,
95 .num_resources = ARRAY_SIZE(resources_otg),
96 .resource = resources_otg,
97 .dev = {
98 .coherent_dma_mask = 0xffffffff,
99 },
100};
101
102static struct resource resources_hsusb[] = {
103 {
104 .start = MSM8960_HSUSB_PHYS,
105 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
106 .flags = IORESOURCE_MEM,
107 },
108 {
109 .start = USB1_HS_IRQ,
110 .end = USB1_HS_IRQ,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115struct platform_device msm_device_gadget_peripheral = {
116 .name = "msm_hsusb",
117 .id = -1,
118 .num_resources = ARRAY_SIZE(resources_hsusb),
119 .resource = resources_hsusb,
120 .dev = {
121 .coherent_dma_mask = 0xffffffff,
122 },
123};
124
125static struct resource resources_hsusb_host[] = {
126 {
127 .start = MSM8960_HSUSB_PHYS,
128 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE - 1,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .start = USB1_HS_IRQ,
133 .end = USB1_HS_IRQ,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static u64 dma_mask = 0xffffffffULL;
139struct platform_device msm_device_hsusb_host = {
140 .name = "msm_hsusb_host",
141 .id = -1,
142 .num_resources = ARRAY_SIZE(resources_hsusb_host),
143 .resource = resources_hsusb_host,
144 .dev = {
145 .dma_mask = &dma_mask,
146 .coherent_dma_mask = 0xffffffff,
147 },
148};
149
150static struct resource resources_uart_gsbi2[] = {
151 {
152 .start = MSM8960_GSBI2_UARTDM_IRQ,
153 .end = MSM8960_GSBI2_UARTDM_IRQ,
154 .flags = IORESOURCE_IRQ,
155 },
156 {
157 .start = MSM_UART2DM_PHYS,
158 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
159 .name = "uartdm_resource",
160 .flags = IORESOURCE_MEM,
161 },
162 {
163 .start = MSM_GSBI2_PHYS,
164 .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
165 .name = "gsbi_resource",
166 .flags = IORESOURCE_MEM,
167 },
168};
169
170struct platform_device msm8960_device_uart_gsbi2 = {
171 .name = "msm_serial_hsl",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(resources_uart_gsbi2),
174 .resource = resources_uart_gsbi2,
175};
176
177static struct resource resources_uart_gsbi5[] = {
178 {
179 .start = GSBI5_UARTDM_IRQ,
180 .end = GSBI5_UARTDM_IRQ,
181 .flags = IORESOURCE_IRQ,
182 },
183 {
184 .start = MSM_UART5DM_PHYS,
185 .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
186 .name = "uartdm_resource",
187 .flags = IORESOURCE_MEM,
188 },
189 {
190 .start = MSM_GSBI5_PHYS,
191 .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
192 .name = "gsbi_resource",
193 .flags = IORESOURCE_MEM,
194 },
195};
196
197struct platform_device msm8960_device_uart_gsbi5 = {
198 .name = "msm_serial_hsl",
199 .id = 0,
200 .num_resources = ARRAY_SIZE(resources_uart_gsbi5),
201 .resource = resources_uart_gsbi5,
202};
203/* MSM Video core device */
204#ifdef CONFIG_MSM_BUS_SCALING
205static struct msm_bus_vectors vidc_init_vectors[] = {
206 {
207 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
208 .dst = MSM_BUS_SLAVE_EBI_CH0,
209 .ab = 0,
210 .ib = 0,
211 },
212 {
213 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
214 .dst = MSM_BUS_SLAVE_EBI_CH0,
215 .ab = 0,
216 .ib = 0,
217 },
218 {
219 .src = MSM_BUS_MASTER_AMPSS_M0,
220 .dst = MSM_BUS_SLAVE_EBI_CH0,
221 .ab = 0,
222 .ib = 0,
223 },
224 {
225 .src = MSM_BUS_MASTER_AMPSS_M0,
226 .dst = MSM_BUS_SLAVE_EBI_CH0,
227 .ab = 0,
228 .ib = 0,
229 },
230};
231static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
232 {
233 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
234 .dst = MSM_BUS_SLAVE_EBI_CH0,
235 .ab = 54525952,
236 .ib = 436207616,
237 },
238 {
239 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
240 .dst = MSM_BUS_SLAVE_EBI_CH0,
241 .ab = 72351744,
242 .ib = 289406976,
243 },
244 {
245 .src = MSM_BUS_MASTER_AMPSS_M0,
246 .dst = MSM_BUS_SLAVE_EBI_CH0,
247 .ab = 500000,
248 .ib = 1000000,
249 },
250 {
251 .src = MSM_BUS_MASTER_AMPSS_M0,
252 .dst = MSM_BUS_SLAVE_EBI_CH0,
253 .ab = 500000,
254 .ib = 1000000,
255 },
256};
257static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
258 {
259 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
260 .dst = MSM_BUS_SLAVE_EBI_CH0,
261 .ab = 40894464,
262 .ib = 327155712,
263 },
264 {
265 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
266 .dst = MSM_BUS_SLAVE_EBI_CH0,
267 .ab = 48234496,
268 .ib = 192937984,
269 },
270 {
271 .src = MSM_BUS_MASTER_AMPSS_M0,
272 .dst = MSM_BUS_SLAVE_EBI_CH0,
273 .ab = 500000,
274 .ib = 2000000,
275 },
276 {
277 .src = MSM_BUS_MASTER_AMPSS_M0,
278 .dst = MSM_BUS_SLAVE_EBI_CH0,
279 .ab = 500000,
280 .ib = 2000000,
281 },
282};
283static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
284 {
285 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
286 .dst = MSM_BUS_SLAVE_EBI_CH0,
287 .ab = 163577856,
288 .ib = 1308622848,
289 },
290 {
291 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
292 .dst = MSM_BUS_SLAVE_EBI_CH0,
293 .ab = 219152384,
294 .ib = 876609536,
295 },
296 {
297 .src = MSM_BUS_MASTER_AMPSS_M0,
298 .dst = MSM_BUS_SLAVE_EBI_CH0,
299 .ab = 1750000,
300 .ib = 3500000,
301 },
302 {
303 .src = MSM_BUS_MASTER_AMPSS_M0,
304 .dst = MSM_BUS_SLAVE_EBI_CH0,
305 .ab = 1750000,
306 .ib = 3500000,
307 },
308};
309static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
310 {
311 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
312 .dst = MSM_BUS_SLAVE_EBI_CH0,
313 .ab = 121634816,
314 .ib = 973078528,
315 },
316 {
317 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
318 .dst = MSM_BUS_SLAVE_EBI_CH0,
319 .ab = 155189248,
320 .ib = 620756992,
321 },
322 {
323 .src = MSM_BUS_MASTER_AMPSS_M0,
324 .dst = MSM_BUS_SLAVE_EBI_CH0,
325 .ab = 1750000,
326 .ib = 7000000,
327 },
328 {
329 .src = MSM_BUS_MASTER_AMPSS_M0,
330 .dst = MSM_BUS_SLAVE_EBI_CH0,
331 .ab = 1750000,
332 .ib = 7000000,
333 },
334};
335static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
336 {
337 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
338 .dst = MSM_BUS_SLAVE_EBI_CH0,
339 .ab = 372244480,
340 .ib = 1861222400,
341 },
342 {
343 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
344 .dst = MSM_BUS_SLAVE_EBI_CH0,
345 .ab = 501219328,
346 .ib = 2004877312,
347 },
348 {
349 .src = MSM_BUS_MASTER_AMPSS_M0,
350 .dst = MSM_BUS_SLAVE_EBI_CH0,
351 .ab = 2500000,
352 .ib = 5000000,
353 },
354 {
355 .src = MSM_BUS_MASTER_AMPSS_M0,
356 .dst = MSM_BUS_SLAVE_EBI_CH0,
357 .ab = 2500000,
358 .ib = 5000000,
359 },
360};
361static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
362 {
363 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
364 .dst = MSM_BUS_SLAVE_EBI_CH0,
365 .ab = 222298112,
366 .ib = 1778384896,
367 },
368 {
369 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
370 .dst = MSM_BUS_SLAVE_EBI_CH0,
371 .ab = 330301440,
372 .ib = 1321205760,
373 },
374 {
375 .src = MSM_BUS_MASTER_AMPSS_M0,
376 .dst = MSM_BUS_SLAVE_EBI_CH0,
377 .ab = 2500000,
378 .ib = 700000000,
379 },
380 {
381 .src = MSM_BUS_MASTER_AMPSS_M0,
382 .dst = MSM_BUS_SLAVE_EBI_CH0,
383 .ab = 2500000,
384 .ib = 10000000,
385 },
386};
387
388static struct msm_bus_paths vidc_bus_client_config[] = {
389 {
390 ARRAY_SIZE(vidc_init_vectors),
391 vidc_init_vectors,
392 },
393 {
394 ARRAY_SIZE(vidc_venc_vga_vectors),
395 vidc_venc_vga_vectors,
396 },
397 {
398 ARRAY_SIZE(vidc_vdec_vga_vectors),
399 vidc_vdec_vga_vectors,
400 },
401 {
402 ARRAY_SIZE(vidc_venc_720p_vectors),
403 vidc_venc_720p_vectors,
404 },
405 {
406 ARRAY_SIZE(vidc_vdec_720p_vectors),
407 vidc_vdec_720p_vectors,
408 },
409 {
410 ARRAY_SIZE(vidc_venc_1080p_vectors),
411 vidc_venc_1080p_vectors,
412 },
413 {
414 ARRAY_SIZE(vidc_vdec_1080p_vectors),
415 vidc_vdec_1080p_vectors,
416 },
417};
418
419static struct msm_bus_scale_pdata vidc_bus_client_data = {
420 vidc_bus_client_config,
421 ARRAY_SIZE(vidc_bus_client_config),
422 .name = "vidc",
423};
424#endif
425
426#define MSM_VIDC_BASE_PHYS 0x04400000
427#define MSM_VIDC_BASE_SIZE 0x00100000
428
429static struct resource msm_device_vidc_resources[] = {
430 {
431 .start = MSM_VIDC_BASE_PHYS,
432 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 {
436 .start = VCODEC_IRQ,
437 .end = VCODEC_IRQ,
438 .flags = IORESOURCE_IRQ,
439 },
440};
441
442struct msm_vidc_platform_data vidc_platform_data = {
443#ifdef CONFIG_MSM_BUS_SCALING
444 .vidc_bus_client_pdata = &vidc_bus_client_data,
445#endif
446 .memtype = MEMTYPE_EBI1
447};
448
449struct platform_device msm_device_vidc = {
450 .name = "msm_vidc",
451 .id = 0,
452 .num_resources = ARRAY_SIZE(msm_device_vidc_resources),
453 .resource = msm_device_vidc_resources,
454 .dev = {
455 .platform_data = &vidc_platform_data,
456 },
457};
458
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]459#define MSM_SDC1_BASE 0x12400000
460#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
461#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
462#define MSM_SDC2_BASE 0x12140000
463#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
464#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
465#define MSM_SDC2_BASE 0x12140000
466#define MSM_SDC3_BASE 0x12180000
467#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
468#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
469#define MSM_SDC4_BASE 0x121C0000
470#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
471#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
472#define MSM_SDC5_BASE 0x12200000
473#define MSM_SDC5_DML_BASE (MSM_SDC5_BASE + 0x800)
474#define MSM_SDC5_BAM_BASE (MSM_SDC5_BASE + 0x2000)
475
476static struct resource resources_sdc1[] = {
477 {
478 .name = "core_mem",
479 .flags = IORESOURCE_MEM,
480 .start = MSM_SDC1_BASE,
481 .end = MSM_SDC1_DML_BASE - 1,
482 },
483 {
484 .name = "core_irq",
485 .flags = IORESOURCE_IRQ,
486 .start = SDC1_IRQ_0,
487 .end = SDC1_IRQ_0
488 },
489#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
490 {
491 .name = "sdcc_dml_addr",
492 .start = MSM_SDC1_DML_BASE,
493 .end = MSM_SDC1_BAM_BASE - 1,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .name = "sdcc_bam_addr",
498 .start = MSM_SDC1_BAM_BASE,
499 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
500 .flags = IORESOURCE_MEM,
501 },
502 {
503 .name = "sdcc_bam_irq",
504 .start = SDC1_BAM_IRQ,
505 .end = SDC1_BAM_IRQ,
506 .flags = IORESOURCE_IRQ,
507 },
508#endif
509};
510
511static struct resource resources_sdc2[] = {
512 {
513 .name = "core_mem",
514 .flags = IORESOURCE_MEM,
515 .start = MSM_SDC2_BASE,
516 .end = MSM_SDC2_DML_BASE - 1,
517 },
518 {
519 .name = "core_irq",
520 .flags = IORESOURCE_IRQ,
521 .start = SDC2_IRQ_0,
522 .end = SDC2_IRQ_0
523 },
524#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
525 {
526 .name = "sdcc_dml_addr",
527 .start = MSM_SDC2_DML_BASE,
528 .end = MSM_SDC2_BAM_BASE - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 {
532 .name = "sdcc_bam_addr",
533 .start = MSM_SDC2_BAM_BASE,
534 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
535 .flags = IORESOURCE_MEM,
536 },
537 {
538 .name = "sdcc_bam_irq",
539 .start = SDC2_BAM_IRQ,
540 .end = SDC2_BAM_IRQ,
541 .flags = IORESOURCE_IRQ,
542 },
543#endif
544};
545
546static struct resource resources_sdc3[] = {
547 {
548 .name = "core_mem",
549 .flags = IORESOURCE_MEM,
550 .start = MSM_SDC3_BASE,
551 .end = MSM_SDC3_DML_BASE - 1,
552 },
553 {
554 .name = "core_irq",
555 .flags = IORESOURCE_IRQ,
556 .start = SDC3_IRQ_0,
557 .end = SDC3_IRQ_0
558 },
559#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
560 {
561 .name = "sdcc_dml_addr",
562 .start = MSM_SDC3_DML_BASE,
563 .end = MSM_SDC3_BAM_BASE - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 {
567 .name = "sdcc_bam_addr",
568 .start = MSM_SDC3_BAM_BASE,
569 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
570 .flags = IORESOURCE_MEM,
571 },
572 {
573 .name = "sdcc_bam_irq",
574 .start = SDC3_BAM_IRQ,
575 .end = SDC3_BAM_IRQ,
576 .flags = IORESOURCE_IRQ,
577 },
578#endif
579};
580
581static struct resource resources_sdc4[] = {
582 {
583 .name = "core_mem",
584 .flags = IORESOURCE_MEM,
585 .start = MSM_SDC4_BASE,
586 .end = MSM_SDC4_DML_BASE - 1,
587 },
588 {
589 .name = "core_irq",
590 .flags = IORESOURCE_IRQ,
591 .start = SDC4_IRQ_0,
592 .end = SDC4_IRQ_0
593 },
594#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
595 {
596 .name = "sdcc_dml_addr",
597 .start = MSM_SDC4_DML_BASE,
598 .end = MSM_SDC4_BAM_BASE - 1,
599 .flags = IORESOURCE_MEM,
600 },
601 {
602 .name = "sdcc_bam_addr",
603 .start = MSM_SDC4_BAM_BASE,
604 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
605 .flags = IORESOURCE_MEM,
606 },
607 {
608 .name = "sdcc_bam_irq",
609 .start = SDC4_BAM_IRQ,
610 .end = SDC4_BAM_IRQ,
611 .flags = IORESOURCE_IRQ,
612 },
613#endif
614};
615
616static struct resource resources_sdc5[] = {
617 {
618 .name = "core_mem",
619 .flags = IORESOURCE_MEM,
620 .start = MSM_SDC5_BASE,
621 .end = MSM_SDC5_DML_BASE - 1,
622 },
623 {
624 .name = "core_irq",
625 .flags = IORESOURCE_IRQ,
626 .start = SDC5_IRQ_0,
627 .end = SDC5_IRQ_0
628 },
629#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
630 {
631 .name = "sdcc_dml_addr",
632 .start = MSM_SDC5_DML_BASE,
633 .end = MSM_SDC5_BAM_BASE - 1,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 .name = "sdcc_bam_addr",
638 .start = MSM_SDC5_BAM_BASE,
639 .end = MSM_SDC5_BAM_BASE + (2 * SZ_4K) - 1,
640 .flags = IORESOURCE_MEM,
641 },
642 {
643 .name = "sdcc_bam_irq",
644 .start = SDC5_BAM_IRQ,
645 .end = SDC5_BAM_IRQ,
646 .flags = IORESOURCE_IRQ,
647 },
648#endif
649};
650
651struct platform_device msm_device_sdc1 = {
652 .name = "msm_sdcc",
653 .id = 1,
654 .num_resources = ARRAY_SIZE(resources_sdc1),
655 .resource = resources_sdc1,
656 .dev = {
657 .coherent_dma_mask = 0xffffffff,
658 },
659};
660
661struct platform_device msm_device_sdc2 = {
662 .name = "msm_sdcc",
663 .id = 2,
664 .num_resources = ARRAY_SIZE(resources_sdc2),
665 .resource = resources_sdc2,
666 .dev = {
667 .coherent_dma_mask = 0xffffffff,
668 },
669};
670
671struct platform_device msm_device_sdc3 = {
672 .name = "msm_sdcc",
673 .id = 3,
674 .num_resources = ARRAY_SIZE(resources_sdc3),
675 .resource = resources_sdc3,
676 .dev = {
677 .coherent_dma_mask = 0xffffffff,
678 },
679};
680
681struct platform_device msm_device_sdc4 = {
682 .name = "msm_sdcc",
683 .id = 4,
684 .num_resources = ARRAY_SIZE(resources_sdc4),
685 .resource = resources_sdc4,
686 .dev = {
687 .coherent_dma_mask = 0xffffffff,
688 },
689};
690
691struct platform_device msm_device_sdc5 = {
692 .name = "msm_sdcc",
693 .id = 5,
694 .num_resources = ARRAY_SIZE(resources_sdc5),
695 .resource = resources_sdc5,
696 .dev = {
697 .coherent_dma_mask = 0xffffffff,
698 },
699};
700
701struct platform_device msm_device_smd = {
702 .name = "msm_smd",
703 .id = -1,
704};
705
706struct platform_device msm_device_bam_dmux = {
707 .name = "BAM_RMNT",
708 .id = -1,
709};
710
711struct resource msm_dmov_resource[] = {
712 {
713 .start = ADM_0_SCSS_1_IRQ,
714 .end = (resource_size_t)MSM_DMOV_BASE,
715 .flags = IORESOURCE_IRQ,
716 },
717};
718
719struct platform_device msm_device_dmov = {
720 .name = "msm_dmov",
721 .id = -1,
722 .resource = msm_dmov_resource,
723 .num_resources = ARRAY_SIZE(msm_dmov_resource),
724};
725
726static struct platform_device *msm_sdcc_devices[] __initdata = {
727 &msm_device_sdc1,
728 &msm_device_sdc2,
729 &msm_device_sdc3,
730 &msm_device_sdc4,
731 &msm_device_sdc5,
732};
733
734int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
735{
736 struct platform_device *pdev;
737
738 if (controller < 1 || controller > 5)
739 return -EINVAL;
740
741 pdev = msm_sdcc_devices[controller-1];
742 pdev->dev.platform_data = plat;
743 return platform_device_register(pdev);
744}
745
746static struct resource resources_qup_i2c_gsbi4[] = {
747 {
748 .name = "gsbi_qup_i2c_addr",
749 .start = MSM_GSBI4_PHYS,
750 .end = MSM_GSBI4_PHYS + MSM_QUP_SIZE - 1,
751 .flags = IORESOURCE_MEM,
752 },
753 {
754 .name = "qup_phys_addr",
755 .start = MSM_GSBI4_QUP_PHYS,
756 .end = MSM_GSBI4_QUP_PHYS + 4 - 1,
757 .flags = IORESOURCE_MEM,
758 },
759 {
760 .name = "qup_err_intr",
761 .start = GSBI4_QUP_IRQ,
762 .end = GSBI4_QUP_IRQ,
763 .flags = IORESOURCE_IRQ,
764 },
765};
766
767struct platform_device msm8960_device_qup_i2c_gsbi4 = {
768 .name = "qup_i2c",
769 .id = 4,
770 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
771 .resource = resources_qup_i2c_gsbi4,
772};
773
774static struct resource resources_qup_i2c_gsbi3[] = {
775 {
776 .name = "gsbi_qup_i2c_addr",
777 .start = MSM_GSBI3_PHYS,
778 .end = MSM_GSBI3_PHYS + MSM_QUP_SIZE - 1,
779 .flags = IORESOURCE_MEM,
780 },
781 {
782 .name = "qup_phys_addr",
783 .start = MSM_GSBI3_QUP_PHYS,
784 .end = MSM_GSBI3_QUP_PHYS + 4 - 1,
785 .flags = IORESOURCE_MEM,
786 },
787 {
788 .name = "qup_err_intr",
789 .start = GSBI3_QUP_IRQ,
790 .end = GSBI3_QUP_IRQ,
791 .flags = IORESOURCE_IRQ,
792 },
793};
794
795struct platform_device msm8960_device_qup_i2c_gsbi3 = {
796 .name = "qup_i2c",
797 .id = 3,
798 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi3),
799 .resource = resources_qup_i2c_gsbi3,
800};
801
802static struct resource resources_qup_i2c_gsbi10[] = {
803 {
804 .name = "gsbi_qup_i2c_addr",
805 .start = MSM_GSBI10_PHYS,
806 .end = MSM_GSBI10_PHYS + MSM_QUP_SIZE - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 {
810 .name = "qup_phys_addr",
811 .start = MSM_GSBI10_QUP_PHYS,
812 .end = MSM_GSBI10_QUP_PHYS + 4 - 1,
813 .flags = IORESOURCE_MEM,
814 },
815 {
816 .name = "qup_err_intr",
817 .start = GSBI10_QUP_IRQ,
818 .end = GSBI10_QUP_IRQ,
819 .flags = IORESOURCE_IRQ,
820 },
821};
822
823struct platform_device msm8960_device_qup_i2c_gsbi10 = {
824 .name = "qup_i2c",
825 .id = 10,
826 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi10),
827 .resource = resources_qup_i2c_gsbi10,
828};
829
830static struct resource resources_qup_i2c_gsbi12[] = {
831 {
832 .name = "gsbi_qup_i2c_addr",
833 .start = MSM_GSBI12_PHYS,
834 .end = MSM_GSBI12_PHYS + MSM_QUP_SIZE - 1,
835 .flags = IORESOURCE_MEM,
836 },
837 {
838 .name = "qup_phys_addr",
839 .start = MSM_GSBI12_QUP_PHYS,
840 .end = MSM_GSBI12_QUP_PHYS + 4 - 1,
841 .flags = IORESOURCE_MEM,
842 },
843 {
844 .name = "qup_err_intr",
845 .start = GSBI12_QUP_IRQ,
846 .end = GSBI12_QUP_IRQ,
847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851struct platform_device msm8960_device_qup_i2c_gsbi12 = {
852 .name = "qup_i2c",
853 .id = 12,
854 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi12),
855 .resource = resources_qup_i2c_gsbi12,
856};
857
858#ifdef CONFIG_MSM_CAMERA
859struct resource msm_camera_resources[] = {
860 {
861 .name = "vfe",
862 .start = 0x04500000,
863 .end = 0x04500000 + SZ_1M - 1,
864 .flags = IORESOURCE_MEM,
865 },
866 {
867 .name = "vfe",
868 .start = VFE_IRQ,
869 .end = VFE_IRQ,
870 .flags = IORESOURCE_IRQ,
871 },
872 {
873 .name = "vid_buf",
874 .flags = IORESOURCE_DMA,
875 },
876 {
877 .name = "ispif",
878 .start = 0x04800800,
879 .end = 0x04800800 + SZ_1K - 1,
880 .flags = IORESOURCE_MEM,
881 },
882 {
883 .name = "ispif",
884 .start = ISPIF_IRQ,
885 .end = ISPIF_IRQ,
886 .flags = IORESOURCE_IRQ,
887 },
888 {
889 .name = "csid0",
890 .start = 0x04800000,
891 .end = 0x04800000 + SZ_1K - 1,
892 .flags = IORESOURCE_MEM,
893 },
894 {
895 .name = "csid0",
896 .start = CSI_0_IRQ,
897 .end = CSI_0_IRQ,
898 .flags = IORESOURCE_IRQ,
899 },
900 {
901 .name = "csiphy0",
902 .start = 0x04800C00,
903 .end = 0x04800C00 + SZ_1K - 1,
904 .flags = IORESOURCE_MEM,
905 },
906 {
907 .name = "csiphy0",
908 .start = CSIPHY_4LN_IRQ,
909 .end = CSIPHY_4LN_IRQ,
910 .flags = IORESOURCE_IRQ,
911 },
912 {
913 .name = "csid1",
914 .start = 0x04800400,
915 .end = 0x04800400 + SZ_1K - 1,
916 .flags = IORESOURCE_MEM,
917 },
918 {
919 .name = "csid1",
920 .start = CSI_1_IRQ,
921 .end = CSI_1_IRQ,
922 .flags = IORESOURCE_IRQ,
923 },
924 {
925 .name = "csiphy1",
926 .start = 0x04801000,
927 .end = 0x04801000 + SZ_1K - 1,
928 .flags = IORESOURCE_MEM,
929 },
930 {
931 .name = "csiphy1",
932 .start = MSM8960_CSIPHY_2LN_IRQ,
933 .end = MSM8960_CSIPHY_2LN_IRQ,
934 .flags = IORESOURCE_IRQ,
935 },
936};
937
938int __init msm_get_cam_resources(struct msm_camera_sensor_info *s_info)
939{
940 s_info->resource = msm_camera_resources;
941 s_info->num_resources = ARRAY_SIZE(msm_camera_resources);
942 return 0;
943}
944#endif
945
946static struct resource resources_ssbi_pm8921[] = {
947 {
948 .start = MSM_PMIC1_SSBI_CMD_PHYS,
949 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
950 .flags = IORESOURCE_MEM,
951 },
952};
953
954struct platform_device msm8960_device_ssbi_pm8921 = {
955 .name = "msm_ssbi",
956 .id = 0,
957 .resource = resources_ssbi_pm8921,
958 .num_resources = ARRAY_SIZE(resources_ssbi_pm8921),
959};
960
961static struct resource resources_qup_spi_gsbi1[] = {
962 {
963 .name = "spi_base",
964 .start = MSM_GSBI1_QUP_PHYS,
965 .end = MSM_GSBI1_QUP_PHYS + SZ_4K - 1,
966 .flags = IORESOURCE_MEM,
967 },
968 {
969 .name = "gsbi_base",
970 .start = MSM_GSBI1_PHYS,
971 .end = MSM_GSBI1_PHYS + 4 - 1,
972 .flags = IORESOURCE_MEM,
973 },
974 {
975 .name = "spi_irq_in",
976 .start = MSM8960_GSBI1_QUP_IRQ,
977 .end = MSM8960_GSBI1_QUP_IRQ,
978 .flags = IORESOURCE_IRQ,
979 },
980};
981
982struct platform_device msm8960_device_qup_spi_gsbi1 = {
983 .name = "spi_qsd",
984 .id = 0,
985 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi1),
986 .resource = resources_qup_spi_gsbi1,
987};
988
989struct platform_device msm_pcm = {
990 .name = "msm-pcm-dsp",
991 .id = -1,
992};
993
994struct platform_device msm_pcm_routing = {
995 .name = "msm-pcm-routing",
996 .id = -1,
997};
998
999struct platform_device msm_cpudai0 = {
1000 .name = "msm-dai-q6",
1001 .id = 0x4000,
1002};
1003
1004struct platform_device msm_cpudai1 = {
1005 .name = "msm-dai-q6",
1006 .id = 0x4001,
1007};
1008
1009struct platform_device msm_cpudai_hdmi_rx = {
1010 .name = "msm-dai-q6",
1011 .id = 8,
1012};
1013
1014struct platform_device msm_cpudai_bt_rx = {
1015 .name = "msm-dai-q6",
1016 .id = 0x3000,
1017};
1018
1019struct platform_device msm_cpudai_bt_tx = {
1020 .name = "msm-dai-q6",
1021 .id = 0x3001,
1022};
1023
1024struct platform_device msm_cpudai_fm_rx = {
1025 .name = "msm-dai-q6",
1026 .id = 0x3004,
1027};
1028
1029struct platform_device msm_cpudai_fm_tx = {
1030 .name = "msm-dai-q6",
1031 .id = 0x3005,
1032};
1033
1034struct platform_device msm_cpu_fe = {
1035 .name = "msm-dai-fe",
1036 .id = -1,
1037};
1038
1039struct platform_device msm_stub_codec = {
1040 .name = "msm-stub-codec",
1041 .id = 1,
1042};
1043
1044struct platform_device msm_voice = {
1045 .name = "msm-pcm-voice",
1046 .id = -1,
1047};
1048
1049struct platform_device msm_voip = {
1050 .name = "msm-voip-dsp",
1051 .id = -1,
1052};
1053
1054struct platform_device msm_lpa_pcm = {
1055 .name = "msm-pcm-lpa",
1056 .id = -1,
1057};
1058
1059struct platform_device msm_pcm_hostless = {
1060 .name = "msm-pcm-hostless",
1061 .id = -1,
1062};
1063
1064struct platform_device *msm_footswitch_devices[] = {
1065};
1066unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
1067
1068#ifdef CONFIG_MSM_ROTATOR
1069#define ROTATOR_HW_BASE 0x04E00000
1070static struct resource resources_msm_rotator[] = {
1071 {
1072 .start = ROTATOR_HW_BASE,
1073 .end = ROTATOR_HW_BASE + 0x100000 - 1,
1074 .flags = IORESOURCE_MEM,
1075 },
1076 {
1077 .start = ROT_IRQ,
1078 .end = ROT_IRQ,
1079 .flags = IORESOURCE_IRQ,
1080 },
1081};
1082
1083static struct msm_rot_clocks rotator_clocks[] = {
1084 {
1085 .clk_name = "rot_clk",
1086 .clk_type = ROTATOR_CORE_CLK,
1087 .clk_rate = 160 * 1000 * 1000,
1088 },
1089 {
1090 .clk_name = "rotator_pclk",
1091 .clk_type = ROTATOR_PCLK,
1092 .clk_rate = 0,
1093 },
1094 {
1095 .clk_name = "rot_axi_clk",
1096 .clk_type = ROTATOR_AXI_CLK,
1097 .clk_rate = 0,
1098 },
1099};
1100
1101static struct msm_rotator_platform_data rotator_pdata = {
1102 .number_of_clocks = ARRAY_SIZE(rotator_clocks),
1103 .hardware_version_number = 0x01020309,
1104 .rotator_clks = rotator_clocks,
1105 .regulator_name = "fs_rot",
1106};
1107
1108struct platform_device msm_rotator_device = {
1109 .name = "msm_rotator",
1110 .id = 0,
1111 .num_resources = ARRAY_SIZE(resources_msm_rotator),
1112 .resource = resources_msm_rotator,
1113 .dev = {
1114 .platform_data = &rotator_pdata,
1115 },
1116};
1117#endif
1118
1119#define MIPI_DSI_HW_BASE 0x04700000
1120#define MDP_HW_BASE 0x05100000
1121
1122static struct resource msm_mipi_dsi1_resources[] = {
1123 {
1124 .name = "mipi_dsi",
1125 .start = MIPI_DSI_HW_BASE,
1126 .end = MIPI_DSI_HW_BASE + 0x000F0000 - 1,
1127 .flags = IORESOURCE_MEM,
1128 },
1129 {
1130 .start = DSI1_IRQ,
1131 .end = DSI1_IRQ,
1132 .flags = IORESOURCE_IRQ,
1133 },
1134};
1135
1136struct platform_device msm_mipi_dsi1_device = {
1137 .name = "mipi_dsi",
1138 .id = 1,
1139 .num_resources = ARRAY_SIZE(msm_mipi_dsi1_resources),
1140 .resource = msm_mipi_dsi1_resources,
1141};
1142
1143static struct resource msm_mdp_resources[] = {
1144 {
1145 .name = "mdp",
1146 .start = MDP_HW_BASE,
1147 .end = MDP_HW_BASE + 0x000F0000 - 1,
1148 .flags = IORESOURCE_MEM,
1149 },
1150 {
1151 .start = MDP_IRQ,
1152 .end = MDP_IRQ,
1153 .flags = IORESOURCE_IRQ,
1154 },
1155};
1156
1157static struct platform_device msm_mdp_device = {
1158 .name = "mdp",
1159 .id = 0,
1160 .num_resources = ARRAY_SIZE(msm_mdp_resources),
1161 .resource = msm_mdp_resources,
1162};
1163
1164static void __init msm_register_device(struct platform_device *pdev, void *data)
1165{
1166 int ret;
1167
1168 pdev->dev.platform_data = data;
1169 ret = platform_device_register(pdev);
1170 if (ret)
1171 dev_err(&pdev->dev,
1172 "%s: platform_device_register() failed = %d\n",
1173 __func__, ret);
1174}
1175
Ravishangar Kalyanam882930f2011-07-08 17:51:52 -0700[diff] [blame]1176#ifdef CONFIG_MSM_BUS_SCALING
1177static struct platform_device msm_dtv_device = {
1178 .name = "dtv",
1179 .id = 0,
1180};
1181#endif
1182
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1183void __init msm_fb_register_device(char *name, void *data)
1184{
1185 if (!strncmp(name, "mdp", 3))
1186 msm_register_device(&msm_mdp_device, data);
1187 else if (!strncmp(name, "mipi_dsi", 8))
1188 msm_register_device(&msm_mipi_dsi1_device, data);
Ravishangar Kalyanam882930f2011-07-08 17:51:52 -0700[diff] [blame]1189#ifdef CONFIG_MSM_BUS_SCALING
1190 else if (!strncmp(name, "dtv", 3))
1191 msm_register_device(&msm_dtv_device, data);
1192#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1193 else
1194 printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
1195}
1196
1197static struct resource resources_sps[] = {
1198 {
1199 .name = "pipe_mem",
1200 .start = 0x12800000,
1201 .end = 0x12800000 + 0x4000 - 1,
1202 .flags = IORESOURCE_MEM,
1203 },
1204 {
1205 .name = "bamdma_dma",
1206 .start = 0x12240000,
1207 .end = 0x12240000 + 0x1000 - 1,
1208 .flags = IORESOURCE_MEM,
1209 },
1210 {
1211 .name = "bamdma_bam",
1212 .start = 0x12244000,
1213 .end = 0x12244000 + 0x4000 - 1,
1214 .flags = IORESOURCE_MEM,
1215 },
1216 {
1217 .name = "bamdma_irq",
1218 .start = SPS_BAM_DMA_IRQ,
1219 .end = SPS_BAM_DMA_IRQ,
1220 .flags = IORESOURCE_IRQ,
1221 },
1222};
1223
1224struct msm_sps_platform_data msm_sps_pdata = {
1225 .bamdma_restricted_pipes = 0x06,
1226};
1227
1228struct platform_device msm_device_sps = {
1229 .name = "msm_sps",
1230 .id = -1,
1231 .num_resources = ARRAY_SIZE(resources_sps),
1232 .resource = resources_sps,
1233 .dev.platform_data = &msm_sps_pdata,
1234};
1235
1236#ifdef CONFIG_MSM_MPM
1237static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
1238 [1] = MSM_GPIO_TO_INT(61),
1239 [4] = MSM_GPIO_TO_INT(87),
1240 [5] = MSM_GPIO_TO_INT(88),
1241 [6] = MSM_GPIO_TO_INT(89),
1242 [7] = MSM_GPIO_TO_INT(90),
1243 [8] = MSM_GPIO_TO_INT(91),
1244 [9] = MSM_GPIO_TO_INT(34),
1245 [10] = MSM_GPIO_TO_INT(38),
1246 [11] = MSM_GPIO_TO_INT(42),
1247 [12] = MSM_GPIO_TO_INT(46),
1248 [13] = MSM_GPIO_TO_INT(50),
1249 [14] = MSM_GPIO_TO_INT(54),
1250 [15] = MSM_GPIO_TO_INT(58),
1251 [16] = MSM_GPIO_TO_INT(63),
1252 [17] = MSM_GPIO_TO_INT(160),
1253 [18] = MSM_GPIO_TO_INT(162),
1254 [19] = MSM_GPIO_TO_INT(144),
1255 [20] = MSM_GPIO_TO_INT(146),
1256 [25] = USB1_HS_IRQ,
1257 [26] = TV_ENC_IRQ,
1258 [27] = HDMI_IRQ,
1259 [29] = MSM_GPIO_TO_INT(123),
1260 [30] = MSM_GPIO_TO_INT(172),
1261 [31] = MSM_GPIO_TO_INT(99),
1262 [32] = MSM_GPIO_TO_INT(96),
1263 [33] = MSM_GPIO_TO_INT(67),
1264 [34] = MSM_GPIO_TO_INT(71),
1265 [35] = MSM_GPIO_TO_INT(105),
1266 [36] = MSM_GPIO_TO_INT(117),
1267 [37] = MSM_GPIO_TO_INT(29),
1268 [38] = MSM_GPIO_TO_INT(30),
1269 [39] = MSM_GPIO_TO_INT(31),
1270 [40] = MSM_GPIO_TO_INT(37),
1271 [41] = MSM_GPIO_TO_INT(40),
1272 [42] = MSM_GPIO_TO_INT(41),
1273 [43] = MSM_GPIO_TO_INT(45),
1274 [44] = MSM_GPIO_TO_INT(51),
1275 [45] = MSM_GPIO_TO_INT(52),
1276 [46] = MSM_GPIO_TO_INT(57),
1277 [47] = MSM_GPIO_TO_INT(73),
1278 [48] = MSM_GPIO_TO_INT(93),
1279 [49] = MSM_GPIO_TO_INT(94),
1280 [50] = MSM_GPIO_TO_INT(103),
1281 [51] = MSM_GPIO_TO_INT(104),
1282 [52] = MSM_GPIO_TO_INT(106),
1283 [53] = MSM_GPIO_TO_INT(115),
1284 [54] = MSM_GPIO_TO_INT(124),
1285 [55] = MSM_GPIO_TO_INT(125),
1286 [56] = MSM_GPIO_TO_INT(126),
1287 [57] = MSM_GPIO_TO_INT(127),
1288 [58] = MSM_GPIO_TO_INT(128),
1289 [59] = MSM_GPIO_TO_INT(129),
1290};
1291
1292static uint16_t msm_mpm_bypassed_apps_irqs[] = {
1293 TLMM_MSM_SUMMARY_IRQ,
1294 RPM_APCC_CPU0_GP_HIGH_IRQ,
1295 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1296 RPM_APCC_CPU0_GP_LOW_IRQ,
1297 RPM_APCC_CPU0_WAKE_UP_IRQ,
1298 RPM_APCC_CPU1_GP_HIGH_IRQ,
1299 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
1300 RPM_APCC_CPU1_GP_LOW_IRQ,
1301 RPM_APCC_CPU1_WAKE_UP_IRQ,
1302 MSS_TO_APPS_IRQ_0,
1303 MSS_TO_APPS_IRQ_1,
1304 MSS_TO_APPS_IRQ_2,
1305 MSS_TO_APPS_IRQ_3,
1306 MSS_TO_APPS_IRQ_4,
1307 MSS_TO_APPS_IRQ_5,
1308 MSS_TO_APPS_IRQ_6,
1309 MSS_TO_APPS_IRQ_7,
1310 MSS_TO_APPS_IRQ_8,
1311 MSS_TO_APPS_IRQ_9,
1312 LPASS_SCSS_GP_LOW_IRQ,
1313 LPASS_SCSS_GP_MEDIUM_IRQ,
1314 LPASS_SCSS_GP_HIGH_IRQ,
1315 SPS_MTI_31,
1316};
1317
1318struct msm_mpm_device_data msm_mpm_dev_data = {
1319 .irqs_m2a = msm_mpm_irqs_m2a,
1320 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
1321 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
1322 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
1323 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
1324 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
1325 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
1326 .mpm_apps_ipc_val = BIT(1),
1327 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1328
1329};
1330#endif
1331
1332struct clk_lookup msm_clocks_8960_dummy[] = {
1333 CLK_DUMMY("pll2", PLL2, NULL, 0),
1334 CLK_DUMMY("pll8", PLL8, NULL, 0),
1335 CLK_DUMMY("pll4", PLL4, NULL, 0),
1336
1337 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
1338 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
1339 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
1340 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
1341 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1342 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
1343 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
1344 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
1345 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
1346 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
1347 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
1348 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
1349 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
1350 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
1351 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
1352 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
1353
1354 CLK_DUMMY("gsbi_uart_clk", GSBI1_UART_CLK, NULL, OFF),
1355 CLK_DUMMY("gsbi_uart_clk", GSBI2_UART_CLK,
1356 "msm_serial_hsl.0", OFF),
1357 CLK_DUMMY("gsbi_uart_clk", GSBI3_UART_CLK, NULL, OFF),
1358 CLK_DUMMY("gsbi_uart_clk", GSBI4_UART_CLK, NULL, OFF),
1359 CLK_DUMMY("gsbi_uart_clk", GSBI5_UART_CLK, NULL, OFF),
1360 CLK_DUMMY("uartdm_clk", GSBI6_UART_CLK, NULL, OFF),
1361 CLK_DUMMY("gsbi_uart_clk", GSBI7_UART_CLK, NULL, OFF),
1362 CLK_DUMMY("gsbi_uart_clk", GSBI8_UART_CLK, NULL, OFF),
1363 CLK_DUMMY("gsbi_uart_clk", GSBI9_UART_CLK, NULL, OFF),
1364 CLK_DUMMY("gsbi_uart_clk", GSBI10_UART_CLK, NULL, OFF),
1365 CLK_DUMMY("gsbi_uart_clk", GSBI11_UART_CLK, NULL, OFF),
1366 CLK_DUMMY("gsbi_uart_clk", GSBI12_UART_CLK, NULL, OFF),
1367 CLK_DUMMY("spi_clk", GSBI1_QUP_CLK, "spi_qsd.0", OFF),
1368 CLK_DUMMY("gsbi_qup_clk", GSBI2_QUP_CLK, NULL, OFF),
1369 CLK_DUMMY("gsbi_qup_clk", GSBI3_QUP_CLK, NULL, OFF),
1370 CLK_DUMMY("gsbi_qup_clk", GSBI4_QUP_CLK,
1371 "qup_i2c.4", OFF),
1372 CLK_DUMMY("gsbi_qup_clk", GSBI5_QUP_CLK, NULL, OFF),
1373 CLK_DUMMY("gsbi_qup_clk", GSBI6_QUP_CLK, NULL, OFF),
1374 CLK_DUMMY("gsbi_qup_clk", GSBI7_QUP_CLK, NULL, OFF),
1375 CLK_DUMMY("gsbi_qup_clk", GSBI8_QUP_CLK, NULL, OFF),
1376 CLK_DUMMY("gsbi_qup_clk", GSBI9_QUP_CLK, NULL, OFF),
1377 CLK_DUMMY("gsbi_qup_clk", GSBI10_QUP_CLK, NULL, OFF),
1378 CLK_DUMMY("gsbi_qup_clk", GSBI11_QUP_CLK, NULL, OFF),
1379 CLK_DUMMY("gsbi_qup_clk", GSBI12_QUP_CLK, NULL, OFF),
1380 CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
1381 CLK_DUMMY("pmem_clk", PMEM_CLK, NULL, OFF),
1382 CLK_DUMMY("prng_clk", PRNG_CLK, NULL, OFF),
1383 CLK_DUMMY("sdc_clk", SDC1_CLK, NULL, OFF),
1384 CLK_DUMMY("sdc_clk", SDC2_CLK, NULL, OFF),
1385 CLK_DUMMY("sdc_clk", SDC3_CLK, NULL, OFF),
1386 CLK_DUMMY("sdc_clk", SDC4_CLK, NULL, OFF),
1387 CLK_DUMMY("sdc_clk", SDC5_CLK, NULL, OFF),
1388 CLK_DUMMY("tsif_ref_clk", TSIF_REF_CLK, NULL, OFF),
1389 CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
1390 CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
1391 CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
1392 CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
1393 CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
1394 CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
1395 CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL, OFF),
1396 CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL, OFF),
1397 CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
1398 CLK_DUMMY("ce_pclk", CE2_CLK, NULL, OFF),
1399 CLK_DUMMY("ce_clk", CE1_CORE_CLK, NULL, OFF),
1400 CLK_DUMMY("spi_pclk", GSBI1_P_CLK, "spi_qsd.0", OFF),
1401 CLK_DUMMY("gsbi_pclk", GSBI2_P_CLK,
1402 "msm_serial_hsl.0", OFF),
1403 CLK_DUMMY("gsbi_pclk", GSBI3_P_CLK, NULL, OFF),
1404 CLK_DUMMY("gsbi_pclk", GSBI4_P_CLK,
1405 "qup_i2c.4", OFF),
1406 CLK_DUMMY("gsbi_pclk", GSBI5_P_CLK, NULL, OFF),
1407 CLK_DUMMY("uartdm_pclk", GSBI6_P_CLK, NULL, OFF),
1408 CLK_DUMMY("gsbi_pclk", GSBI7_P_CLK, NULL, OFF),
1409 CLK_DUMMY("gsbi_pclk", GSBI8_P_CLK, NULL, OFF),
1410 CLK_DUMMY("gsbi_pclk", GSBI9_P_CLK, NULL, OFF),
1411 CLK_DUMMY("gsbi_pclk", GSBI10_P_CLK, NULL, OFF),
1412 CLK_DUMMY("gsbi_pclk", GSBI11_P_CLK, NULL, OFF),
1413 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
1414 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
1415 CLK_DUMMY("tsif_pclk", TSIF_P_CLK, NULL, OFF),
1416 CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
1417 CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL, OFF),
1418 CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
1419 CLK_DUMMY("sdc_pclk", SDC1_P_CLK, NULL, OFF),
1420 CLK_DUMMY("sdc_pclk", SDC2_P_CLK, NULL, OFF),
1421 CLK_DUMMY("sdc_pclk", SDC3_P_CLK, NULL, OFF),
1422 CLK_DUMMY("sdc_pclk", SDC4_P_CLK, NULL, OFF),
1423 CLK_DUMMY("sdc_pclk", SDC5_P_CLK, NULL, OFF),
1424 CLK_DUMMY("adm_clk", ADM0_CLK, NULL, OFF),
1425 CLK_DUMMY("adm_pclk", ADM0_P_CLK, NULL, OFF),
1426 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
1427 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
1428 CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
1429 CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
1430 CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
1431 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
1432 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
1433 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
1434 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
1435 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
1436 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
1437 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
1438 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
1439 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
1440 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
1441 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
1442 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, "mipi_dsi.1", OFF),
1443 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, "mipi_dsi.2", OFF),
1444 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, "mipi_dsi.1", OFF),
1445 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, "mipi_dsi.2", OFF),
1446 CLK_DUMMY("gfx2d0_clk", GFX2D0_CLK, NULL, OFF),
1447 CLK_DUMMY("gfx2d1_clk", GFX2D1_CLK, NULL, OFF),
1448 CLK_DUMMY("gfx3d_clk", GFX3D_CLK, NULL, OFF),
1449 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
1450 CLK_DUMMY("imem_clk", IMEM_CLK, NULL, OFF),
1451 CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
1452 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
1453 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
1454 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
1455 CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
1456 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
1457 CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
1458 CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
1459 CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
1460 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
1461 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
1462 CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
1463 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
1464 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
1465 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
1466 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
1467 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
1468 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
1469 CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
1470 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
1471 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
1472 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
1473 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
1474 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
1475 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
1476 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, "mipi_dsi.1", OFF),
1477 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, "mipi_dsi.1", OFF),
1478 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, "mipi_dsi.2", OFF),
1479 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, "mipi_dsi.2", OFF),
1480 CLK_DUMMY("gfx2d0_pclk", GFX2D0_P_CLK, NULL, OFF),
1481 CLK_DUMMY("gfx2d1_pclk", GFX2D1_P_CLK, NULL, OFF),
1482 CLK_DUMMY("gfx3d_pclk", GFX3D_P_CLK, NULL, OFF),
1483 CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
1484 CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
1485 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
1486 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
1487 CLK_DUMMY("imem_pclk", IMEM_P_CLK, NULL, OFF),
1488 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
1489 CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
1490 CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
1491 CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
1492 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
1493 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
1494 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
1495 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
1496 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
1497 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
1498 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
1499 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
1500 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
1501 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
1502 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
1503 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
1504 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
1505 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
1506 CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
1507 CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
1508 CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
1509 CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
1510 CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
1511 CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
1512
1513 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
1514 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
1515 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC1_CLK, "msm_sdcc.1", 0),
1516 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC2_CLK, "msm_sdcc.2", 0),
1517 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC3_CLK, "msm_sdcc.3", 0),
1518 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC4_CLK, "msm_sdcc.4", 0),
1519 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC5_CLK, "msm_sdcc.5", 0),
1520 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1521 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
1522};
1523
1524unsigned msm_num_clocks_8960_dummy = ARRAY_SIZE(msm_clocks_8960_dummy);
1525
1526#define LPASS_SLIMBUS_PHYS 0x28080000
1527#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
1528/* Board info for the slimbus slave device */
1529static struct resource slimbus_res[] = {
1530 {
1531 .start = LPASS_SLIMBUS_PHYS,
1532 .end = LPASS_SLIMBUS_PHYS + 8191,
1533 .flags = IORESOURCE_MEM,
1534 .name = "slimbus_physical",
1535 },
1536 {
1537 .start = LPASS_SLIMBUS_BAM_PHYS,
1538 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
1539 .flags = IORESOURCE_MEM,
1540 .name = "slimbus_bam_physical",
1541 },
1542 {
1543 .start = SLIMBUS0_CORE_EE1_IRQ,
1544 .end = SLIMBUS0_CORE_EE1_IRQ,
1545 .flags = IORESOURCE_IRQ,
1546 .name = "slimbus_irq",
1547 },
1548 {
1549 .start = SLIMBUS0_BAM_EE1_IRQ,
1550 .end = SLIMBUS0_BAM_EE1_IRQ,
1551 .flags = IORESOURCE_IRQ,
1552 .name = "slimbus_bam_irq",
1553 },
1554};
1555
1556struct platform_device msm_slim_ctrl = {
1557 .name = "msm_slim_ctrl",
1558 .id = 1,
1559 .num_resources = ARRAY_SIZE(slimbus_res),
1560 .resource = slimbus_res,
1561 .dev = {
1562 .coherent_dma_mask = 0xffffffffULL,
1563 },
1564};
1565
1566#ifdef CONFIG_MSM_BUS_SCALING
1567static struct msm_bus_vectors grp3d_init_vectors[] = {
1568 {
1569 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1570 .dst = MSM_BUS_SLAVE_EBI_CH0,
1571 .ab = 0,
1572 .ib = 0,
1573 },
1574};
1575
1576static struct msm_bus_vectors grp3d_nominal_vectors[] = {
1577 {
1578 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1579 .dst = MSM_BUS_SLAVE_EBI_CH0,
1580 .ab = 0,
1581 .ib = 200800000U,
1582 },
1583};
1584
1585static struct msm_bus_vectors grp3d_max_vectors[] = {
1586 {
1587 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1588 .dst = MSM_BUS_SLAVE_EBI_CH0,
1589 .ab = 0,
1590 .ib = 2096000000U,
1591 },
1592};
1593
1594static struct msm_bus_paths grp3d_bus_scale_usecases[] = {
1595 {
1596 ARRAY_SIZE(grp3d_init_vectors),
1597 grp3d_init_vectors,
1598 },
1599 {
1600 ARRAY_SIZE(grp3d_nominal_vectors),
1601 grp3d_nominal_vectors,
1602 },
1603 {
1604 ARRAY_SIZE(grp3d_max_vectors),
1605 grp3d_max_vectors,
1606 },
1607};
1608
1609static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = {
1610 grp3d_bus_scale_usecases,
1611 ARRAY_SIZE(grp3d_bus_scale_usecases),
1612 .name = "grp3d",
1613};
1614
1615static struct msm_bus_vectors grp2d0_init_vectors[] = {
1616 {
1617 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1618 .dst = MSM_BUS_SLAVE_EBI_CH0,
1619 .ab = 0,
1620 .ib = 0,
1621 },
1622};
1623
1624static struct msm_bus_vectors grp2d0_max_vectors[] = {
1625 {
1626 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1627 .dst = MSM_BUS_SLAVE_EBI_CH0,
1628 .ab = 0,
1629 .ib = 248000000,
1630 },
1631};
1632
1633static struct msm_bus_paths grp2d0_bus_scale_usecases[] = {
1634 {
1635 ARRAY_SIZE(grp2d0_init_vectors),
1636 grp2d0_init_vectors,
1637 },
1638 {
1639 ARRAY_SIZE(grp2d0_max_vectors),
1640 grp2d0_max_vectors,
1641 },
1642};
1643
1644struct msm_bus_scale_pdata grp2d0_bus_scale_pdata = {
1645 grp2d0_bus_scale_usecases,
1646 ARRAY_SIZE(grp2d0_bus_scale_usecases),
1647 .name = "grp2d0",
1648};
1649
1650static struct msm_bus_vectors grp2d1_init_vectors[] = {
1651 {
1652 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1653 .dst = MSM_BUS_SLAVE_EBI_CH0,
1654 .ab = 0,
1655 .ib = 0,
1656 },
1657};
1658
1659static struct msm_bus_vectors grp2d1_max_vectors[] = {
1660 {
1661 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1662 .dst = MSM_BUS_SLAVE_EBI_CH0,
1663 .ab = 0,
1664 .ib = 248000000,
1665 },
1666};
1667
1668static struct msm_bus_paths grp2d1_bus_scale_usecases[] = {
1669 {
1670 ARRAY_SIZE(grp2d1_init_vectors),
1671 grp2d1_init_vectors,
1672 },
1673 {
1674 ARRAY_SIZE(grp2d1_max_vectors),
1675 grp2d1_max_vectors,
1676 },
1677};
1678
1679struct msm_bus_scale_pdata grp2d1_bus_scale_pdata = {
1680 grp2d1_bus_scale_usecases,
1681 ARRAY_SIZE(grp2d1_bus_scale_usecases),
1682 .name = "grp2d1",
1683};
1684#endif
1685
1686static struct resource kgsl_3d0_resources[] = {
1687 {
1688 .name = KGSL_3D0_REG_MEMORY,
1689 .start = 0x04300000, /* GFX3D address */
1690 .end = 0x0431ffff,
1691 .flags = IORESOURCE_MEM,
1692 },
1693 {
1694 .name = KGSL_3D0_IRQ,
1695 .start = GFX3D_IRQ,
1696 .end = GFX3D_IRQ,
1697 .flags = IORESOURCE_IRQ,
1698 },
1699};
1700
1701static struct kgsl_device_platform_data kgsl_3d0_pdata = {
1702 .pwr_data = {
1703 .pwrlevel = {
1704 {
1705 .gpu_freq = 266667000,
1706 .bus_freq = 2,
1707 },
1708 {
1709 .gpu_freq = 228571000,
1710 .bus_freq = 1,
1711 },
1712 {
1713 .gpu_freq = 266667000,
1714 .bus_freq = 0,
1715 },
1716 },
1717 .init_level = 0,
1718 .num_levels = 3,
1719 .set_grp_async = NULL,
1720 .idle_timeout = HZ/5,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1721 .nap_allowed = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1722 },
1723 .clk = {
1724 .name = {
1725 .clk = "gfx3d_clk",
1726 .pclk = "gfx3d_pclk",
1727 },
1728#ifdef CONFIG_MSM_BUS_SCALING
1729 .bus_scale_table = &grp3d_bus_scale_pdata,
1730#endif
1731 },
1732 .imem_clk_name = {
1733 .clk = NULL,
1734 .pclk = "imem_pclk",
1735 },
1736};
1737
1738struct platform_device msm_kgsl_3d0 = {
1739 .name = "kgsl-3d0",
1740 .id = 0,
1741 .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
1742 .resource = kgsl_3d0_resources,
1743 .dev = {
1744 .platform_data = &kgsl_3d0_pdata,
1745 },
1746};
1747
1748static struct resource kgsl_2d0_resources[] = {
1749 {
1750 .name = KGSL_2D0_REG_MEMORY,
1751 .start = 0x04100000, /* Z180 base address */
1752 .end = 0x04100FFF,
1753 .flags = IORESOURCE_MEM,
1754 },
1755 {
1756 .name = KGSL_2D0_IRQ,
1757 .start = GFX2D0_IRQ,
1758 .end = GFX2D0_IRQ,
1759 .flags = IORESOURCE_IRQ,
1760 },
1761};
1762
1763static struct kgsl_device_platform_data kgsl_2d0_pdata = {
1764 .pwr_data = {
1765 .pwrlevel = {
1766 {
1767 .gpu_freq = 200000000,
1768 .bus_freq = 1,
1769 },
1770 {
1771 .gpu_freq = 200000000,
1772 .bus_freq = 0,
1773 },
1774 },
1775 .init_level = 0,
1776 .num_levels = 2,
1777 .set_grp_async = NULL,
1778 .idle_timeout = HZ/10,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1779 .nap_allowed = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1780 },
1781 .clk = {
1782 .name = {
1783 /* note: 2d clocks disabled on v1 */
1784 .clk = "gfx2d0_clk",
1785 .pclk = "gfx2d0_pclk",
1786 },
1787#ifdef CONFIG_MSM_BUS_SCALING
1788 .bus_scale_table = &grp2d0_bus_scale_pdata,
1789#endif
1790 },
1791};
1792
1793struct platform_device msm_kgsl_2d0 = {
1794 .name = "kgsl-2d0",
1795 .id = 0,
1796 .num_resources = ARRAY_SIZE(kgsl_2d0_resources),
1797 .resource = kgsl_2d0_resources,
1798 .dev = {
1799 .platform_data = &kgsl_2d0_pdata,
1800 },
1801};
1802
1803static struct resource kgsl_2d1_resources[] = {
1804 {
1805 .name = KGSL_2D1_REG_MEMORY,
1806 .start = 0x04200000, /* Z180 device 1 base address */
1807 .end = 0x04200FFF,
1808 .flags = IORESOURCE_MEM,
1809 },
1810 {
1811 .name = KGSL_2D1_IRQ,
1812 .start = GFX2D1_IRQ,
1813 .end = GFX2D1_IRQ,
1814 .flags = IORESOURCE_IRQ,
1815 },
1816};
1817
1818static struct kgsl_device_platform_data kgsl_2d1_pdata = {
1819 .pwr_data = {
1820 .pwrlevel = {
1821 {
1822 .gpu_freq = 200000000,
1823 .bus_freq = 1,
1824 },
1825 {
1826 .gpu_freq = 200000000,
1827 .bus_freq = 0,
1828 },
1829 },
1830 .init_level = 0,
1831 .num_levels = 2,
1832 .set_grp_async = NULL,
1833 .idle_timeout = HZ/10,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1834 .nap_allowed = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1835 },
1836 .clk = {
1837 .name = {
1838 .clk = "gfx2d1_clk",
1839 .pclk = "gfx2d1_pclk",
1840 },
1841#ifdef CONFIG_MSM_BUS_SCALING
1842 .bus_scale_table = &grp2d1_bus_scale_pdata,
1843#endif
1844 },
1845};
1846
1847struct platform_device msm_kgsl_2d1 = {
1848 .name = "kgsl-2d1",
1849 .id = 1,
1850 .num_resources = ARRAY_SIZE(kgsl_2d1_resources),
1851 .resource = kgsl_2d1_resources,
1852 .dev = {
1853 .platform_data = &kgsl_2d1_pdata,
1854 },
1855};
1856
1857#ifdef CONFIG_MSM_GEMINI
1858static struct resource msm_gemini_resources[] = {
1859 {
1860 .start = 0x04600000,
1861 .end = 0x04600000 + SZ_1M - 1,
1862 .flags = IORESOURCE_MEM,
1863 },
1864 {
1865 .start = JPEG_IRQ,
1866 .end = JPEG_IRQ,
1867 .flags = IORESOURCE_IRQ,
1868 },
1869};
1870
1871struct platform_device msm8960_gemini_device = {
1872 .name = "msm_gemini",
1873 .resource = msm_gemini_resources,
1874 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1875};
1876#endif
1877
1878struct msm_rpm_map_data rpm_map_data[] __initdata = {
1879 MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
1880 MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
1881
1882 MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
1883
1884 MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
1885 MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
1886 MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
1887 MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
1888 MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
1889 MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
1890 MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
1891 MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
1892 MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
1893 MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
1894
1895 MSM_RPM_MAP(APPS_FABRIC_CFG_HALT_0, APPS_FABRIC_CFG_HALT, 2),
1896 MSM_RPM_MAP(APPS_FABRIC_CFG_CLKMOD_0, APPS_FABRIC_CFG_CLKMOD, 3),
1897 MSM_RPM_MAP(APPS_FABRIC_CFG_IOCTL, APPS_FABRIC_CFG_IOCTL, 1),
1898 MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
1899
1900 MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
1901 MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
1902 MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
Eugene Seahd9040ad2011-07-11 13:20:54 -0600[diff] [blame^]1903 MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1904
1905 MSM_RPM_MAP(MMSS_FABRIC_CFG_HALT_0, MMSS_FABRIC_CFG_HALT, 2),
1906 MSM_RPM_MAP(MMSS_FABRIC_CFG_CLKMOD_0, MMSS_FABRIC_CFG_CLKMOD, 3),
1907 MSM_RPM_MAP(MMSS_FABRIC_CFG_IOCTL, MMSS_FABRIC_CFG_IOCTL, 1),
1908 MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
1909
1910 MSM_RPM_MAP(PM8921_S1_0, PM8921_S1, 2),
1911 MSM_RPM_MAP(PM8921_S2_0, PM8921_S2, 2),
1912 MSM_RPM_MAP(PM8921_S3_0, PM8921_S3, 2),
1913 MSM_RPM_MAP(PM8921_S4_0, PM8921_S4, 2),
1914 MSM_RPM_MAP(PM8921_S5_0, PM8921_S5, 2),
1915 MSM_RPM_MAP(PM8921_S6_0, PM8921_S6, 2),
1916 MSM_RPM_MAP(PM8921_S7_0, PM8921_S7, 2),
1917 MSM_RPM_MAP(PM8921_S8_0, PM8921_S8, 2),
1918 MSM_RPM_MAP(PM8921_L1_0, PM8921_L1, 2),
1919 MSM_RPM_MAP(PM8921_L2_0, PM8921_L2, 2),
1920 MSM_RPM_MAP(PM8921_L3_0, PM8921_L3, 2),
1921 MSM_RPM_MAP(PM8921_L4_0, PM8921_L4, 2),
1922 MSM_RPM_MAP(PM8921_L5_0, PM8921_L5, 2),
1923 MSM_RPM_MAP(PM8921_L6_0, PM8921_L6, 2),
1924 MSM_RPM_MAP(PM8921_L7_0, PM8921_L7, 2),
1925 MSM_RPM_MAP(PM8921_L8_0, PM8921_L8, 2),
1926 MSM_RPM_MAP(PM8921_L9_0, PM8921_L9, 2),
1927 MSM_RPM_MAP(PM8921_L10_0, PM8921_L10, 2),
1928 MSM_RPM_MAP(PM8921_L11_0, PM8921_L11, 2),
1929 MSM_RPM_MAP(PM8921_L12_0, PM8921_L12, 2),
1930 MSM_RPM_MAP(PM8921_L13_0, PM8921_L13, 2),
1931 MSM_RPM_MAP(PM8921_L14_0, PM8921_L14, 2),
1932 MSM_RPM_MAP(PM8921_L15_0, PM8921_L15, 2),
1933 MSM_RPM_MAP(PM8921_L16_0, PM8921_L16, 2),
1934 MSM_RPM_MAP(PM8921_L17_0, PM8921_L17, 2),
1935 MSM_RPM_MAP(PM8921_L18_0, PM8921_L18, 2),
1936 MSM_RPM_MAP(PM8921_L19_0, PM8921_L19, 2),
1937 MSM_RPM_MAP(PM8921_L20_0, PM8921_L20, 2),
1938 MSM_RPM_MAP(PM8921_L21_0, PM8921_L21, 2),
1939 MSM_RPM_MAP(PM8921_L22_0, PM8921_L22, 2),
1940 MSM_RPM_MAP(PM8921_L23_0, PM8921_L23, 2),
1941 MSM_RPM_MAP(PM8921_L24_0, PM8921_L24, 2),
1942 MSM_RPM_MAP(PM8921_L25_0, PM8921_L25, 2),
1943 MSM_RPM_MAP(PM8921_L26_0, PM8921_L26, 2),
1944 MSM_RPM_MAP(PM8921_L27_0, PM8921_L27, 2),
1945 MSM_RPM_MAP(PM8921_L28_0, PM8921_L28, 2),
1946 MSM_RPM_MAP(PM8921_L29_0, PM8921_L29, 2),
1947 MSM_RPM_MAP(PM8921_CLK1_0, PM8921_CLK1, 2),
1948 MSM_RPM_MAP(PM8921_CLK2_0, PM8921_CLK2, 2),
1949 MSM_RPM_MAP(PM8921_LVS1, PM8921_LVS1, 1),
1950 MSM_RPM_MAP(PM8921_LVS2, PM8921_LVS2, 1),
1951 MSM_RPM_MAP(PM8921_LVS3, PM8921_LVS3, 1),
1952 MSM_RPM_MAP(PM8921_LVS4, PM8921_LVS4, 1),
1953 MSM_RPM_MAP(PM8921_LVS5, PM8921_LVS5, 1),
1954 MSM_RPM_MAP(PM8921_LVS6, PM8921_LVS6, 1),
1955 MSM_RPM_MAP(PM8921_LVS7, PM8921_LVS7, 1),
1956 MSM_RPM_MAP(NCP_0, NCP, 2),
1957 MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
1958 MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
1959 MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
1960
1961};
1962unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
1963
1964struct platform_device msm_bus_sys_fabric = {
1965 .name = "msm_bus_fabric",
1966 .id = MSM_BUS_FAB_SYSTEM,
1967};
1968struct platform_device msm_bus_apps_fabric = {
1969 .name = "msm_bus_fabric",
1970 .id = MSM_BUS_FAB_APPSS,
1971};
1972struct platform_device msm_bus_mm_fabric = {
1973 .name = "msm_bus_fabric",
1974 .id = MSM_BUS_FAB_MMSS,
1975};
1976struct platform_device msm_bus_sys_fpb = {
1977 .name = "msm_bus_fabric",
1978 .id = MSM_BUS_FAB_SYSTEM_FPB,
1979};
1980struct platform_device msm_bus_cpss_fpb = {
1981 .name = "msm_bus_fabric",
1982 .id = MSM_BUS_FAB_CPSS_FPB,
1983};
1984
1985/* Sensors DSPS platform data */
1986#ifdef CONFIG_MSM_DSPS
1987
1988#define PPSS_REG_PHYS_BASE 0x12080000
1989
1990static struct dsps_clk_info dsps_clks[] = {};
1991static struct dsps_regulator_info dsps_regs[] = {};
1992
1993/*
1994 * Note: GPIOs field is intialized in run-time at the function
1995 * msm8960_init_dsps().
1996 */
1997
1998struct msm_dsps_platform_data msm_dsps_pdata = {
1999 .clks = dsps_clks,
2000 .clks_num = ARRAY_SIZE(dsps_clks),
2001 .gpios = NULL,
2002 .gpios_num = 0,
2003 .regs = dsps_regs,
2004 .regs_num = ARRAY_SIZE(dsps_regs),
2005 .dsps_pwr_ctl_en = 1,
2006 .signature = DSPS_SIGNATURE,
2007};
2008
2009static struct resource msm_dsps_resources[] = {
2010 {
2011 .start = PPSS_REG_PHYS_BASE,
2012 .end = PPSS_REG_PHYS_BASE + SZ_8K - 1,
2013 .name = "ppss_reg",
2014 .flags = IORESOURCE_MEM,
2015 },
2016};
2017
2018struct platform_device msm_dsps_device = {
2019 .name = "msm_dsps",
2020 .id = 0,
2021 .num_resources = ARRAY_SIZE(msm_dsps_resources),
2022 .resource = msm_dsps_resources,
2023 .dev.platform_data = &msm_dsps_pdata,
2024};
2025
2026#endif /* CONFIG_MSM_DSPS */