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review.evervolv.com / android_kernel_htc_msm8960 / d9d4dae5bcce09f3dd90a1ba4837ef6dc6342fdc / . / drivers / mtd / devices / msm_nand.c
blob: 3675d2cb64d670d255798e295de80f2277f219a6 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/*
2 * Copyright (C) 2007 Google, Inc.
Krishna Konda99e362f2012-02-29 21:16:34 -0800[diff] [blame]3 * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/slab.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
22#include <linux/platform_device.h>
23#include <linux/sched.h>
24#include <linux/dma-mapping.h>
25#include <linux/io.h>
26#include <linux/crc16.h>
27#include <linux/bitrev.h>
28
29#include <asm/dma.h>
30#include <asm/mach/flash.h>
31
32#include <mach/dma.h>
33
34#include "msm_nand.h"
35
36unsigned long msm_nand_phys;
37unsigned long msm_nandc01_phys;
38unsigned long msm_nandc10_phys;
39unsigned long msm_nandc11_phys;
40unsigned long ebi2_register_base;
41uint32_t dual_nand_ctlr_present;
42uint32_t interleave_enable;
43uint32_t enable_bch_ecc;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]44
45#define MSM_NAND_DMA_BUFFER_SIZE SZ_8K
46#define MSM_NAND_DMA_BUFFER_SLOTS \
47 (MSM_NAND_DMA_BUFFER_SIZE / (sizeof(((atomic_t *)0)->counter) * 8))
48
49#define MSM_NAND_CFG0_RAW_ONFI_IDENTIFIER 0x88000800
50#define MSM_NAND_CFG0_RAW_ONFI_PARAM_INFO 0x88040000
51#define MSM_NAND_CFG1_RAW_ONFI_IDENTIFIER 0x0005045d
52#define MSM_NAND_CFG1_RAW_ONFI_PARAM_INFO 0x0005045d
53
54#define ONFI_IDENTIFIER_LENGTH 0x0004
55#define ONFI_PARAM_INFO_LENGTH 0x0200
56#define ONFI_PARAM_PAGE_LENGTH 0x0100
57
58#define ONFI_PARAMETER_PAGE_SIGNATURE 0x49464E4F
59
60#define FLASH_READ_ONFI_IDENTIFIER_COMMAND 0x90
61#define FLASH_READ_ONFI_IDENTIFIER_ADDRESS 0x20
62#define FLASH_READ_ONFI_PARAMETERS_COMMAND 0xEC
63#define FLASH_READ_ONFI_PARAMETERS_ADDRESS 0x00
64
65#define VERBOSE 0
66
67struct msm_nand_chip {
68 struct device *dev;
69 wait_queue_head_t wait_queue;
70 atomic_t dma_buffer_busy;
71 unsigned dma_channel;
72 uint8_t *dma_buffer;
73 dma_addr_t dma_addr;
74 unsigned CFG0, CFG1, CFG0_RAW, CFG1_RAW;
75 uint32_t ecc_buf_cfg;
76 uint32_t ecc_bch_cfg;
77 uint32_t ecc_parity_bytes;
78 unsigned cw_size;
79};
80
81#define CFG1_WIDE_FLASH (1U << 1)
82
83/* TODO: move datamover code out */
84
85#define SRC_CRCI_NAND_CMD CMD_SRC_CRCI(DMOV_NAND_CRCI_CMD)
86#define DST_CRCI_NAND_CMD CMD_DST_CRCI(DMOV_NAND_CRCI_CMD)
87#define SRC_CRCI_NAND_DATA CMD_SRC_CRCI(DMOV_NAND_CRCI_DATA)
88#define DST_CRCI_NAND_DATA CMD_DST_CRCI(DMOV_NAND_CRCI_DATA)
89
90#define msm_virt_to_dma(chip, vaddr) \
91 ((chip)->dma_addr + \
92 ((uint8_t *)(vaddr) - (chip)->dma_buffer))
93
94/**
95 * msm_nand_oob_64 - oob info for 2KB page
96 */
97static struct nand_ecclayout msm_nand_oob_64 = {
98 .eccbytes = 40,
99 .eccpos = {
100 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
101 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
102 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
103 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
104 },
105 .oobavail = 16,
106 .oobfree = {
107 {30, 16},
108 }
109};
110
111/**
112 * msm_nand_oob_128 - oob info for 4KB page
113 */
114static struct nand_ecclayout msm_nand_oob_128 = {
115 .eccbytes = 80,
116 .eccpos = {
117 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
118 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
119 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
120 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
121 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
122 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
123 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
124 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
125 },
126 .oobavail = 32,
127 .oobfree = {
128 {70, 32},
129 }
130};
131
132/**
133 * msm_nand_oob_224 - oob info for 4KB page 8Bit interface
134 */
135static struct nand_ecclayout msm_nand_oob_224_x8 = {
136 .eccbytes = 104,
137 .eccpos = {
138 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
139 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
140 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
141 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
142 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
143 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
144 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
145 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
146 },
147 .oobavail = 32,
148 .oobfree = {
149 {91, 32},
150 }
151};
152
153/**
154 * msm_nand_oob_224 - oob info for 4KB page 16Bit interface
155 */
156static struct nand_ecclayout msm_nand_oob_224_x16 = {
157 .eccbytes = 112,
158 .eccpos = {
159 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
160 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
161 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
162 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
163 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
164 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
165 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
166 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
167 },
168 .oobavail = 32,
169 .oobfree = {
170 {98, 32},
171 }
172};
173
174/**
175 * msm_nand_oob_256 - oob info for 8KB page
176 */
177static struct nand_ecclayout msm_nand_oob_256 = {
178 .eccbytes = 160,
179 .eccpos = {
180 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
181 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
182 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
183 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
184 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
185 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
186 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
187 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
188 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
189 90, 91, 92, 93, 94, 96, 97, 98 , 99, 100,
190 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
191 111, 112, 113, 114, 115, 116, 117, 118, 119, 120,
192 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,
193 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,
194 141, 142, 143, 144, 145, 146, 147, 148, 149, 150,
195 215, 216, 217, 218, 219, 220, 221, 222, 223, 224,
196 },
197 .oobavail = 64,
198 .oobfree = {
199 {151, 64},
200 }
201};
202
203/**
204 * msm_onenand_oob_64 - oob info for large (2KB) page
205 */
206static struct nand_ecclayout msm_onenand_oob_64 = {
207 .eccbytes = 20,
208 .eccpos = {
209 8, 9, 10, 11, 12,
210 24, 25, 26, 27, 28,
211 40, 41, 42, 43, 44,
212 56, 57, 58, 59, 60,
213 },
214 .oobavail = 20,
215 .oobfree = {
216 {2, 3}, {14, 2}, {18, 3}, {30, 2},
217 {34, 3}, {46, 2}, {50, 3}, {62, 2}
218 }
219};
220
221static void *msm_nand_get_dma_buffer(struct msm_nand_chip *chip, size_t size)
222{
223 unsigned int bitmask, free_bitmask, old_bitmask;
224 unsigned int need_mask, current_need_mask;
225 int free_index;
226
227 need_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
228 bitmask = atomic_read(&chip->dma_buffer_busy);
229 free_bitmask = ~bitmask;
230 do {
231 free_index = __ffs(free_bitmask);
232 current_need_mask = need_mask << free_index;
233
234 if (size + free_index * MSM_NAND_DMA_BUFFER_SLOTS >=
235 MSM_NAND_DMA_BUFFER_SIZE)
236 return NULL;
237
238 if ((bitmask & current_need_mask) == 0) {
239 old_bitmask =
240 atomic_cmpxchg(&chip->dma_buffer_busy,
241 bitmask,
242 bitmask | current_need_mask);
243 if (old_bitmask == bitmask)
244 return chip->dma_buffer +
245 free_index * MSM_NAND_DMA_BUFFER_SLOTS;
246 free_bitmask = 0; /* force return */
247 }
248 /* current free range was too small, clear all free bits */
249 /* below the top busy bit within current_need_mask */
250 free_bitmask &=
251 ~(~0U >> (32 - fls(bitmask & current_need_mask)));
252 } while (free_bitmask);
253
254 return NULL;
255}
256
257static void msm_nand_release_dma_buffer(struct msm_nand_chip *chip,
258 void *buffer, size_t size)
259{
260 int index;
261 unsigned int used_mask;
262
263 used_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
264 index = ((uint8_t *)buffer - chip->dma_buffer) /
265 MSM_NAND_DMA_BUFFER_SLOTS;
266 atomic_sub(used_mask << index, &chip->dma_buffer_busy);
267
268 wake_up(&chip->wait_queue);
269}
270
271
272unsigned flash_rd_reg(struct msm_nand_chip *chip, unsigned addr)
273{
274 struct {
275 dmov_s cmd;
276 unsigned cmdptr;
277 unsigned data;
278 } *dma_buffer;
279 unsigned rv;
280
281 wait_event(chip->wait_queue,
282 (dma_buffer = msm_nand_get_dma_buffer(
283 chip, sizeof(*dma_buffer))));
284
285 dma_buffer->cmd.cmd = CMD_LC | CMD_OCB | CMD_OCU;
286 dma_buffer->cmd.src = addr;
287 dma_buffer->cmd.dst = msm_virt_to_dma(chip, &dma_buffer->data);
288 dma_buffer->cmd.len = 4;
289
290 dma_buffer->cmdptr =
291 (msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
292 dma_buffer->data = 0xeeeeeeee;
293
294 mb();
295 msm_dmov_exec_cmd(
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]296 chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]297 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
298 mb();
299
300 rv = dma_buffer->data;
301
302 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
303
304 return rv;
305}
306
307void flash_wr_reg(struct msm_nand_chip *chip, unsigned addr, unsigned val)
308{
309 struct {
310 dmov_s cmd;
311 unsigned cmdptr;
312 unsigned data;
313 } *dma_buffer;
314
315 wait_event(chip->wait_queue,
316 (dma_buffer = msm_nand_get_dma_buffer(
317 chip, sizeof(*dma_buffer))));
318
319 dma_buffer->cmd.cmd = CMD_LC | CMD_OCB | CMD_OCU;
320 dma_buffer->cmd.src = msm_virt_to_dma(chip, &dma_buffer->data);
321 dma_buffer->cmd.dst = addr;
322 dma_buffer->cmd.len = 4;
323
324 dma_buffer->cmdptr =
325 (msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
326 dma_buffer->data = val;
327
328 mb();
329 msm_dmov_exec_cmd(
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]330 chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]331 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
332 mb();
333
334 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
335}
336
337static dma_addr_t
338msm_nand_dma_map(struct device *dev, void *addr, size_t size,
339 enum dma_data_direction dir)
340{
341 struct page *page;
342 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
343 if (virt_addr_valid(addr))
344 page = virt_to_page(addr);
345 else {
346 if (WARN_ON(size + offset > PAGE_SIZE))
347 return ~0;
348 page = vmalloc_to_page(addr);
349 }
350 return dma_map_page(dev, page, offset, size, dir);
351}
352
353uint32_t flash_read_id(struct msm_nand_chip *chip)
354{
355 struct {
356 dmov_s cmd[7];
357 unsigned cmdptr;
358 unsigned data[7];
359 } *dma_buffer;
360 uint32_t rv;
361
362 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
363 (chip, sizeof(*dma_buffer))));
364
365 dma_buffer->data[0] = 0 | 4;
366 dma_buffer->data[1] = MSM_NAND_CMD_FETCH_ID;
367 dma_buffer->data[2] = 1;
368 dma_buffer->data[3] = 0xeeeeeeee;
369 dma_buffer->data[4] = 0xeeeeeeee;
370 dma_buffer->data[5] = flash_rd_reg(chip, MSM_NAND_SFLASHC_BURST_CFG);
371 dma_buffer->data[6] = 0x00000000;
372 BUILD_BUG_ON(6 != ARRAY_SIZE(dma_buffer->data) - 1);
373
374 dma_buffer->cmd[0].cmd = 0 | CMD_OCB;
375 dma_buffer->cmd[0].src = msm_virt_to_dma(chip, &dma_buffer->data[6]);
376 dma_buffer->cmd[0].dst = MSM_NAND_SFLASHC_BURST_CFG;
377 dma_buffer->cmd[0].len = 4;
378
379 dma_buffer->cmd[1].cmd = 0;
380 dma_buffer->cmd[1].src = msm_virt_to_dma(chip, &dma_buffer->data[0]);
381 dma_buffer->cmd[1].dst = MSM_NAND_FLASH_CHIP_SELECT;
382 dma_buffer->cmd[1].len = 4;
383
384 dma_buffer->cmd[2].cmd = DST_CRCI_NAND_CMD;
385 dma_buffer->cmd[2].src = msm_virt_to_dma(chip, &dma_buffer->data[1]);
386 dma_buffer->cmd[2].dst = MSM_NAND_FLASH_CMD;
387 dma_buffer->cmd[2].len = 4;
388
389 dma_buffer->cmd[3].cmd = 0;
390 dma_buffer->cmd[3].src = msm_virt_to_dma(chip, &dma_buffer->data[2]);
391 dma_buffer->cmd[3].dst = MSM_NAND_EXEC_CMD;
392 dma_buffer->cmd[3].len = 4;
393
394 dma_buffer->cmd[4].cmd = SRC_CRCI_NAND_DATA;
395 dma_buffer->cmd[4].src = MSM_NAND_FLASH_STATUS;
396 dma_buffer->cmd[4].dst = msm_virt_to_dma(chip, &dma_buffer->data[3]);
397 dma_buffer->cmd[4].len = 4;
398
399 dma_buffer->cmd[5].cmd = 0;
400 dma_buffer->cmd[5].src = MSM_NAND_READ_ID;
401 dma_buffer->cmd[5].dst = msm_virt_to_dma(chip, &dma_buffer->data[4]);
402 dma_buffer->cmd[5].len = 4;
403
404 dma_buffer->cmd[6].cmd = CMD_OCU | CMD_LC;
405 dma_buffer->cmd[6].src = msm_virt_to_dma(chip, &dma_buffer->data[5]);
406 dma_buffer->cmd[6].dst = MSM_NAND_SFLASHC_BURST_CFG;
407 dma_buffer->cmd[6].len = 4;
408
409 BUILD_BUG_ON(6 != ARRAY_SIZE(dma_buffer->cmd) - 1);
410
411 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3
412 ) | CMD_PTR_LP;
413
414 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]415 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]416 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
417 mb();
418
419 pr_info("status: %x\n", dma_buffer->data[3]);
420 pr_info("nandid: %x maker %02x device %02x\n",
421 dma_buffer->data[4], dma_buffer->data[4] & 0xff,
422 (dma_buffer->data[4] >> 8) & 0xff);
423 rv = dma_buffer->data[4];
424 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
425 return rv;
426}
427
428struct flash_identification {
429 uint32_t flash_id;
430 uint32_t density;
431 uint32_t widebus;
432 uint32_t pagesize;
433 uint32_t blksize;
434 uint32_t oobsize;
435 uint32_t ecc_correctability;
436} supported_flash;
437
438uint16_t flash_onfi_crc_check(uint8_t *buffer, uint16_t count)
439{
440 int i;
441 uint16_t result;
442
443 for (i = 0; i < count; i++)
444 buffer[i] = bitrev8(buffer[i]);
445
446 result = bitrev16(crc16(bitrev16(0x4f4e), buffer, count));
447
448 for (i = 0; i < count; i++)
449 buffer[i] = bitrev8(buffer[i]);
450
451 return result;
452}
453
454
455uint32_t flash_onfi_probe(struct msm_nand_chip *chip)
456{
457 struct onfi_param_page {
458 uint32_t parameter_page_signature;
459 uint16_t revision_number;
460 uint16_t features_supported;
461 uint16_t optional_commands_supported;
462 uint8_t reserved0[22];
463 uint8_t device_manufacturer[12];
464 uint8_t device_model[20];
465 uint8_t jedec_manufacturer_id;
466 uint16_t date_code;
467 uint8_t reserved1[13];
468 uint32_t number_of_data_bytes_per_page;
469 uint16_t number_of_spare_bytes_per_page;
470 uint32_t number_of_data_bytes_per_partial_page;
471 uint16_t number_of_spare_bytes_per_partial_page;
472 uint32_t number_of_pages_per_block;
473 uint32_t number_of_blocks_per_logical_unit;
474 uint8_t number_of_logical_units;
475 uint8_t number_of_address_cycles;
476 uint8_t number_of_bits_per_cell;
477 uint16_t maximum_bad_blocks_per_logical_unit;
478 uint16_t block_endurance;
479 uint8_t guaranteed_valid_begin_blocks;
480 uint16_t guaranteed_valid_begin_blocks_endurance;
481 uint8_t number_of_programs_per_page;
482 uint8_t partial_program_attributes;
483 uint8_t number_of_bits_ecc_correctability;
484 uint8_t number_of_interleaved_address_bits;
485 uint8_t interleaved_operation_attributes;
486 uint8_t reserved2[13];
487 uint8_t io_pin_capacitance;
488 uint16_t timing_mode_support;
489 uint16_t program_cache_timing_mode_support;
490 uint16_t maximum_page_programming_time;
491 uint16_t maximum_block_erase_time;
492 uint16_t maximum_page_read_time;
493 uint16_t maximum_change_column_setup_time;
494 uint8_t reserved3[23];
495 uint16_t vendor_specific_revision_number;
496 uint8_t vendor_specific[88];
497 uint16_t integrity_crc;
498
499 } __attribute__((__packed__));
500
501 struct onfi_param_page *onfi_param_page_ptr;
502 uint8_t *onfi_identifier_buf = NULL;
503 uint8_t *onfi_param_info_buf = NULL;
504
505 struct {
506 dmov_s cmd[11];
507 unsigned cmdptr;
508 struct {
509 uint32_t cmd;
510 uint32_t addr0;
511 uint32_t addr1;
512 uint32_t cfg0;
513 uint32_t cfg1;
514 uint32_t exec;
515 uint32_t flash_status;
516 uint32_t devcmd1_orig;
517 uint32_t devcmdvld_orig;
518 uint32_t devcmd1_mod;
519 uint32_t devcmdvld_mod;
520 uint32_t sflash_bcfg_orig;
521 uint32_t sflash_bcfg_mod;
522 } data;
523 } *dma_buffer;
524 dmov_s *cmd;
525
526 unsigned page_address = 0;
527 int err = 0;
528 dma_addr_t dma_addr_param_info = 0;
529 dma_addr_t dma_addr_identifier = 0;
530 unsigned cmd_set_count = 2;
531 unsigned crc_chk_count = 0;
532
533 if (msm_nand_data.nr_parts) {
534 page_address = ((msm_nand_data.parts[0]).offset << 6);
535 } else {
536 pr_err("flash_onfi_probe: "
537 "No partition info available\n");
538 err = -EIO;
539 return err;
540 }
541
542 wait_event(chip->wait_queue, (onfi_identifier_buf =
543 msm_nand_get_dma_buffer(chip, ONFI_IDENTIFIER_LENGTH)));
544 dma_addr_identifier = msm_virt_to_dma(chip, onfi_identifier_buf);
545
546 wait_event(chip->wait_queue, (onfi_param_info_buf =
547 msm_nand_get_dma_buffer(chip, ONFI_PARAM_INFO_LENGTH)));
548 dma_addr_param_info = msm_virt_to_dma(chip, onfi_param_info_buf);
549
550 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
551 (chip, sizeof(*dma_buffer))));
552
553 dma_buffer->data.sflash_bcfg_orig = flash_rd_reg
554 (chip, MSM_NAND_SFLASHC_BURST_CFG);
555 dma_buffer->data.devcmd1_orig = flash_rd_reg(chip, MSM_NAND_DEV_CMD1);
556 dma_buffer->data.devcmdvld_orig = flash_rd_reg(chip,
557 MSM_NAND_DEV_CMD_VLD);
558
559 while (cmd_set_count-- > 0) {
560 cmd = dma_buffer->cmd;
561
562 dma_buffer->data.devcmd1_mod = (dma_buffer->data.devcmd1_orig &
563 0xFFFFFF00) | (cmd_set_count
564 ? FLASH_READ_ONFI_IDENTIFIER_COMMAND
565 : FLASH_READ_ONFI_PARAMETERS_COMMAND);
566 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
567 dma_buffer->data.addr0 = (page_address << 16) | (cmd_set_count
568 ? FLASH_READ_ONFI_IDENTIFIER_ADDRESS
569 : FLASH_READ_ONFI_PARAMETERS_ADDRESS);
570 dma_buffer->data.addr1 = (page_address >> 16) & 0xFF;
571 dma_buffer->data.cfg0 = (cmd_set_count
572 ? MSM_NAND_CFG0_RAW_ONFI_IDENTIFIER
573 : MSM_NAND_CFG0_RAW_ONFI_PARAM_INFO);
574 dma_buffer->data.cfg1 = (cmd_set_count
575 ? MSM_NAND_CFG1_RAW_ONFI_IDENTIFIER
576 : MSM_NAND_CFG1_RAW_ONFI_PARAM_INFO);
577 dma_buffer->data.sflash_bcfg_mod = 0x00000000;
578 dma_buffer->data.devcmdvld_mod = (dma_buffer->
579 data.devcmdvld_orig & 0xFFFFFFFE);
580 dma_buffer->data.exec = 1;
581 dma_buffer->data.flash_status = 0xeeeeeeee;
582
583 /* Put the Nand ctlr in Async mode and disable SFlash ctlr */
584 cmd->cmd = 0;
585 cmd->src = msm_virt_to_dma(chip,
586 &dma_buffer->data.sflash_bcfg_mod);
587 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
588 cmd->len = 4;
589 cmd++;
590
591 /* Block on cmd ready, & write CMD,ADDR0,ADDR1,CHIPSEL regs */
592 cmd->cmd = DST_CRCI_NAND_CMD;
593 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
594 cmd->dst = MSM_NAND_FLASH_CMD;
595 cmd->len = 12;
596 cmd++;
597
598 /* Configure the CFG0 and CFG1 registers */
599 cmd->cmd = 0;
600 cmd->src = msm_virt_to_dma(chip,
601 &dma_buffer->data.cfg0);
602 cmd->dst = MSM_NAND_DEV0_CFG0;
603 cmd->len = 8;
604 cmd++;
605
606 /* Configure the DEV_CMD_VLD register */
607 cmd->cmd = 0;
608 cmd->src = msm_virt_to_dma(chip,
609 &dma_buffer->data.devcmdvld_mod);
610 cmd->dst = MSM_NAND_DEV_CMD_VLD;
611 cmd->len = 4;
612 cmd++;
613
614 /* Configure the DEV_CMD1 register */
615 cmd->cmd = 0;
616 cmd->src = msm_virt_to_dma(chip,
617 &dma_buffer->data.devcmd1_mod);
618 cmd->dst = MSM_NAND_DEV_CMD1;
619 cmd->len = 4;
620 cmd++;
621
622 /* Kick the execute command */
623 cmd->cmd = 0;
624 cmd->src = msm_virt_to_dma(chip,
625 &dma_buffer->data.exec);
626 cmd->dst = MSM_NAND_EXEC_CMD;
627 cmd->len = 4;
628 cmd++;
629
630 /* Block on data ready, and read the two status registers */
631 cmd->cmd = SRC_CRCI_NAND_DATA;
632 cmd->src = MSM_NAND_FLASH_STATUS;
633 cmd->dst = msm_virt_to_dma(chip,
634 &dma_buffer->data.flash_status);
635 cmd->len = 4;
636 cmd++;
637
638 /* Read data block - valid only if status says success */
639 cmd->cmd = 0;
640 cmd->src = MSM_NAND_FLASH_BUFFER;
641 cmd->dst = (cmd_set_count ? dma_addr_identifier :
642 dma_addr_param_info);
643 cmd->len = (cmd_set_count ? ONFI_IDENTIFIER_LENGTH :
644 ONFI_PARAM_INFO_LENGTH);
645 cmd++;
646
647 /* Restore the DEV_CMD1 register */
648 cmd->cmd = 0 ;
649 cmd->src = msm_virt_to_dma(chip,
650 &dma_buffer->data.devcmd1_orig);
651 cmd->dst = MSM_NAND_DEV_CMD1;
652 cmd->len = 4;
653 cmd++;
654
655 /* Restore the DEV_CMD_VLD register */
656 cmd->cmd = 0;
657 cmd->src = msm_virt_to_dma(chip,
658 &dma_buffer->data.devcmdvld_orig);
659 cmd->dst = MSM_NAND_DEV_CMD_VLD;
660 cmd->len = 4;
661 cmd++;
662
663 /* Restore the SFLASH_BURST_CONFIG register */
664 cmd->cmd = 0;
665 cmd->src = msm_virt_to_dma(chip,
666 &dma_buffer->data.sflash_bcfg_orig);
667 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
668 cmd->len = 4;
669 cmd++;
670
671 BUILD_BUG_ON(11 != ARRAY_SIZE(dma_buffer->cmd));
672 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
673 dma_buffer->cmd[0].cmd |= CMD_OCB;
674 cmd[-1].cmd |= CMD_OCU | CMD_LC;
675
676 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
677 >> 3) | CMD_PTR_LP;
678
679 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]680 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]681 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
682 &dma_buffer->cmdptr)));
683 mb();
684
685 /* Check for errors, protection violations etc */
686 if (dma_buffer->data.flash_status & 0x110) {
687 pr_info("MPU/OP error (0x%x) during "
688 "ONFI probe\n",
689 dma_buffer->data.flash_status);
690 err = -EIO;
691 break;
692 }
693
694 if (cmd_set_count) {
695 onfi_param_page_ptr = (struct onfi_param_page *)
696 (&(onfi_identifier_buf[0]));
697 if (onfi_param_page_ptr->parameter_page_signature !=
698 ONFI_PARAMETER_PAGE_SIGNATURE) {
699 pr_info("ONFI probe : Found a non"
700 "ONFI Compliant device \n");
701 err = -EIO;
702 break;
703 }
704 } else {
705 for (crc_chk_count = 0; crc_chk_count <
706 ONFI_PARAM_INFO_LENGTH
707 / ONFI_PARAM_PAGE_LENGTH;
708 crc_chk_count++) {
709 onfi_param_page_ptr =
710 (struct onfi_param_page *)
711 (&(onfi_param_info_buf
712 [ONFI_PARAM_PAGE_LENGTH *
713 crc_chk_count]));
714 if (flash_onfi_crc_check(
715 (uint8_t *)onfi_param_page_ptr,
716 ONFI_PARAM_PAGE_LENGTH - 2) ==
717 onfi_param_page_ptr->integrity_crc) {
718 break;
719 }
720 }
721 if (crc_chk_count >= ONFI_PARAM_INFO_LENGTH
722 / ONFI_PARAM_PAGE_LENGTH) {
723 pr_info("ONFI probe : CRC Check "
724 "failed on ONFI Parameter "
725 "data \n");
726 err = -EIO;
727 break;
728 } else {
729 supported_flash.flash_id =
730 flash_read_id(chip);
731 supported_flash.widebus =
732 onfi_param_page_ptr->
733 features_supported & 0x01;
734 supported_flash.pagesize =
735 onfi_param_page_ptr->
736 number_of_data_bytes_per_page;
737 supported_flash.blksize =
738 onfi_param_page_ptr->
739 number_of_pages_per_block *
740 supported_flash.pagesize;
741 supported_flash.oobsize =
742 onfi_param_page_ptr->
743 number_of_spare_bytes_per_page;
744 supported_flash.density =
745 onfi_param_page_ptr->
746 number_of_blocks_per_logical_unit
747 * supported_flash.blksize;
748 supported_flash.ecc_correctability =
749 onfi_param_page_ptr->
750 number_of_bits_ecc_correctability;
751
752 pr_info("ONFI probe : Found an ONFI "
753 "compliant device %s\n",
754 onfi_param_page_ptr->device_model);
755
756 /* Temporary hack for MT29F4G08ABC device.
757 * Since the device is not properly adhering
758 * to ONFi specification it is reporting
759 * as 16 bit device though it is 8 bit device!!!
760 */
761 if (!strncmp(onfi_param_page_ptr->device_model,
762 "MT29F4G08ABC", 12))
763 supported_flash.widebus = 0;
764 }
765 }
766 }
767
768 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
769 msm_nand_release_dma_buffer(chip, onfi_param_info_buf,
770 ONFI_PARAM_INFO_LENGTH);
771 msm_nand_release_dma_buffer(chip, onfi_identifier_buf,
772 ONFI_IDENTIFIER_LENGTH);
773
774 return err;
775}
776
777static int msm_nand_read_oob(struct mtd_info *mtd, loff_t from,
778 struct mtd_oob_ops *ops)
779{
780 struct msm_nand_chip *chip = mtd->priv;
781
782 struct {
783 dmov_s cmd[8 * 5 + 2];
784 unsigned cmdptr;
785 struct {
786 uint32_t cmd;
787 uint32_t addr0;
788 uint32_t addr1;
789 uint32_t chipsel;
790 uint32_t cfg0;
791 uint32_t cfg1;
792 uint32_t eccbchcfg;
793 uint32_t exec;
794 uint32_t ecccfg;
795 struct {
796 uint32_t flash_status;
797 uint32_t buffer_status;
798 } result[8];
799 } data;
800 } *dma_buffer;
801 dmov_s *cmd;
802 unsigned n;
803 unsigned page = 0;
804 uint32_t oob_len;
805 uint32_t sectordatasize;
806 uint32_t sectoroobsize;
807 int err, pageerr, rawerr;
808 dma_addr_t data_dma_addr = 0;
809 dma_addr_t oob_dma_addr = 0;
810 dma_addr_t data_dma_addr_curr = 0;
811 dma_addr_t oob_dma_addr_curr = 0;
812 uint32_t oob_col = 0;
813 unsigned page_count;
814 unsigned pages_read = 0;
815 unsigned start_sector = 0;
816 uint32_t ecc_errors;
817 uint32_t total_ecc_errors = 0;
818 unsigned cwperpage;
819#if VERBOSE
820 pr_info("================================================="
821 "================\n");
822 pr_info("%s:\nfrom 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
823 "\noobbuf 0x%p ooblen 0x%x\n",
824 __func__, from, ops->mode, ops->datbuf, ops->len,
825 ops->oobbuf, ops->ooblen);
826#endif
827
828 if (mtd->writesize == 2048)
829 page = from >> 11;
830
831 if (mtd->writesize == 4096)
832 page = from >> 12;
833
834 oob_len = ops->ooblen;
835 cwperpage = (mtd->writesize >> 9);
836
837 if (from & (mtd->writesize - 1)) {
838 pr_err("%s: unsupported from, 0x%llx\n",
839 __func__, from);
840 return -EINVAL;
841 }
842 if (ops->mode != MTD_OOB_RAW) {
843 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
844 /* when ops->datbuf is NULL, ops->len can be ooblen */
845 pr_err("%s: unsupported ops->len, %d\n",
846 __func__, ops->len);
847 return -EINVAL;
848 }
849 } else {
850 if (ops->datbuf != NULL &&
851 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
852 pr_err("%s: unsupported ops->len,"
853 " %d for MTD_OOB_RAW\n", __func__, ops->len);
854 return -EINVAL;
855 }
856 }
857
858 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
859 pr_err("%s: unsupported ops->ooboffs, %d\n",
860 __func__, ops->ooboffs);
861 return -EINVAL;
862 }
863
864 if (ops->oobbuf && !ops->datbuf && ops->mode == MTD_OOB_AUTO)
865 start_sector = cwperpage - 1;
866
867 if (ops->oobbuf && !ops->datbuf) {
868 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
869 mtd->oobavail : mtd->oobsize);
870 if ((page_count == 0) && (ops->ooblen))
871 page_count = 1;
872 } else if (ops->mode != MTD_OOB_RAW)
873 page_count = ops->len / mtd->writesize;
874 else
875 page_count = ops->len / (mtd->writesize + mtd->oobsize);
876
877 if (ops->datbuf) {
878 data_dma_addr_curr = data_dma_addr =
879 msm_nand_dma_map(chip->dev, ops->datbuf, ops->len,
880 DMA_FROM_DEVICE);
881 if (dma_mapping_error(chip->dev, data_dma_addr)) {
882 pr_err("msm_nand_read_oob: failed to get dma addr "
883 "for %p\n", ops->datbuf);
884 return -EIO;
885 }
886 }
887 if (ops->oobbuf) {
888 memset(ops->oobbuf, 0xff, ops->ooblen);
889 oob_dma_addr_curr = oob_dma_addr =
890 msm_nand_dma_map(chip->dev, ops->oobbuf,
891 ops->ooblen, DMA_BIDIRECTIONAL);
892 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
893 pr_err("msm_nand_read_oob: failed to get dma addr "
894 "for %p\n", ops->oobbuf);
895 err = -EIO;
896 goto err_dma_map_oobbuf_failed;
897 }
898 }
899
900 wait_event(chip->wait_queue,
901 (dma_buffer = msm_nand_get_dma_buffer(
902 chip, sizeof(*dma_buffer))));
903
904 oob_col = start_sector * chip->cw_size;
905 if (chip->CFG1 & CFG1_WIDE_FLASH)
906 oob_col >>= 1;
907
908 err = 0;
909 while (page_count-- > 0) {
910 cmd = dma_buffer->cmd;
911
912 /* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
913 if (ops->mode != MTD_OOB_RAW) {
914 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ_ECC;
915 dma_buffer->data.cfg0 =
916 (chip->CFG0 & ~(7U << 6))
917 | (((cwperpage-1) - start_sector) << 6);
918 dma_buffer->data.cfg1 = chip->CFG1;
919 if (enable_bch_ecc)
920 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
921 } else {
922 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
923 dma_buffer->data.cfg0 = (chip->CFG0_RAW
924 & ~(7U << 6)) | ((cwperpage-1) << 6);
925 dma_buffer->data.cfg1 = chip->CFG1_RAW |
926 (chip->CFG1 & CFG1_WIDE_FLASH);
927 }
928
929 dma_buffer->data.addr0 = (page << 16) | oob_col;
930 dma_buffer->data.addr1 = (page >> 16) & 0xff;
931 /* chipsel_0 + enable DM interface */
932 dma_buffer->data.chipsel = 0 | 4;
933
934
935 /* GO bit for the EXEC register */
936 dma_buffer->data.exec = 1;
937
938
939 BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.result));
940
941 for (n = start_sector; n < cwperpage; n++) {
942 /* flash + buffer status return words */
943 dma_buffer->data.result[n].flash_status = 0xeeeeeeee;
944 dma_buffer->data.result[n].buffer_status = 0xeeeeeeee;
945
946 /* block on cmd ready, then
947 * write CMD / ADDR0 / ADDR1 / CHIPSEL
948 * regs in a burst
949 */
950 cmd->cmd = DST_CRCI_NAND_CMD;
951 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
952 cmd->dst = MSM_NAND_FLASH_CMD;
953 if (n == start_sector)
954 cmd->len = 16;
955 else
956 cmd->len = 4;
957 cmd++;
958
959 if (n == start_sector) {
960 cmd->cmd = 0;
961 cmd->src = msm_virt_to_dma(chip,
962 &dma_buffer->data.cfg0);
963 cmd->dst = MSM_NAND_DEV0_CFG0;
964 if (enable_bch_ecc)
965 cmd->len = 12;
966 else
967 cmd->len = 8;
968 cmd++;
969
970 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
971 cmd->cmd = 0;
972 cmd->src = msm_virt_to_dma(chip,
973 &dma_buffer->data.ecccfg);
974 cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
975 cmd->len = 4;
976 cmd++;
977 }
978
979 /* kick the execute register */
980 cmd->cmd = 0;
981 cmd->src =
982 msm_virt_to_dma(chip, &dma_buffer->data.exec);
983 cmd->dst = MSM_NAND_EXEC_CMD;
984 cmd->len = 4;
985 cmd++;
986
987 /* block on data ready, then
988 * read the status register
989 */
990 cmd->cmd = SRC_CRCI_NAND_DATA;
991 cmd->src = MSM_NAND_FLASH_STATUS;
992 cmd->dst = msm_virt_to_dma(chip,
993 &dma_buffer->data.result[n]);
994 /* MSM_NAND_FLASH_STATUS + MSM_NAND_BUFFER_STATUS */
995 cmd->len = 8;
996 cmd++;
997
998 /* read data block
999 * (only valid if status says success)
1000 */
1001 if (ops->datbuf) {
1002 if (ops->mode != MTD_OOB_RAW)
1003 sectordatasize = (n < (cwperpage - 1))
1004 ? 516 : (512 - ((cwperpage - 1) << 2));
1005 else
1006 sectordatasize = chip->cw_size;
1007
1008 cmd->cmd = 0;
1009 cmd->src = MSM_NAND_FLASH_BUFFER;
1010 cmd->dst = data_dma_addr_curr;
1011 data_dma_addr_curr += sectordatasize;
1012 cmd->len = sectordatasize;
1013 cmd++;
1014 }
1015
1016 if (ops->oobbuf && (n == (cwperpage - 1)
1017 || ops->mode != MTD_OOB_AUTO)) {
1018 cmd->cmd = 0;
1019 if (n == (cwperpage - 1)) {
1020 cmd->src = MSM_NAND_FLASH_BUFFER +
1021 (512 - ((cwperpage - 1) << 2));
1022 sectoroobsize = (cwperpage << 2);
1023 if (ops->mode != MTD_OOB_AUTO)
1024 sectoroobsize +=
1025 chip->ecc_parity_bytes;
1026 } else {
1027 cmd->src = MSM_NAND_FLASH_BUFFER + 516;
1028 sectoroobsize = chip->ecc_parity_bytes;
1029 }
1030
1031 cmd->dst = oob_dma_addr_curr;
1032 if (sectoroobsize < oob_len)
1033 cmd->len = sectoroobsize;
1034 else
1035 cmd->len = oob_len;
1036 oob_dma_addr_curr += cmd->len;
1037 oob_len -= cmd->len;
1038 if (cmd->len > 0)
1039 cmd++;
1040 }
1041 }
1042
1043 BUILD_BUG_ON(8 * 5 + 2 != ARRAY_SIZE(dma_buffer->cmd));
1044 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
1045 dma_buffer->cmd[0].cmd |= CMD_OCB;
1046 cmd[-1].cmd |= CMD_OCU | CMD_LC;
1047
1048 dma_buffer->cmdptr =
1049 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
1050 | CMD_PTR_LP;
1051
1052 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]1053 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1054 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
1055 &dma_buffer->cmdptr)));
1056 mb();
1057
1058 /* if any of the writes failed (0x10), or there
1059 * was a protection violation (0x100), we lose
1060 */
1061 pageerr = rawerr = 0;
1062 for (n = start_sector; n < cwperpage; n++) {
1063 if (dma_buffer->data.result[n].flash_status & 0x110) {
1064 rawerr = -EIO;
1065 break;
1066 }
1067 }
1068 if (rawerr) {
1069 if (ops->datbuf && ops->mode != MTD_OOB_RAW) {
1070 uint8_t *datbuf = ops->datbuf +
1071 pages_read * mtd->writesize;
1072
1073 dma_sync_single_for_cpu(chip->dev,
1074 data_dma_addr_curr-mtd->writesize,
1075 mtd->writesize, DMA_BIDIRECTIONAL);
1076
1077 for (n = 0; n < mtd->writesize; n++) {
1078 /* empty blocks read 0x54 at
1079 * these offsets
1080 */
1081 if ((n % 516 == 3 || n % 516 == 175)
1082 && datbuf[n] == 0x54)
1083 datbuf[n] = 0xff;
1084 if (datbuf[n] != 0xff) {
1085 pageerr = rawerr;
1086 break;
1087 }
1088 }
1089
1090 dma_sync_single_for_device(chip->dev,
1091 data_dma_addr_curr-mtd->writesize,
1092 mtd->writesize, DMA_BIDIRECTIONAL);
1093
1094 }
1095 if (ops->oobbuf) {
1096 dma_sync_single_for_cpu(chip->dev,
1097 oob_dma_addr_curr - (ops->ooblen - oob_len),
1098 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1099
1100 for (n = 0; n < ops->ooblen; n++) {
1101 if (ops->oobbuf[n] != 0xff) {
1102 pageerr = rawerr;
1103 break;
1104 }
1105 }
1106
1107 dma_sync_single_for_device(chip->dev,
1108 oob_dma_addr_curr - (ops->ooblen - oob_len),
1109 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1110 }
1111 }
1112 if (pageerr) {
1113 for (n = start_sector; n < cwperpage; n++) {
1114 if (enable_bch_ecc ?
1115 (dma_buffer->data.result[n].buffer_status & 0x10) :
1116 (dma_buffer->data.result[n].buffer_status & 0x8)) {
1117 /* not thread safe */
1118 mtd->ecc_stats.failed++;
1119 pageerr = -EBADMSG;
1120 break;
1121 }
1122 }
1123 }
1124 if (!rawerr) { /* check for corretable errors */
1125 for (n = start_sector; n < cwperpage; n++) {
1126 ecc_errors = enable_bch_ecc ?
1127 (dma_buffer->data.result[n].buffer_status & 0xF) :
1128 (dma_buffer->data.result[n].buffer_status & 0x7);
1129 if (ecc_errors) {
1130 total_ecc_errors += ecc_errors;
1131 /* not thread safe */
1132 mtd->ecc_stats.corrected += ecc_errors;
1133 if (ecc_errors > 1)
1134 pageerr = -EUCLEAN;
1135 }
1136 }
1137 }
1138 if (pageerr && (pageerr != -EUCLEAN || err == 0))
1139 err = pageerr;
1140
1141#if VERBOSE
1142 if (rawerr && !pageerr) {
1143 pr_err("msm_nand_read_oob %llx %x %x empty page\n",
1144 (loff_t)page * mtd->writesize, ops->len,
1145 ops->ooblen);
1146 } else {
1147 for (n = start_sector; n < cwperpage; n++)
1148 pr_info("flash_status[%d] = %x,\
1149 buffr_status[%d] = %x\n",
1150 n, dma_buffer->data.result[n].flash_status,
1151 n, dma_buffer->data.result[n].buffer_status);
1152 }
1153#endif
1154 if (err && err != -EUCLEAN && err != -EBADMSG)
1155 break;
1156 pages_read++;
1157 page++;
1158 }
1159 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
1160
1161 if (ops->oobbuf) {
1162 dma_unmap_page(chip->dev, oob_dma_addr,
1163 ops->ooblen, DMA_FROM_DEVICE);
1164 }
1165err_dma_map_oobbuf_failed:
1166 if (ops->datbuf) {
1167 dma_unmap_page(chip->dev, data_dma_addr,
1168 ops->len, DMA_BIDIRECTIONAL);
1169 }
1170
1171 if (ops->mode != MTD_OOB_RAW)
1172 ops->retlen = mtd->writesize * pages_read;
1173 else
1174 ops->retlen = (mtd->writesize + mtd->oobsize) *
1175 pages_read;
1176 ops->oobretlen = ops->ooblen - oob_len;
1177 if (err)
1178 pr_err("msm_nand_read_oob %llx %x %x failed %d, corrected %d\n",
1179 from, ops->datbuf ? ops->len : 0, ops->ooblen, err,
1180 total_ecc_errors);
1181#if VERBOSE
1182 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
1183 __func__, err, ops->retlen, ops->oobretlen);
1184
1185 pr_info("==================================================="
1186 "==============\n");
1187#endif
1188 return err;
1189}
1190
1191static int msm_nand_read_oob_dualnandc(struct mtd_info *mtd, loff_t from,
1192 struct mtd_oob_ops *ops)
1193{
1194 struct msm_nand_chip *chip = mtd->priv;
1195
1196 struct {
1197 dmov_s cmd[16 * 6 + 20];
1198 unsigned cmdptr;
1199 struct {
1200 uint32_t cmd;
1201 uint32_t nandc01_addr0;
1202 uint32_t nandc10_addr0;
1203 uint32_t nandc11_addr1;
1204 uint32_t chipsel_cs0;
1205 uint32_t chipsel_cs1;
1206 uint32_t cfg0;
1207 uint32_t cfg1;
1208 uint32_t eccbchcfg;
1209 uint32_t exec;
1210 uint32_t ecccfg;
1211 uint32_t ebi2_chip_select_cfg0;
1212 uint32_t adm_mux_data_ack_req_nc01;
1213 uint32_t adm_mux_cmd_ack_req_nc01;
1214 uint32_t adm_mux_data_ack_req_nc10;
1215 uint32_t adm_mux_cmd_ack_req_nc10;
1216 uint32_t adm_default_mux;
1217 uint32_t default_ebi2_chip_select_cfg0;
1218 uint32_t nc10_flash_dev_cmd_vld;
1219 uint32_t nc10_flash_dev_cmd1;
1220 uint32_t nc10_flash_dev_cmd_vld_default;
1221 uint32_t nc10_flash_dev_cmd1_default;
1222 struct {
1223 uint32_t flash_status;
1224 uint32_t buffer_status;
1225 } result[16];
1226 } data;
1227 } *dma_buffer;
1228 dmov_s *cmd;
1229 unsigned n;
1230 unsigned page = 0;
1231 uint32_t oob_len;
1232 uint32_t sectordatasize;
1233 uint32_t sectoroobsize;
1234 int err, pageerr, rawerr;
1235 dma_addr_t data_dma_addr = 0;
1236 dma_addr_t oob_dma_addr = 0;
1237 dma_addr_t data_dma_addr_curr = 0;
1238 dma_addr_t oob_dma_addr_curr = 0;
1239 uint32_t oob_col = 0;
1240 unsigned page_count;
1241 unsigned pages_read = 0;
1242 unsigned start_sector = 0;
1243 uint32_t ecc_errors;
1244 uint32_t total_ecc_errors = 0;
1245 unsigned cwperpage;
1246 unsigned cw_offset = chip->cw_size;
1247#if VERBOSE
1248 pr_info("================================================="
1249 "============\n");
1250 pr_info("%s:\nfrom 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
1251 "\noobbuf 0x%p ooblen 0x%x\n\n",
1252 __func__, from, ops->mode, ops->datbuf,
1253 ops->len, ops->oobbuf, ops->ooblen);
1254#endif
1255
1256 if (mtd->writesize == 2048)
1257 page = from >> 11;
1258
1259 if (mtd->writesize == 4096)
1260 page = from >> 12;
1261
1262 if (interleave_enable)
1263 page = (from >> 1) >> 12;
1264
1265 oob_len = ops->ooblen;
1266 cwperpage = (mtd->writesize >> 9);
1267
1268 if (from & (mtd->writesize - 1)) {
1269 pr_err("%s: unsupported from, 0x%llx\n",
1270 __func__, from);
1271 return -EINVAL;
1272 }
1273 if (ops->mode != MTD_OOB_RAW) {
1274 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
1275 pr_err("%s: unsupported ops->len, %d\n",
1276 __func__, ops->len);
1277 return -EINVAL;
1278 }
1279 } else {
1280 if (ops->datbuf != NULL &&
1281 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
1282 pr_err("%s: unsupported ops->len,"
1283 " %d for MTD_OOB_RAW\n", __func__, ops->len);
1284 return -EINVAL;
1285 }
1286 }
1287
1288 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
1289 pr_err("%s: unsupported ops->ooboffs, %d\n",
1290 __func__, ops->ooboffs);
1291 return -EINVAL;
1292 }
1293
1294 if (ops->oobbuf && !ops->datbuf && ops->mode == MTD_OOB_AUTO)
1295 start_sector = cwperpage - 1;
1296
1297 if (ops->oobbuf && !ops->datbuf) {
1298 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
1299 mtd->oobavail : mtd->oobsize);
1300 if ((page_count == 0) && (ops->ooblen))
1301 page_count = 1;
1302 } else if (ops->mode != MTD_OOB_RAW)
1303 page_count = ops->len / mtd->writesize;
1304 else
1305 page_count = ops->len / (mtd->writesize + mtd->oobsize);
1306
1307 if (ops->datbuf) {
1308 data_dma_addr_curr = data_dma_addr =
1309 msm_nand_dma_map(chip->dev, ops->datbuf, ops->len,
1310 DMA_FROM_DEVICE);
1311 if (dma_mapping_error(chip->dev, data_dma_addr)) {
1312 pr_err("msm_nand_read_oob_dualnandc: "
1313 "failed to get dma addr for %p\n",
1314 ops->datbuf);
1315 return -EIO;
1316 }
1317 }
1318 if (ops->oobbuf) {
1319 memset(ops->oobbuf, 0xff, ops->ooblen);
1320 oob_dma_addr_curr = oob_dma_addr =
1321 msm_nand_dma_map(chip->dev, ops->oobbuf,
1322 ops->ooblen, DMA_BIDIRECTIONAL);
1323 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
1324 pr_err("msm_nand_read_oob_dualnandc: "
1325 "failed to get dma addr for %p\n",
1326 ops->oobbuf);
1327 err = -EIO;
1328 goto err_dma_map_oobbuf_failed;
1329 }
1330 }
1331
1332 wait_event(chip->wait_queue,
1333 (dma_buffer = msm_nand_get_dma_buffer(
1334 chip, sizeof(*dma_buffer))));
1335
1336 oob_col = start_sector * chip->cw_size;
1337 if (chip->CFG1 & CFG1_WIDE_FLASH) {
1338 oob_col >>= 1;
1339 cw_offset >>= 1;
1340 }
1341
1342 err = 0;
1343 while (page_count-- > 0) {
1344 cmd = dma_buffer->cmd;
1345
1346 if (ops->mode != MTD_OOB_RAW) {
1347 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ_ECC;
1348 if (start_sector == (cwperpage - 1)) {
1349 dma_buffer->data.cfg0 = (chip->CFG0 &
1350 ~(7U << 6));
1351 } else {
1352 dma_buffer->data.cfg0 = (chip->CFG0 &
1353 ~(7U << 6))
1354 | (((cwperpage >> 1)-1) << 6);
1355 }
1356 dma_buffer->data.cfg1 = chip->CFG1;
1357 if (enable_bch_ecc)
1358 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
1359 } else {
1360 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
1361 dma_buffer->data.cfg0 = ((chip->CFG0_RAW &
1362 ~(7U << 6)) | ((((cwperpage >> 1)-1) << 6)));
1363 dma_buffer->data.cfg1 = chip->CFG1_RAW |
1364 (chip->CFG1 & CFG1_WIDE_FLASH);
1365 }
1366
1367 if (!interleave_enable) {
1368 if (start_sector == (cwperpage - 1)) {
1369 dma_buffer->data.nandc10_addr0 =
1370 (page << 16) | oob_col;
1371 dma_buffer->data.nc10_flash_dev_cmd_vld = 0xD;
1372 dma_buffer->data.nc10_flash_dev_cmd1 =
1373 0xF00F3000;
1374 } else {
1375 dma_buffer->data.nandc01_addr0 = page << 16;
1376 /* NC10 ADDR0 points to the next code word */
1377 dma_buffer->data.nandc10_addr0 = (page << 16) |
1378 cw_offset;
1379 dma_buffer->data.nc10_flash_dev_cmd_vld = 0x1D;
1380 dma_buffer->data.nc10_flash_dev_cmd1 =
1381 0xF00FE005;
1382 }
1383 } else {
1384 dma_buffer->data.nandc01_addr0 =
1385 dma_buffer->data.nandc10_addr0 =
1386 (page << 16) | oob_col;
1387 }
1388 /* ADDR1 */
1389 dma_buffer->data.nandc11_addr1 = (page >> 16) & 0xff;
1390
1391 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
1392 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
1393 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
1394 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
1395 dma_buffer->data.adm_default_mux = 0x00000FC0;
1396 dma_buffer->data.nc10_flash_dev_cmd_vld_default = 0x1D;
1397 dma_buffer->data.nc10_flash_dev_cmd1_default = 0xF00F3000;
1398
1399 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
1400 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
1401
1402 /* chipsel_0 + enable DM interface */
1403 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
1404 /* chipsel_1 + enable DM interface */
1405 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
1406
1407 /* GO bit for the EXEC register */
1408 dma_buffer->data.exec = 1;
1409
1410 BUILD_BUG_ON(16 != ARRAY_SIZE(dma_buffer->data.result));
1411
1412 for (n = start_sector; n < cwperpage; n++) {
1413 /* flash + buffer status return words */
1414 dma_buffer->data.result[n].flash_status = 0xeeeeeeee;
1415 dma_buffer->data.result[n].buffer_status = 0xeeeeeeee;
1416
1417 if (n == start_sector) {
1418 if (!interleave_enable) {
1419 cmd->cmd = 0;
1420 cmd->src = msm_virt_to_dma(chip,
1421 &dma_buffer->
1422 data.nc10_flash_dev_cmd_vld);
1423 cmd->dst = NC10(MSM_NAND_DEV_CMD_VLD);
1424 cmd->len = 4;
1425 cmd++;
1426
1427 cmd->cmd = 0;
1428 cmd->src = msm_virt_to_dma(chip,
1429 &dma_buffer->data.nc10_flash_dev_cmd1);
1430 cmd->dst = NC10(MSM_NAND_DEV_CMD1);
1431 cmd->len = 4;
1432 cmd++;
1433
1434 /* NC01, NC10 --> ADDR1 */
1435 cmd->cmd = 0;
1436 cmd->src = msm_virt_to_dma(chip,
1437 &dma_buffer->data.nandc11_addr1);
1438 cmd->dst = NC11(MSM_NAND_ADDR1);
1439 cmd->len = 8;
1440 cmd++;
1441
1442 cmd->cmd = 0;
1443 cmd->src = msm_virt_to_dma(chip,
1444 &dma_buffer->data.cfg0);
1445 cmd->dst = NC11(MSM_NAND_DEV0_CFG0);
1446 if (enable_bch_ecc)
1447 cmd->len = 12;
1448 else
1449 cmd->len = 8;
1450 cmd++;
1451 } else {
1452 /* enable CS0 & CS1 */
1453 cmd->cmd = 0;
1454 cmd->src = msm_virt_to_dma(chip,
1455 &dma_buffer->
1456 data.ebi2_chip_select_cfg0);
1457 cmd->dst = EBI2_CHIP_SELECT_CFG0;
1458 cmd->len = 4;
1459 cmd++;
1460
1461 /* NC01, NC10 --> ADDR1 */
1462 cmd->cmd = 0;
1463 cmd->src = msm_virt_to_dma(chip,
1464 &dma_buffer->data.nandc11_addr1);
1465 cmd->dst = NC11(MSM_NAND_ADDR1);
1466 cmd->len = 4;
1467 cmd++;
1468
1469 /* Enable CS0 for NC01 */
1470 cmd->cmd = 0;
1471 cmd->src = msm_virt_to_dma(chip,
1472 &dma_buffer->data.chipsel_cs0);
1473 cmd->dst =
1474 NC01(MSM_NAND_FLASH_CHIP_SELECT);
1475 cmd->len = 4;
1476 cmd++;
1477
1478 /* Enable CS1 for NC10 */
1479 cmd->cmd = 0;
1480 cmd->src = msm_virt_to_dma(chip,
1481 &dma_buffer->data.chipsel_cs1);
1482 cmd->dst =
1483 NC10(MSM_NAND_FLASH_CHIP_SELECT);
1484 cmd->len = 4;
1485 cmd++;
1486
1487 /* config DEV0_CFG0 & CFG1 for CS0 */
1488 cmd->cmd = 0;
1489 cmd->src = msm_virt_to_dma(chip,
1490 &dma_buffer->data.cfg0);
1491 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
1492 cmd->len = 8;
1493 cmd++;
1494
1495 /* config DEV1_CFG0 & CFG1 for CS1 */
1496 cmd->cmd = 0;
1497 cmd->src = msm_virt_to_dma(chip,
1498 &dma_buffer->data.cfg0);
1499 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
1500 cmd->len = 8;
1501 cmd++;
1502 }
1503
1504 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
1505 cmd->cmd = 0;
1506 cmd->src = msm_virt_to_dma(chip,
1507 &dma_buffer->data.ecccfg);
1508 cmd->dst = NC11(MSM_NAND_EBI2_ECC_BUF_CFG);
1509 cmd->len = 4;
1510 cmd++;
1511
1512 /* if 'only' the last code word */
1513 if (n == cwperpage - 1) {
1514 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
1515 cmd->cmd = 0;
1516 cmd->src = msm_virt_to_dma(chip,
1517 &dma_buffer->
1518 data.adm_mux_cmd_ack_req_nc01);
1519 cmd->dst = EBI2_NAND_ADM_MUX;
1520 cmd->len = 4;
1521 cmd++;
1522
1523 /* CMD */
1524 cmd->cmd = DST_CRCI_NAND_CMD;
1525 cmd->src = msm_virt_to_dma(chip,
1526 &dma_buffer->data.cmd);
1527 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
1528 cmd->len = 4;
1529 cmd++;
1530
1531 /* NC10 --> ADDR0 ( 0x0 ) */
1532 cmd->cmd = 0;
1533 cmd->src = msm_virt_to_dma(chip,
1534 &dma_buffer->data.nandc10_addr0);
1535 cmd->dst = NC10(MSM_NAND_ADDR0);
1536 cmd->len = 4;
1537 cmd++;
1538
1539 /* kick the execute reg for NC10 */
1540 cmd->cmd = 0;
1541 cmd->src = msm_virt_to_dma(chip,
1542 &dma_buffer->data.exec);
1543 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
1544 cmd->len = 4;
1545 cmd++;
1546
1547 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
1548 cmd->cmd = 0;
1549 cmd->src = msm_virt_to_dma(chip,
1550 &dma_buffer->
1551 data.adm_mux_data_ack_req_nc01);
1552 cmd->dst = EBI2_NAND_ADM_MUX;
1553 cmd->len = 4;
1554 cmd++;
1555
1556 /* block on data ready from NC10, then
1557 * read the status register
1558 */
1559 cmd->cmd = SRC_CRCI_NAND_DATA;
1560 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
1561 cmd->dst = msm_virt_to_dma(chip,
1562 &dma_buffer->data.result[n]);
1563 /* MSM_NAND_FLASH_STATUS +
1564 * MSM_NAND_BUFFER_STATUS
1565 */
1566 cmd->len = 8;
1567 cmd++;
1568 } else {
1569 /* NC01 --> ADDR0 */
1570 cmd->cmd = 0;
1571 cmd->src = msm_virt_to_dma(chip,
1572 &dma_buffer->data.nandc01_addr0);
1573 cmd->dst = NC01(MSM_NAND_ADDR0);
1574 cmd->len = 4;
1575 cmd++;
1576
1577 /* NC10 --> ADDR1 */
1578 cmd->cmd = 0;
1579 cmd->src = msm_virt_to_dma(chip,
1580 &dma_buffer->data.nandc10_addr0);
1581 cmd->dst = NC10(MSM_NAND_ADDR0);
1582 cmd->len = 4;
1583 cmd++;
1584
1585 /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
1586 cmd->cmd = 0;
1587 cmd->src = msm_virt_to_dma(chip,
1588 &dma_buffer->
1589 data.adm_mux_cmd_ack_req_nc10);
1590 cmd->dst = EBI2_NAND_ADM_MUX;
1591 cmd->len = 4;
1592 cmd++;
1593
1594 /* CMD */
1595 cmd->cmd = DST_CRCI_NAND_CMD;
1596 cmd->src = msm_virt_to_dma(chip,
1597 &dma_buffer->data.cmd);
1598 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
1599 cmd->len = 4;
1600 cmd++;
1601
1602 /* kick the execute register for NC01*/
1603 cmd->cmd = 0;
1604 cmd->src = msm_virt_to_dma(chip,
1605 &dma_buffer->data.exec);
1606 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
1607 cmd->len = 4;
1608 cmd++;
1609 }
1610 }
1611
1612 /* read data block
1613 * (only valid if status says success)
1614 */
1615 if (ops->datbuf || (ops->oobbuf &&
1616 ops->mode != MTD_OOB_AUTO)) {
1617 if (ops->mode != MTD_OOB_RAW)
1618 sectordatasize = (n < (cwperpage - 1))
1619 ? 516 : (512 - ((cwperpage - 1) << 2));
1620 else
1621 sectordatasize = chip->cw_size;
1622
1623 if (n % 2 == 0) {
1624 /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
1625 cmd->cmd = 0;
1626 cmd->src = msm_virt_to_dma(chip,
1627 &dma_buffer->
1628 data.adm_mux_data_ack_req_nc10);
1629 cmd->dst = EBI2_NAND_ADM_MUX;
1630 cmd->len = 4;
1631 cmd++;
1632
1633 /* block on data ready from NC01, then
1634 * read the status register
1635 */
1636 cmd->cmd = SRC_CRCI_NAND_DATA;
1637 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
1638 cmd->dst = msm_virt_to_dma(chip,
1639 &dma_buffer->data.result[n]);
1640 /* MSM_NAND_FLASH_STATUS +
1641 * MSM_NAND_BUFFER_STATUS
1642 */
1643 cmd->len = 8;
1644 cmd++;
1645
1646 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
1647 cmd->cmd = 0;
1648 cmd->src = msm_virt_to_dma(chip,
1649 &dma_buffer->
1650 data.adm_mux_cmd_ack_req_nc01);
1651 cmd->dst = EBI2_NAND_ADM_MUX;
1652 cmd->len = 4;
1653 cmd++;
1654
1655 /* CMD */
1656 cmd->cmd = DST_CRCI_NAND_CMD;
1657 cmd->src = msm_virt_to_dma(chip,
1658 &dma_buffer->data.cmd);
1659 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
1660 cmd->len = 4;
1661 cmd++;
1662
1663 /* kick the execute register for NC10 */
1664 cmd->cmd = 0;
1665 cmd->src = msm_virt_to_dma(chip,
1666 &dma_buffer->data.exec);
1667 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
1668 cmd->len = 4;
1669 cmd++;
1670
1671 /* Read only when there is data
1672 * buffer
1673 */
1674 if (ops->datbuf) {
1675 cmd->cmd = 0;
1676 cmd->src =
1677 NC01(MSM_NAND_FLASH_BUFFER);
1678 cmd->dst = data_dma_addr_curr;
1679 data_dma_addr_curr +=
1680 sectordatasize;
1681 cmd->len = sectordatasize;
1682 cmd++;
1683 }
1684 } else {
1685 /* MASK DATA ACK/REQ -->
1686 * NC01 (0xA3C)
1687 */
1688 cmd->cmd = 0;
1689 cmd->src = msm_virt_to_dma(chip,
1690 &dma_buffer->
1691 data.adm_mux_data_ack_req_nc01);
1692 cmd->dst = EBI2_NAND_ADM_MUX;
1693 cmd->len = 4;
1694 cmd++;
1695
1696 /* block on data ready from NC10
1697 * then read the status register
1698 */
1699 cmd->cmd = SRC_CRCI_NAND_DATA;
1700 cmd->src =
1701 NC10(MSM_NAND_FLASH_STATUS);
1702 cmd->dst = msm_virt_to_dma(chip,
1703 &dma_buffer->data.result[n]);
1704 /* MSM_NAND_FLASH_STATUS +
1705 * MSM_NAND_BUFFER_STATUS
1706 */
1707 cmd->len = 8;
1708 cmd++;
1709 if (n != cwperpage - 1) {
1710 /* MASK CMD ACK/REQ -->
1711 * NC10 (0xF14)
1712 */
1713 cmd->cmd = 0;
1714 cmd->src =
1715 msm_virt_to_dma(chip,
1716 &dma_buffer->
1717 data.adm_mux_cmd_ack_req_nc10);
1718 cmd->dst = EBI2_NAND_ADM_MUX;
1719 cmd->len = 4;
1720 cmd++;
1721
1722 /* CMD */
1723 cmd->cmd = DST_CRCI_NAND_CMD;
1724 cmd->src = msm_virt_to_dma(chip,
1725 &dma_buffer->data.cmd);
1726 cmd->dst =
1727 NC01(MSM_NAND_FLASH_CMD);
1728 cmd->len = 4;
1729 cmd++;
1730
1731 /* EXEC */
1732 cmd->cmd = 0;
1733 cmd->src = msm_virt_to_dma(chip,
1734 &dma_buffer->data.exec);
1735 cmd->dst =
1736 NC01(MSM_NAND_EXEC_CMD);
1737 cmd->len = 4;
1738 cmd++;
1739 }
1740
1741 /* Read only when there is data
1742 * buffer
1743 */
1744 if (ops->datbuf) {
1745 cmd->cmd = 0;
1746 cmd->src =
1747 NC10(MSM_NAND_FLASH_BUFFER);
1748 cmd->dst = data_dma_addr_curr;
1749 data_dma_addr_curr +=
1750 sectordatasize;
1751 cmd->len = sectordatasize;
1752 cmd++;
1753 }
1754 }
1755 }
1756
1757 if (ops->oobbuf && (n == (cwperpage - 1)
1758 || ops->mode != MTD_OOB_AUTO)) {
1759 cmd->cmd = 0;
1760 if (n == (cwperpage - 1)) {
1761 /* Use NC10 for reading the
1762 * last codeword!!!
1763 */
1764 cmd->src = NC10(MSM_NAND_FLASH_BUFFER) +
1765 (512 - ((cwperpage - 1) << 2));
1766 sectoroobsize = (cwperpage << 2);
1767 if (ops->mode != MTD_OOB_AUTO)
1768 sectoroobsize +=
1769 chip->ecc_parity_bytes;
1770 } else {
1771 if (n % 2 == 0)
1772 cmd->src =
1773 NC01(MSM_NAND_FLASH_BUFFER)
1774 + 516;
1775 else
1776 cmd->src =
1777 NC10(MSM_NAND_FLASH_BUFFER)
1778 + 516;
1779 sectoroobsize = chip->ecc_parity_bytes;
1780 }
1781 cmd->dst = oob_dma_addr_curr;
1782 if (sectoroobsize < oob_len)
1783 cmd->len = sectoroobsize;
1784 else
1785 cmd->len = oob_len;
1786 oob_dma_addr_curr += cmd->len;
1787 oob_len -= cmd->len;
1788 if (cmd->len > 0)
1789 cmd++;
1790 }
1791 }
1792 /* ADM --> Default mux state (0xFC0) */
1793 cmd->cmd = 0;
1794 cmd->src = msm_virt_to_dma(chip,
1795 &dma_buffer->data.adm_default_mux);
1796 cmd->dst = EBI2_NAND_ADM_MUX;
1797 cmd->len = 4;
1798 cmd++;
1799
1800 if (!interleave_enable) {
1801 cmd->cmd = 0;
1802 cmd->src = msm_virt_to_dma(chip,
1803 &dma_buffer->data.nc10_flash_dev_cmd_vld_default);
1804 cmd->dst = NC10(MSM_NAND_DEV_CMD_VLD);
1805 cmd->len = 4;
1806 cmd++;
1807
1808 cmd->cmd = 0;
1809 cmd->src = msm_virt_to_dma(chip,
1810 &dma_buffer->data.nc10_flash_dev_cmd1_default);
1811 cmd->dst = NC10(MSM_NAND_DEV_CMD1);
1812 cmd->len = 4;
1813 cmd++;
1814 } else {
1815 /* disable CS1 */
1816 cmd->cmd = 0;
1817 cmd->src = msm_virt_to_dma(chip,
1818 &dma_buffer->data.default_ebi2_chip_select_cfg0);
1819 cmd->dst = EBI2_CHIP_SELECT_CFG0;
1820 cmd->len = 4;
1821 cmd++;
1822 }
1823
1824 BUILD_BUG_ON(16 * 6 + 20 != ARRAY_SIZE(dma_buffer->cmd));
1825 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
1826 dma_buffer->cmd[0].cmd |= CMD_OCB;
1827 cmd[-1].cmd |= CMD_OCU | CMD_LC;
1828
1829 dma_buffer->cmdptr =
1830 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
1831 | CMD_PTR_LP;
1832
1833 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]1834 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1835 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
1836 &dma_buffer->cmdptr)));
1837 mb();
1838
1839 /* if any of the writes failed (0x10), or there
1840 * was a protection violation (0x100), we lose
1841 */
1842 pageerr = rawerr = 0;
1843 for (n = start_sector; n < cwperpage; n++) {
1844 if (dma_buffer->data.result[n].flash_status & 0x110) {
1845 rawerr = -EIO;
1846 break;
1847 }
1848 }
1849 if (rawerr) {
1850 if (ops->datbuf && ops->mode != MTD_OOB_RAW) {
1851 uint8_t *datbuf = ops->datbuf +
1852 pages_read * mtd->writesize;
1853
1854 dma_sync_single_for_cpu(chip->dev,
1855 data_dma_addr_curr-mtd->writesize,
1856 mtd->writesize, DMA_BIDIRECTIONAL);
1857
1858 for (n = 0; n < mtd->writesize; n++) {
1859 /* empty blocks read 0x54 at
1860 * these offsets
1861 */
1862 if ((n % 516 == 3 || n % 516 == 175)
1863 && datbuf[n] == 0x54)
1864 datbuf[n] = 0xff;
1865 if (datbuf[n] != 0xff) {
1866 pageerr = rawerr;
1867 break;
1868 }
1869 }
1870
1871 dma_sync_single_for_device(chip->dev,
1872 data_dma_addr_curr-mtd->writesize,
1873 mtd->writesize, DMA_BIDIRECTIONAL);
1874
1875 }
1876 if (ops->oobbuf) {
1877 dma_sync_single_for_cpu(chip->dev,
1878 oob_dma_addr_curr - (ops->ooblen - oob_len),
1879 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1880
1881 for (n = 0; n < ops->ooblen; n++) {
1882 if (ops->oobbuf[n] != 0xff) {
1883 pageerr = rawerr;
1884 break;
1885 }
1886 }
1887
1888 dma_sync_single_for_device(chip->dev,
1889 oob_dma_addr_curr - (ops->ooblen - oob_len),
1890 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1891 }
1892 }
1893 if (pageerr) {
1894 for (n = start_sector; n < cwperpage; n++) {
1895 if (dma_buffer->data.result[n].buffer_status
1896 & MSM_NAND_BUF_STAT_UNCRCTBL_ERR) {
1897 /* not thread safe */
1898 mtd->ecc_stats.failed++;
1899 pageerr = -EBADMSG;
1900 break;
1901 }
1902 }
1903 }
1904 if (!rawerr) { /* check for corretable errors */
1905 for (n = start_sector; n < cwperpage; n++) {
1906 ecc_errors = dma_buffer->data.
1907 result[n].buffer_status
1908 & MSM_NAND_BUF_STAT_NUM_ERR_MASK;
1909 if (ecc_errors) {
1910 total_ecc_errors += ecc_errors;
1911 /* not thread safe */
1912 mtd->ecc_stats.corrected += ecc_errors;
1913 if (ecc_errors > 1)
1914 pageerr = -EUCLEAN;
1915 }
1916 }
1917 }
1918 if (pageerr && (pageerr != -EUCLEAN || err == 0))
1919 err = pageerr;
1920
1921#if VERBOSE
1922 if (rawerr && !pageerr) {
1923 pr_err("msm_nand_read_oob_dualnandc "
1924 "%llx %x %x empty page\n",
1925 (loff_t)page * mtd->writesize, ops->len,
1926 ops->ooblen);
1927 } else {
1928 for (n = start_sector; n < cwperpage; n++) {
1929 if (n%2) {
1930 pr_info("NC10: flash_status[%d] = %x, "
1931 "buffr_status[%d] = %x\n",
1932 n, dma_buffer->
1933 data.result[n].flash_status,
1934 n, dma_buffer->
1935 data.result[n].buffer_status);
1936 } else {
1937 pr_info("NC01: flash_status[%d] = %x, "
1938 "buffr_status[%d] = %x\n",
1939 n, dma_buffer->
1940 data.result[n].flash_status,
1941 n, dma_buffer->
1942 data.result[n].buffer_status);
1943 }
1944 }
1945 }
1946#endif
1947 if (err && err != -EUCLEAN && err != -EBADMSG)
1948 break;
1949 pages_read++;
1950 page++;
1951 }
1952
1953 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
1954
1955 if (ops->oobbuf) {
1956 dma_unmap_page(chip->dev, oob_dma_addr,
1957 ops->ooblen, DMA_FROM_DEVICE);
1958 }
1959err_dma_map_oobbuf_failed:
1960 if (ops->datbuf) {
1961 dma_unmap_page(chip->dev, data_dma_addr,
1962 ops->len, DMA_BIDIRECTIONAL);
1963 }
1964
1965 if (ops->mode != MTD_OOB_RAW)
1966 ops->retlen = mtd->writesize * pages_read;
1967 else
1968 ops->retlen = (mtd->writesize + mtd->oobsize) *
1969 pages_read;
1970 ops->oobretlen = ops->ooblen - oob_len;
1971 if (err)
1972 pr_err("msm_nand_read_oob_dualnandc "
1973 "%llx %x %x failed %d, corrected %d\n",
1974 from, ops->datbuf ? ops->len : 0, ops->ooblen, err,
1975 total_ecc_errors);
1976#if VERBOSE
1977 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
1978 __func__, err, ops->retlen, ops->oobretlen);
1979
1980 pr_info("==================================================="
1981 "==========\n");
1982#endif
1983 return err;
1984}
1985
1986static int
1987msm_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1988 size_t *retlen, u_char *buf)
1989{
1990 int ret;
1991 struct mtd_oob_ops ops;
1992
1993 /* printk("msm_nand_read %llx %x\n", from, len); */
1994
1995 ops.mode = MTD_OOB_PLACE;
1996 ops.len = len;
1997 ops.retlen = 0;
1998 ops.ooblen = 0;
1999 ops.datbuf = buf;
2000 ops.oobbuf = NULL;
2001 if (!dual_nand_ctlr_present)
2002 ret = msm_nand_read_oob(mtd, from, &ops);
2003 else
2004 ret = msm_nand_read_oob_dualnandc(mtd, from, &ops);
2005 *retlen = ops.retlen;
2006 return ret;
2007}
2008
2009static int
2010msm_nand_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
2011{
2012 struct msm_nand_chip *chip = mtd->priv;
2013 struct {
2014 dmov_s cmd[8 * 7 + 2];
2015 unsigned cmdptr;
2016 struct {
2017 uint32_t cmd;
2018 uint32_t addr0;
2019 uint32_t addr1;
2020 uint32_t chipsel;
2021 uint32_t cfg0;
2022 uint32_t cfg1;
2023 uint32_t eccbchcfg;
2024 uint32_t exec;
2025 uint32_t ecccfg;
2026 uint32_t clrfstatus;
2027 uint32_t clrrstatus;
2028 uint32_t flash_status[8];
2029 } data;
2030 } *dma_buffer;
2031 dmov_s *cmd;
2032 unsigned n;
2033 unsigned page = 0;
2034 uint32_t oob_len;
2035 uint32_t sectordatawritesize;
2036 int err = 0;
2037 dma_addr_t data_dma_addr = 0;
2038 dma_addr_t oob_dma_addr = 0;
2039 dma_addr_t data_dma_addr_curr = 0;
2040 dma_addr_t oob_dma_addr_curr = 0;
2041 unsigned page_count;
2042 unsigned pages_written = 0;
2043 unsigned cwperpage;
2044#if VERBOSE
2045 pr_info("================================================="
2046 "================\n");
2047 pr_info("%s:\nto 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
2048 "\noobbuf 0x%p ooblen 0x%x\n",
2049 __func__, to, ops->mode, ops->datbuf, ops->len,
2050 ops->oobbuf, ops->ooblen);
2051#endif
2052
2053 if (mtd->writesize == 2048)
2054 page = to >> 11;
2055
2056 if (mtd->writesize == 4096)
2057 page = to >> 12;
2058
2059 oob_len = ops->ooblen;
2060 cwperpage = (mtd->writesize >> 9);
2061
2062 if (to & (mtd->writesize - 1)) {
2063 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
2064 return -EINVAL;
2065 }
2066
2067 if (ops->mode != MTD_OOB_RAW) {
2068 if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO) {
2069 pr_err("%s: unsupported ops->mode,%d\n",
2070 __func__, ops->mode);
2071 return -EINVAL;
2072 }
2073 if ((ops->len % mtd->writesize) != 0) {
2074 pr_err("%s: unsupported ops->len, %d\n",
2075 __func__, ops->len);
2076 return -EINVAL;
2077 }
2078 } else {
2079 if ((ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
2080 pr_err("%s: unsupported ops->len, "
2081 "%d for MTD_OOB_RAW mode\n",
2082 __func__, ops->len);
2083 return -EINVAL;
2084 }
2085 }
2086
2087 if (ops->datbuf == NULL) {
2088 pr_err("%s: unsupported ops->datbuf == NULL\n", __func__);
2089 return -EINVAL;
2090 }
2091 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
2092 pr_err("%s: unsupported ops->ooboffs, %d\n",
2093 __func__, ops->ooboffs);
2094 return -EINVAL;
2095 }
2096
2097 if (ops->datbuf) {
2098 data_dma_addr_curr = data_dma_addr =
2099 msm_nand_dma_map(chip->dev, ops->datbuf,
2100 ops->len, DMA_TO_DEVICE);
2101 if (dma_mapping_error(chip->dev, data_dma_addr)) {
2102 pr_err("msm_nand_write_oob: failed to get dma addr "
2103 "for %p\n", ops->datbuf);
2104 return -EIO;
2105 }
2106 }
2107 if (ops->oobbuf) {
2108 oob_dma_addr_curr = oob_dma_addr =
2109 msm_nand_dma_map(chip->dev, ops->oobbuf,
2110 ops->ooblen, DMA_TO_DEVICE);
2111 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
2112 pr_err("msm_nand_write_oob: failed to get dma addr "
2113 "for %p\n", ops->oobbuf);
2114 err = -EIO;
2115 goto err_dma_map_oobbuf_failed;
2116 }
2117 }
2118 if (ops->mode != MTD_OOB_RAW)
2119 page_count = ops->len / mtd->writesize;
2120 else
2121 page_count = ops->len / (mtd->writesize + mtd->oobsize);
2122
2123 wait_event(chip->wait_queue, (dma_buffer =
2124 msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
2125
2126 while (page_count-- > 0) {
2127 cmd = dma_buffer->cmd;
2128
2129 if (ops->mode != MTD_OOB_RAW) {
2130 dma_buffer->data.cfg0 = chip->CFG0;
2131 dma_buffer->data.cfg1 = chip->CFG1;
2132 if (enable_bch_ecc)
2133 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
2134 } else {
2135 dma_buffer->data.cfg0 = (chip->CFG0_RAW &
2136 ~(7U << 6)) | ((cwperpage-1) << 6);
2137 dma_buffer->data.cfg1 = chip->CFG1_RAW |
2138 (chip->CFG1 & CFG1_WIDE_FLASH);
2139 }
2140
2141 /* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
2142 dma_buffer->data.cmd = MSM_NAND_CMD_PRG_PAGE;
2143 dma_buffer->data.addr0 = page << 16;
2144 dma_buffer->data.addr1 = (page >> 16) & 0xff;
2145 /* chipsel_0 + enable DM interface */
2146 dma_buffer->data.chipsel = 0 | 4;
2147
2148
2149 /* GO bit for the EXEC register */
2150 dma_buffer->data.exec = 1;
2151 dma_buffer->data.clrfstatus = 0x00000020;
2152 dma_buffer->data.clrrstatus = 0x000000C0;
2153
2154 BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.flash_status));
2155
2156 for (n = 0; n < cwperpage ; n++) {
2157 /* status return words */
2158 dma_buffer->data.flash_status[n] = 0xeeeeeeee;
2159 /* block on cmd ready, then
2160 * write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst
2161 */
2162 cmd->cmd = DST_CRCI_NAND_CMD;
2163 cmd->src =
2164 msm_virt_to_dma(chip, &dma_buffer->data.cmd);
2165 cmd->dst = MSM_NAND_FLASH_CMD;
2166 if (n == 0)
2167 cmd->len = 16;
2168 else
2169 cmd->len = 4;
2170 cmd++;
2171
2172 if (n == 0) {
2173 cmd->cmd = 0;
2174 cmd->src = msm_virt_to_dma(chip,
2175 &dma_buffer->data.cfg0);
2176 cmd->dst = MSM_NAND_DEV0_CFG0;
2177 if (enable_bch_ecc)
2178 cmd->len = 12;
2179 else
2180 cmd->len = 8;
2181 cmd++;
2182
2183 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
2184 cmd->cmd = 0;
2185 cmd->src = msm_virt_to_dma(chip,
2186 &dma_buffer->data.ecccfg);
2187 cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
2188 cmd->len = 4;
2189 cmd++;
2190 }
2191
2192 /* write data block */
2193 if (ops->mode != MTD_OOB_RAW)
2194 sectordatawritesize = (n < (cwperpage - 1)) ?
2195 516 : (512 - ((cwperpage - 1) << 2));
2196 else
2197 sectordatawritesize = chip->cw_size;
2198
2199 cmd->cmd = 0;
2200 cmd->src = data_dma_addr_curr;
2201 data_dma_addr_curr += sectordatawritesize;
2202 cmd->dst = MSM_NAND_FLASH_BUFFER;
2203 cmd->len = sectordatawritesize;
2204 cmd++;
2205
2206 if (ops->oobbuf) {
2207 if (n == (cwperpage - 1)) {
2208 cmd->cmd = 0;
2209 cmd->src = oob_dma_addr_curr;
2210 cmd->dst = MSM_NAND_FLASH_BUFFER +
2211 (512 - ((cwperpage - 1) << 2));
2212 if ((cwperpage << 2) < oob_len)
2213 cmd->len = (cwperpage << 2);
2214 else
2215 cmd->len = oob_len;
2216 oob_dma_addr_curr += cmd->len;
2217 oob_len -= cmd->len;
2218 if (cmd->len > 0)
2219 cmd++;
2220 }
2221 if (ops->mode != MTD_OOB_AUTO) {
2222 /* skip ecc bytes in oobbuf */
2223 if (oob_len < chip->ecc_parity_bytes) {
2224 oob_dma_addr_curr +=
2225 chip->ecc_parity_bytes;
2226 oob_len -=
2227 chip->ecc_parity_bytes;
2228 } else {
2229 oob_dma_addr_curr += oob_len;
2230 oob_len = 0;
2231 }
2232 }
2233 }
2234
2235 /* kick the execute register */
2236 cmd->cmd = 0;
2237 cmd->src =
2238 msm_virt_to_dma(chip, &dma_buffer->data.exec);
2239 cmd->dst = MSM_NAND_EXEC_CMD;
2240 cmd->len = 4;
2241 cmd++;
2242
2243 /* block on data ready, then
2244 * read the status register
2245 */
2246 cmd->cmd = SRC_CRCI_NAND_DATA;
2247 cmd->src = MSM_NAND_FLASH_STATUS;
2248 cmd->dst = msm_virt_to_dma(chip,
2249 &dma_buffer->data.flash_status[n]);
2250 cmd->len = 4;
2251 cmd++;
2252
2253 cmd->cmd = 0;
2254 cmd->src = msm_virt_to_dma(chip,
2255 &dma_buffer->data.clrfstatus);
2256 cmd->dst = MSM_NAND_FLASH_STATUS;
2257 cmd->len = 4;
2258 cmd++;
2259
2260 cmd->cmd = 0;
2261 cmd->src = msm_virt_to_dma(chip,
2262 &dma_buffer->data.clrrstatus);
2263 cmd->dst = MSM_NAND_READ_STATUS;
2264 cmd->len = 4;
2265 cmd++;
2266
2267 }
2268
2269 dma_buffer->cmd[0].cmd |= CMD_OCB;
2270 cmd[-1].cmd |= CMD_OCU | CMD_LC;
2271 BUILD_BUG_ON(8 * 7 + 2 != ARRAY_SIZE(dma_buffer->cmd));
2272 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
2273 dma_buffer->cmdptr =
2274 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) |
2275 CMD_PTR_LP;
2276
2277 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]2278 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2279 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(
2280 msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
2281 mb();
2282
2283 /* if any of the writes failed (0x10), or there was a
2284 * protection violation (0x100), or the program success
2285 * bit (0x80) is unset, we lose
2286 */
2287 err = 0;
2288 for (n = 0; n < cwperpage; n++) {
2289 if (dma_buffer->data.flash_status[n] & 0x110) {
2290 err = -EIO;
2291 break;
2292 }
2293 if (!(dma_buffer->data.flash_status[n] & 0x80)) {
2294 err = -EIO;
2295 break;
2296 }
2297 }
2298
2299#if VERBOSE
2300 for (n = 0; n < cwperpage; n++)
2301 pr_info("write pg %d: flash_status[%d] = %x\n", page,
2302 n, dma_buffer->data.flash_status[n]);
2303
2304#endif
2305 if (err)
2306 break;
2307 pages_written++;
2308 page++;
2309 }
2310 if (ops->mode != MTD_OOB_RAW)
2311 ops->retlen = mtd->writesize * pages_written;
2312 else
2313 ops->retlen = (mtd->writesize + mtd->oobsize) * pages_written;
2314
2315 ops->oobretlen = ops->ooblen - oob_len;
2316
2317 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
2318
2319 if (ops->oobbuf)
2320 dma_unmap_page(chip->dev, oob_dma_addr,
2321 ops->ooblen, DMA_TO_DEVICE);
2322err_dma_map_oobbuf_failed:
2323 if (ops->datbuf)
2324 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
2325 DMA_TO_DEVICE);
2326 if (err)
2327 pr_err("msm_nand_write_oob %llx %x %x failed %d\n",
2328 to, ops->len, ops->ooblen, err);
2329
2330#if VERBOSE
2331 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
2332 __func__, err, ops->retlen, ops->oobretlen);
2333
2334 pr_info("==================================================="
2335 "==============\n");
2336#endif
2337 return err;
2338}
2339
2340static int
2341msm_nand_write_oob_dualnandc(struct mtd_info *mtd, loff_t to,
2342 struct mtd_oob_ops *ops)
2343{
2344 struct msm_nand_chip *chip = mtd->priv;
2345 struct {
2346 dmov_s cmd[16 * 6 + 18];
2347 unsigned cmdptr;
2348 struct {
2349 uint32_t cmd;
2350 uint32_t nandc01_addr0;
2351 uint32_t nandc10_addr0;
2352 uint32_t nandc11_addr1;
2353 uint32_t chipsel_cs0;
2354 uint32_t chipsel_cs1;
2355 uint32_t cfg0;
2356 uint32_t cfg1;
2357 uint32_t eccbchcfg;
2358 uint32_t exec;
2359 uint32_t ecccfg;
2360 uint32_t cfg0_nc01;
2361 uint32_t ebi2_chip_select_cfg0;
2362 uint32_t adm_mux_data_ack_req_nc01;
2363 uint32_t adm_mux_cmd_ack_req_nc01;
2364 uint32_t adm_mux_data_ack_req_nc10;
2365 uint32_t adm_mux_cmd_ack_req_nc10;
2366 uint32_t adm_default_mux;
2367 uint32_t default_ebi2_chip_select_cfg0;
2368 uint32_t nc01_flash_dev_cmd_vld;
2369 uint32_t nc10_flash_dev_cmd0;
2370 uint32_t nc01_flash_dev_cmd_vld_default;
2371 uint32_t nc10_flash_dev_cmd0_default;
2372 uint32_t flash_status[16];
2373 uint32_t clrfstatus;
2374 uint32_t clrrstatus;
2375 } data;
2376 } *dma_buffer;
2377 dmov_s *cmd;
2378 unsigned n;
2379 unsigned page = 0;
2380 uint32_t oob_len;
2381 uint32_t sectordatawritesize;
2382 int err = 0;
2383 dma_addr_t data_dma_addr = 0;
2384 dma_addr_t oob_dma_addr = 0;
2385 dma_addr_t data_dma_addr_curr = 0;
2386 dma_addr_t oob_dma_addr_curr = 0;
2387 unsigned page_count;
2388 unsigned pages_written = 0;
2389 unsigned cwperpage;
2390 unsigned cw_offset = chip->cw_size;
2391#if VERBOSE
2392 pr_info("================================================="
2393 "============\n");
2394 pr_info("%s:\nto 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
2395 "\noobbuf 0x%p ooblen 0x%x\n\n",
2396 __func__, to, ops->mode, ops->datbuf, ops->len,
2397 ops->oobbuf, ops->ooblen);
2398#endif
2399
2400 if (mtd->writesize == 2048)
2401 page = to >> 11;
2402
2403 if (mtd->writesize == 4096)
2404 page = to >> 12;
2405
2406 if (interleave_enable)
2407 page = (to >> 1) >> 12;
2408
2409 oob_len = ops->ooblen;
2410 cwperpage = (mtd->writesize >> 9);
2411
2412 if (to & (mtd->writesize - 1)) {
2413 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
2414 return -EINVAL;
2415 }
2416
2417 if (ops->mode != MTD_OOB_RAW) {
2418 if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO) {
2419 pr_err("%s: unsupported ops->mode,%d\n",
2420 __func__, ops->mode);
2421 return -EINVAL;
2422 }
2423 if ((ops->len % mtd->writesize) != 0) {
2424 pr_err("%s: unsupported ops->len, %d\n",
2425 __func__, ops->len);
2426 return -EINVAL;
2427 }
2428 } else {
2429 if ((ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
2430 pr_err("%s: unsupported ops->len, "
2431 "%d for MTD_OOB_RAW mode\n",
2432 __func__, ops->len);
2433 return -EINVAL;
2434 }
2435 }
2436
2437 if (ops->datbuf == NULL) {
2438 pr_err("%s: unsupported ops->datbuf == NULL\n", __func__);
2439 return -EINVAL;
2440 }
2441
2442 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
2443 pr_err("%s: unsupported ops->ooboffs, %d\n",
2444 __func__, ops->ooboffs);
2445 return -EINVAL;
2446 }
2447
2448 if (ops->datbuf) {
2449 data_dma_addr_curr = data_dma_addr =
2450 msm_nand_dma_map(chip->dev, ops->datbuf,
2451 ops->len, DMA_TO_DEVICE);
2452 if (dma_mapping_error(chip->dev, data_dma_addr)) {
2453 pr_err("msm_nand_write_oob_dualnandc:"
2454 "failed to get dma addr "
2455 "for %p\n", ops->datbuf);
2456 return -EIO;
2457 }
2458 }
2459 if (ops->oobbuf) {
2460 oob_dma_addr_curr = oob_dma_addr =
2461 msm_nand_dma_map(chip->dev, ops->oobbuf,
2462 ops->ooblen, DMA_TO_DEVICE);
2463 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
2464 pr_err("msm_nand_write_oob_dualnandc:"
2465 "failed to get dma addr "
2466 "for %p\n", ops->oobbuf);
2467 err = -EIO;
2468 goto err_dma_map_oobbuf_failed;
2469 }
2470 }
2471 if (ops->mode != MTD_OOB_RAW)
2472 page_count = ops->len / mtd->writesize;
2473 else
2474 page_count = ops->len / (mtd->writesize + mtd->oobsize);
2475
2476 wait_event(chip->wait_queue, (dma_buffer =
2477 msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
2478
2479 if (chip->CFG1 & CFG1_WIDE_FLASH)
2480 cw_offset >>= 1;
2481
2482 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
2483 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
2484 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
2485 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
2486 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
2487 dma_buffer->data.adm_default_mux = 0x00000FC0;
2488 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
2489 dma_buffer->data.nc01_flash_dev_cmd_vld = 0x9;
2490 dma_buffer->data.nc10_flash_dev_cmd0 = 0x1085D060;
2491 dma_buffer->data.nc01_flash_dev_cmd_vld_default = 0x1D;
2492 dma_buffer->data.nc10_flash_dev_cmd0_default = 0x1080D060;
2493 dma_buffer->data.clrfstatus = 0x00000020;
2494 dma_buffer->data.clrrstatus = 0x000000C0;
2495
2496 while (page_count-- > 0) {
2497 cmd = dma_buffer->cmd;
2498
2499 if (ops->mode != MTD_OOB_RAW) {
2500 dma_buffer->data.cfg0 = ((chip->CFG0 & ~(7U << 6))
2501 & ~(1 << 4)) | ((((cwperpage >> 1)-1)) << 6);
2502 dma_buffer->data.cfg1 = chip->CFG1;
2503 if (enable_bch_ecc)
2504 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
2505 } else {
2506 dma_buffer->data.cfg0 = ((chip->CFG0_RAW &
2507 ~(7U << 6)) & ~(1 << 4)) | (((cwperpage >> 1)-1) << 6);
2508 dma_buffer->data.cfg1 = chip->CFG1_RAW |
2509 (chip->CFG1 & CFG1_WIDE_FLASH);
2510 }
2511
2512 /* Disables the automatic issuing of the read
2513 * status command for first NAND controller.
2514 */
2515 if (!interleave_enable)
2516 dma_buffer->data.cfg0_nc01 = dma_buffer->data.cfg0
2517 | (1 << 4);
2518 else
2519 dma_buffer->data.cfg0 |= (1 << 4);
2520
2521 dma_buffer->data.cmd = MSM_NAND_CMD_PRG_PAGE;
2522 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
2523 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
2524
2525 /* GO bit for the EXEC register */
2526 dma_buffer->data.exec = 1;
2527
2528 if (!interleave_enable) {
2529 dma_buffer->data.nandc01_addr0 = (page << 16) | 0x0;
2530 /* NC10 ADDR0 points to the next code word */
2531 dma_buffer->data.nandc10_addr0 =
2532 (page << 16) | cw_offset;
2533 } else {
2534 dma_buffer->data.nandc01_addr0 =
2535 dma_buffer->data.nandc10_addr0 = (page << 16) | 0x0;
2536 }
2537 /* ADDR1 */
2538 dma_buffer->data.nandc11_addr1 = (page >> 16) & 0xff;
2539
2540 BUILD_BUG_ON(16 != ARRAY_SIZE(dma_buffer->data.flash_status));
2541
2542 for (n = 0; n < cwperpage; n++) {
2543 /* status return words */
2544 dma_buffer->data.flash_status[n] = 0xeeeeeeee;
2545
2546 if (n == 0) {
2547 if (!interleave_enable) {
2548 cmd->cmd = 0;
2549 cmd->src = msm_virt_to_dma(chip,
2550 &dma_buffer->
2551 data.nc01_flash_dev_cmd_vld);
2552 cmd->dst = NC01(MSM_NAND_DEV_CMD_VLD);
2553 cmd->len = 4;
2554 cmd++;
2555
2556 cmd->cmd = 0;
2557 cmd->src = msm_virt_to_dma(chip,
2558 &dma_buffer->data.nc10_flash_dev_cmd0);
2559 cmd->dst = NC10(MSM_NAND_DEV_CMD0);
2560 cmd->len = 4;
2561 cmd++;
2562
2563 /* common settings for both NC01 & NC10
2564 * NC01, NC10 --> ADDR1 / CHIPSEL
2565 */
2566 cmd->cmd = 0;
2567 cmd->src = msm_virt_to_dma(chip,
2568 &dma_buffer->data.nandc11_addr1);
2569 cmd->dst = NC11(MSM_NAND_ADDR1);
2570 cmd->len = 8;
2571 cmd++;
2572
2573 /* Disables the automatic issue of the
2574 * read status command after the write
2575 * operation.
2576 */
2577 cmd->cmd = 0;
2578 cmd->src = msm_virt_to_dma(chip,
2579 &dma_buffer->data.cfg0_nc01);
2580 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
2581 cmd->len = 4;
2582 cmd++;
2583
2584 cmd->cmd = 0;
2585 cmd->src = msm_virt_to_dma(chip,
2586 &dma_buffer->data.cfg0);
2587 cmd->dst = NC10(MSM_NAND_DEV0_CFG0);
2588 cmd->len = 4;
2589 cmd++;
2590
2591 cmd->cmd = 0;
2592 cmd->src = msm_virt_to_dma(chip,
2593 &dma_buffer->data.cfg1);
2594 cmd->dst = NC11(MSM_NAND_DEV0_CFG1);
2595 if (enable_bch_ecc)
2596 cmd->len = 8;
2597 else
2598 cmd->len = 4;
2599 cmd++;
2600 } else {
2601 /* enable CS1 */
2602 cmd->cmd = 0;
2603 cmd->src = msm_virt_to_dma(chip,
2604 &dma_buffer->
2605 data.ebi2_chip_select_cfg0);
2606 cmd->dst = EBI2_CHIP_SELECT_CFG0;
2607 cmd->len = 4;
2608 cmd++;
2609
2610 /* NC11 --> ADDR1 */
2611 cmd->cmd = 0;
2612 cmd->src = msm_virt_to_dma(chip,
2613 &dma_buffer->data.nandc11_addr1);
2614 cmd->dst = NC11(MSM_NAND_ADDR1);
2615 cmd->len = 4;
2616 cmd++;
2617
2618 /* Enable CS0 for NC01 */
2619 cmd->cmd = 0;
2620 cmd->src = msm_virt_to_dma(chip,
2621 &dma_buffer->data.chipsel_cs0);
2622 cmd->dst =
2623 NC01(MSM_NAND_FLASH_CHIP_SELECT);
2624 cmd->len = 4;
2625 cmd++;
2626
2627 /* Enable CS1 for NC10 */
2628 cmd->cmd = 0;
2629 cmd->src = msm_virt_to_dma(chip,
2630 &dma_buffer->data.chipsel_cs1);
2631 cmd->dst =
2632 NC10(MSM_NAND_FLASH_CHIP_SELECT);
2633 cmd->len = 4;
2634 cmd++;
2635
2636 /* config DEV0_CFG0 & CFG1 for CS0 */
2637 cmd->cmd = 0;
2638 cmd->src = msm_virt_to_dma(chip,
2639 &dma_buffer->data.cfg0);
2640 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
2641 cmd->len = 8;
2642 cmd++;
2643
2644 /* config DEV1_CFG0 & CFG1 for CS1 */
2645 cmd->cmd = 0;
2646 cmd->src = msm_virt_to_dma(chip,
2647 &dma_buffer->data.cfg0);
2648 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
2649 cmd->len = 8;
2650 cmd++;
2651 }
2652
2653 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
2654 cmd->cmd = 0;
2655 cmd->src = msm_virt_to_dma(chip,
2656 &dma_buffer->data.ecccfg);
2657 cmd->dst = NC11(MSM_NAND_EBI2_ECC_BUF_CFG);
2658 cmd->len = 4;
2659 cmd++;
2660
2661 /* NC01 --> ADDR0 */
2662 cmd->cmd = 0;
2663 cmd->src = msm_virt_to_dma(chip,
2664 &dma_buffer->data.nandc01_addr0);
2665 cmd->dst = NC01(MSM_NAND_ADDR0);
2666 cmd->len = 4;
2667 cmd++;
2668
2669 /* NC10 --> ADDR0 */
2670 cmd->cmd = 0;
2671 cmd->src = msm_virt_to_dma(chip,
2672 &dma_buffer->data.nandc10_addr0);
2673 cmd->dst = NC10(MSM_NAND_ADDR0);
2674 cmd->len = 4;
2675 cmd++;
2676 }
2677
2678 if (n % 2 == 0) {
2679 /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
2680 cmd->cmd = 0;
2681 cmd->src = msm_virt_to_dma(chip,
2682 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
2683 cmd->dst = EBI2_NAND_ADM_MUX;
2684 cmd->len = 4;
2685 cmd++;
2686
2687 /* CMD */
2688 cmd->cmd = DST_CRCI_NAND_CMD;
2689 cmd->src = msm_virt_to_dma(chip,
2690 &dma_buffer->data.cmd);
2691 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
2692 cmd->len = 4;
2693 cmd++;
2694 } else {
2695 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
2696 cmd->cmd = 0;
2697 cmd->src = msm_virt_to_dma(chip,
2698 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
2699 cmd->dst = EBI2_NAND_ADM_MUX;
2700 cmd->len = 4;
2701 cmd++;
2702
2703 /* CMD */
2704 cmd->cmd = DST_CRCI_NAND_CMD;
2705 cmd->src = msm_virt_to_dma(chip,
2706 &dma_buffer->data.cmd);
2707 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
2708 cmd->len = 4;
2709 cmd++;
2710 }
2711
2712 if (ops->mode != MTD_OOB_RAW)
2713 sectordatawritesize = (n < (cwperpage - 1)) ?
2714 516 : (512 - ((cwperpage - 1) << 2));
2715 else
2716 sectordatawritesize = chip->cw_size;
2717
2718 cmd->cmd = 0;
2719 cmd->src = data_dma_addr_curr;
2720 data_dma_addr_curr += sectordatawritesize;
2721
2722 if (n % 2 == 0)
2723 cmd->dst = NC01(MSM_NAND_FLASH_BUFFER);
2724 else
2725 cmd->dst = NC10(MSM_NAND_FLASH_BUFFER);
2726 cmd->len = sectordatawritesize;
2727 cmd++;
2728
2729 if (ops->oobbuf) {
2730 if (n == (cwperpage - 1)) {
2731 cmd->cmd = 0;
2732 cmd->src = oob_dma_addr_curr;
2733 cmd->dst = NC10(MSM_NAND_FLASH_BUFFER) +
2734 (512 - ((cwperpage - 1) << 2));
2735 if ((cwperpage << 2) < oob_len)
2736 cmd->len = (cwperpage << 2);
2737 else
2738 cmd->len = oob_len;
2739 oob_dma_addr_curr += cmd->len;
2740 oob_len -= cmd->len;
2741 if (cmd->len > 0)
2742 cmd++;
2743 }
2744 if (ops->mode != MTD_OOB_AUTO) {
2745 /* skip ecc bytes in oobbuf */
2746 if (oob_len < chip->ecc_parity_bytes) {
2747 oob_dma_addr_curr +=
2748 chip->ecc_parity_bytes;
2749 oob_len -=
2750 chip->ecc_parity_bytes;
2751 } else {
2752 oob_dma_addr_curr += oob_len;
2753 oob_len = 0;
2754 }
2755 }
2756 }
2757
2758 if (n % 2 == 0) {
2759 if (n != 0) {
2760 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
2761 cmd->cmd = 0;
2762 cmd->src = msm_virt_to_dma(chip,
2763 &dma_buffer->
2764 data.adm_mux_data_ack_req_nc01);
2765 cmd->dst = EBI2_NAND_ADM_MUX;
2766 cmd->len = 4;
2767 cmd++;
2768
2769 /* block on data ready from NC10, then
2770 * read the status register
2771 */
2772 cmd->cmd = SRC_CRCI_NAND_DATA;
2773 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
2774 cmd->dst = msm_virt_to_dma(chip,
2775 &dma_buffer->data.flash_status[n-1]);
2776 cmd->len = 4;
2777 cmd++;
2778 }
2779 /* kick the NC01 execute register */
2780 cmd->cmd = 0;
2781 cmd->src = msm_virt_to_dma(chip,
2782 &dma_buffer->data.exec);
2783 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
2784 cmd->len = 4;
2785 cmd++;
2786 } else {
2787 /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
2788 cmd->cmd = 0;
2789 cmd->src = msm_virt_to_dma(chip,
2790 &dma_buffer->data.adm_mux_data_ack_req_nc10);
2791 cmd->dst = EBI2_NAND_ADM_MUX;
2792 cmd->len = 4;
2793 cmd++;
2794
2795 /* block on data ready from NC01, then
2796 * read the status register
2797 */
2798 cmd->cmd = SRC_CRCI_NAND_DATA;
2799 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
2800 cmd->dst = msm_virt_to_dma(chip,
2801 &dma_buffer->data.flash_status[n-1]);
2802 cmd->len = 4;
2803 cmd++;
2804
2805 /* kick the execute register */
2806 cmd->cmd = 0;
2807 cmd->src =
2808 msm_virt_to_dma(chip, &dma_buffer->data.exec);
2809 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
2810 cmd->len = 4;
2811 cmd++;
2812 }
2813 }
2814
2815 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
2816 cmd->cmd = 0;
2817 cmd->src = msm_virt_to_dma(chip,
2818 &dma_buffer->data.adm_mux_data_ack_req_nc01);
2819 cmd->dst = EBI2_NAND_ADM_MUX;
2820 cmd->len = 4;
2821 cmd++;
2822
2823 /* we should process outstanding request */
2824 /* block on data ready, then
2825 * read the status register
2826 */
2827 cmd->cmd = SRC_CRCI_NAND_DATA;
2828 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
2829 cmd->dst = msm_virt_to_dma(chip,
2830 &dma_buffer->data.flash_status[n-1]);
2831 cmd->len = 4;
2832 cmd++;
2833
2834 cmd->cmd = 0;
2835 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
2836 cmd->dst = NC11(MSM_NAND_FLASH_STATUS);
2837 cmd->len = 4;
2838 cmd++;
2839
2840 cmd->cmd = 0;
2841 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
2842 cmd->dst = NC11(MSM_NAND_READ_STATUS);
2843 cmd->len = 4;
2844 cmd++;
2845
2846 /* MASK DATA ACK/REQ --> NC01 (0xFC0)*/
2847 cmd->cmd = 0;
2848 cmd->src = msm_virt_to_dma(chip,
2849 &dma_buffer->data.adm_default_mux);
2850 cmd->dst = EBI2_NAND_ADM_MUX;
2851 cmd->len = 4;
2852 cmd++;
2853
2854 if (!interleave_enable) {
2855 /* setting to defalut values back */
2856 cmd->cmd = 0;
2857 cmd->src = msm_virt_to_dma(chip,
2858 &dma_buffer->data.nc01_flash_dev_cmd_vld_default);
2859 cmd->dst = NC01(MSM_NAND_DEV_CMD_VLD);
2860 cmd->len = 4;
2861 cmd++;
2862
2863 cmd->cmd = 0;
2864 cmd->src = msm_virt_to_dma(chip,
2865 &dma_buffer->data.nc10_flash_dev_cmd0_default);
2866 cmd->dst = NC10(MSM_NAND_DEV_CMD0);
2867 cmd->len = 4;
2868 cmd++;
2869 } else {
2870 /* disable CS1 */
2871 cmd->cmd = 0;
2872 cmd->src = msm_virt_to_dma(chip,
2873 &dma_buffer->data.default_ebi2_chip_select_cfg0);
2874 cmd->dst = EBI2_CHIP_SELECT_CFG0;
2875 cmd->len = 4;
2876 cmd++;
2877 }
2878
2879 dma_buffer->cmd[0].cmd |= CMD_OCB;
2880 cmd[-1].cmd |= CMD_OCU | CMD_LC;
2881 BUILD_BUG_ON(16 * 6 + 18 != ARRAY_SIZE(dma_buffer->cmd));
2882 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
2883 dma_buffer->cmdptr =
2884 ((msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP);
2885
2886 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]2887 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2888 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(
2889 msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
2890 mb();
2891
2892 /* if any of the writes failed (0x10), or there was a
2893 * protection violation (0x100), or the program success
2894 * bit (0x80) is unset, we lose
2895 */
2896 err = 0;
2897 for (n = 0; n < cwperpage; n++) {
2898 if (dma_buffer->data.flash_status[n] & 0x110) {
2899 err = -EIO;
2900 break;
2901 }
2902 if (!(dma_buffer->data.flash_status[n] & 0x80)) {
2903 err = -EIO;
2904 break;
2905 }
2906 }
2907 /* check for flash status busy for the last codeword */
2908 if (!interleave_enable)
2909 if (!(dma_buffer->data.flash_status[cwperpage - 1]
2910 & 0x20)) {
2911 err = -EIO;
2912 break;
2913 }
2914#if VERBOSE
2915 for (n = 0; n < cwperpage; n++) {
2916 if (n%2) {
2917 pr_info("NC10: write pg %d: flash_status[%d] = %x\n",
2918 page, n, dma_buffer->data.flash_status[n]);
2919 } else {
2920 pr_info("NC01: write pg %d: flash_status[%d] = %x\n",
2921 page, n, dma_buffer->data.flash_status[n]);
2922 }
2923 }
2924#endif
2925 if (err)
2926 break;
2927 pages_written++;
2928 page++;
2929 }
2930 if (ops->mode != MTD_OOB_RAW)
2931 ops->retlen = mtd->writesize * pages_written;
2932 else
2933 ops->retlen = (mtd->writesize + mtd->oobsize) * pages_written;
2934
2935 ops->oobretlen = ops->ooblen - oob_len;
2936
2937 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
2938
2939 if (ops->oobbuf)
2940 dma_unmap_page(chip->dev, oob_dma_addr,
2941 ops->ooblen, DMA_TO_DEVICE);
2942err_dma_map_oobbuf_failed:
2943 if (ops->datbuf)
2944 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
2945 DMA_TO_DEVICE);
2946 if (err)
2947 pr_err("msm_nand_write_oob_dualnandc %llx %x %x failed %d\n",
2948 to, ops->len, ops->ooblen, err);
2949
2950#if VERBOSE
2951 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
2952 __func__, err, ops->retlen, ops->oobretlen);
2953
2954 pr_info("==================================================="
2955 "==========\n");
2956#endif
2957 return err;
2958}
2959
2960static int msm_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2961 size_t *retlen, const u_char *buf)
2962{
2963 int ret;
2964 struct mtd_oob_ops ops;
2965
2966 ops.mode = MTD_OOB_PLACE;
2967 ops.len = len;
2968 ops.retlen = 0;
2969 ops.ooblen = 0;
2970 ops.datbuf = (uint8_t *)buf;
2971 ops.oobbuf = NULL;
2972 if (!dual_nand_ctlr_present)
2973 ret = msm_nand_write_oob(mtd, to, &ops);
2974 else
2975 ret = msm_nand_write_oob_dualnandc(mtd, to, &ops);
2976 *retlen = ops.retlen;
2977 return ret;
2978}
2979
2980static int
2981msm_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2982{
2983 int err;
2984 struct msm_nand_chip *chip = mtd->priv;
2985 struct {
2986 dmov_s cmd[6];
2987 unsigned cmdptr;
2988 struct {
2989 uint32_t cmd;
2990 uint32_t addr0;
2991 uint32_t addr1;
2992 uint32_t chipsel;
2993 uint32_t cfg0;
2994 uint32_t cfg1;
2995 uint32_t exec;
2996 uint32_t flash_status;
2997 uint32_t clrfstatus;
2998 uint32_t clrrstatus;
2999 } data;
3000 } *dma_buffer;
3001 dmov_s *cmd;
3002 unsigned page = 0;
3003
3004 if (mtd->writesize == 2048)
3005 page = instr->addr >> 11;
3006
3007 if (mtd->writesize == 4096)
3008 page = instr->addr >> 12;
3009
3010 if (instr->addr & (mtd->erasesize - 1)) {
3011 pr_err("%s: unsupported erase address, 0x%llx\n",
3012 __func__, instr->addr);
3013 return -EINVAL;
3014 }
3015 if (instr->len != mtd->erasesize) {
3016 pr_err("%s: unsupported erase len, %lld\n",
3017 __func__, instr->len);
3018 return -EINVAL;
3019 }
3020
3021 wait_event(chip->wait_queue,
3022 (dma_buffer = msm_nand_get_dma_buffer(
3023 chip, sizeof(*dma_buffer))));
3024
3025 cmd = dma_buffer->cmd;
3026
3027 dma_buffer->data.cmd = MSM_NAND_CMD_BLOCK_ERASE;
3028 dma_buffer->data.addr0 = page;
3029 dma_buffer->data.addr1 = 0;
3030 dma_buffer->data.chipsel = 0 | 4;
3031 dma_buffer->data.exec = 1;
3032 dma_buffer->data.flash_status = 0xeeeeeeee;
3033 dma_buffer->data.cfg0 = chip->CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
3034 dma_buffer->data.cfg1 = chip->CFG1;
3035 dma_buffer->data.clrfstatus = 0x00000020;
3036 dma_buffer->data.clrrstatus = 0x000000C0;
3037
3038 cmd->cmd = DST_CRCI_NAND_CMD | CMD_OCB;
3039 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3040 cmd->dst = MSM_NAND_FLASH_CMD;
3041 cmd->len = 16;
3042 cmd++;
3043
3044 cmd->cmd = 0;
3045 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3046 cmd->dst = MSM_NAND_DEV0_CFG0;
3047 cmd->len = 8;
3048 cmd++;
3049
3050 cmd->cmd = 0;
3051 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3052 cmd->dst = MSM_NAND_EXEC_CMD;
3053 cmd->len = 4;
3054 cmd++;
3055
3056 cmd->cmd = SRC_CRCI_NAND_DATA;
3057 cmd->src = MSM_NAND_FLASH_STATUS;
3058 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status);
3059 cmd->len = 4;
3060 cmd++;
3061
3062 cmd->cmd = 0;
3063 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
3064 cmd->dst = MSM_NAND_FLASH_STATUS;
3065 cmd->len = 4;
3066 cmd++;
3067
3068 cmd->cmd = CMD_OCU | CMD_LC;
3069 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
3070 cmd->dst = MSM_NAND_READ_STATUS;
3071 cmd->len = 4;
3072 cmd++;
3073
3074 BUILD_BUG_ON(5 != ARRAY_SIZE(dma_buffer->cmd) - 1);
3075 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3076 dma_buffer->cmdptr =
3077 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3078
3079 mb();
3080 msm_dmov_exec_cmd(
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]3081 chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3082 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3083 mb();
3084
3085 /* we fail if there was an operation error, a mpu error, or the
3086 * erase success bit was not set.
3087 */
3088
3089 if (dma_buffer->data.flash_status & 0x110 ||
3090 !(dma_buffer->data.flash_status & 0x80))
3091 err = -EIO;
3092 else
3093 err = 0;
3094
3095 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
3096 if (err) {
3097 pr_err("%s: erase failed, 0x%llx\n", __func__, instr->addr);
3098 instr->fail_addr = instr->addr;
3099 instr->state = MTD_ERASE_FAILED;
3100 } else {
3101 instr->state = MTD_ERASE_DONE;
3102 instr->fail_addr = 0xffffffff;
3103 mtd_erase_callback(instr);
3104 }
3105 return err;
3106}
3107
3108static int
3109msm_nand_erase_dualnandc(struct mtd_info *mtd, struct erase_info *instr)
3110{
3111 int err;
3112 struct msm_nand_chip *chip = mtd->priv;
3113 struct {
3114 dmov_s cmd[18];
3115 unsigned cmdptr;
3116 struct {
3117 uint32_t cmd;
3118 uint32_t addr0;
3119 uint32_t addr1;
3120 uint32_t chipsel_cs0;
3121 uint32_t chipsel_cs1;
3122 uint32_t cfg0;
3123 uint32_t cfg1;
3124 uint32_t exec;
3125 uint32_t ecccfg;
3126 uint32_t ebi2_chip_select_cfg0;
3127 uint32_t adm_mux_data_ack_req_nc01;
3128 uint32_t adm_mux_cmd_ack_req_nc01;
3129 uint32_t adm_mux_data_ack_req_nc10;
3130 uint32_t adm_mux_cmd_ack_req_nc10;
3131 uint32_t adm_default_mux;
3132 uint32_t default_ebi2_chip_select_cfg0;
3133 uint32_t nc01_flash_dev_cmd0;
3134 uint32_t nc01_flash_dev_cmd0_default;
3135 uint32_t flash_status[2];
3136 uint32_t clrfstatus;
3137 uint32_t clrrstatus;
3138 } data;
3139 } *dma_buffer;
3140 dmov_s *cmd;
3141 unsigned page = 0;
3142
3143 if (mtd->writesize == 2048)
3144 page = instr->addr >> 11;
3145
3146 if (mtd->writesize == 4096)
3147 page = instr->addr >> 12;
3148
3149 if (mtd->writesize == 8192)
3150 page = (instr->addr >> 1) >> 12;
3151
3152 if (instr->addr & (mtd->erasesize - 1)) {
3153 pr_err("%s: unsupported erase address, 0x%llx\n",
3154 __func__, instr->addr);
3155 return -EINVAL;
3156 }
3157 if (instr->len != mtd->erasesize) {
3158 pr_err("%s: unsupported erase len, %lld\n",
3159 __func__, instr->len);
3160 return -EINVAL;
3161 }
3162
3163 wait_event(chip->wait_queue,
3164 (dma_buffer = msm_nand_get_dma_buffer(
3165 chip, sizeof(*dma_buffer))));
3166
3167 cmd = dma_buffer->cmd;
3168
3169 dma_buffer->data.cmd = MSM_NAND_CMD_BLOCK_ERASE;
3170 dma_buffer->data.addr0 = page;
3171 dma_buffer->data.addr1 = 0;
3172 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
3173 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
3174 dma_buffer->data.exec = 1;
3175 dma_buffer->data.flash_status[0] = 0xeeeeeeee;
3176 dma_buffer->data.flash_status[1] = 0xeeeeeeee;
3177 dma_buffer->data.cfg0 = chip->CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
3178 dma_buffer->data.cfg1 = chip->CFG1;
3179 dma_buffer->data.clrfstatus = 0x00000020;
3180 dma_buffer->data.clrrstatus = 0x000000C0;
3181
3182 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
3183 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
3184 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
3185 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
3186 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
3187 dma_buffer->data.adm_default_mux = 0x00000FC0;
3188 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
3189
3190 /* enable CS1 */
3191 cmd->cmd = 0 | CMD_OCB;
3192 cmd->src = msm_virt_to_dma(chip,
3193 &dma_buffer->data.ebi2_chip_select_cfg0);
3194 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3195 cmd->len = 4;
3196 cmd++;
3197
3198 /* erase CS0 block now !!! */
3199 /* 0xF14 */
3200 cmd->cmd = 0;
3201 cmd->src = msm_virt_to_dma(chip,
3202 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
3203 cmd->dst = EBI2_NAND_ADM_MUX;
3204 cmd->len = 4;
3205 cmd++;
3206
3207 cmd->cmd = DST_CRCI_NAND_CMD;
3208 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3209 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
3210 cmd->len = 16;
3211 cmd++;
3212
3213 cmd->cmd = 0;
3214 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3215 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
3216 cmd->len = 8;
3217 cmd++;
3218
3219 cmd->cmd = 0;
3220 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3221 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
3222 cmd->len = 4;
3223 cmd++;
3224
3225 /* 0xF28 */
3226 cmd->cmd = 0;
3227 cmd->src = msm_virt_to_dma(chip,
3228 &dma_buffer->data.adm_mux_data_ack_req_nc10);
3229 cmd->dst = EBI2_NAND_ADM_MUX;
3230 cmd->len = 4;
3231 cmd++;
3232
3233 cmd->cmd = SRC_CRCI_NAND_DATA;
3234 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
3235 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status[0]);
3236 cmd->len = 4;
3237 cmd++;
3238
3239 /* erase CS1 block now !!! */
3240 /* 0x53C */
3241 cmd->cmd = 0;
3242 cmd->src = msm_virt_to_dma(chip,
3243 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
3244 cmd->dst = EBI2_NAND_ADM_MUX;
3245 cmd->len = 4;
3246 cmd++;
3247
3248 cmd->cmd = DST_CRCI_NAND_CMD;
3249 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3250 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
3251 cmd->len = 12;
3252 cmd++;
3253
3254 cmd->cmd = 0;
3255 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.chipsel_cs1);
3256 cmd->dst = NC10(MSM_NAND_FLASH_CHIP_SELECT);
3257 cmd->len = 4;
3258 cmd++;
3259
3260 cmd->cmd = 0;
3261 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3262 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
3263 cmd->len = 8;
3264
3265 cmd->cmd = 0;
3266 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3267 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
3268 cmd->len = 4;
3269 cmd++;
3270
3271 /* 0xA3C */
3272 cmd->cmd = 0;
3273 cmd->src = msm_virt_to_dma(chip,
3274 &dma_buffer->data.adm_mux_data_ack_req_nc01);
3275 cmd->dst = EBI2_NAND_ADM_MUX;
3276 cmd->len = 4;
3277 cmd++;
3278
3279 cmd->cmd = SRC_CRCI_NAND_DATA;
3280 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
3281 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status[1]);
3282 cmd->len = 4;
3283 cmd++;
3284
3285 cmd->cmd = 0;
3286 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
3287 cmd->dst = NC11(MSM_NAND_FLASH_STATUS);
3288 cmd->len = 4;
3289 cmd++;
3290
3291 cmd->cmd = 0;
3292 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
3293 cmd->dst = NC11(MSM_NAND_READ_STATUS);
3294 cmd->len = 4;
3295 cmd++;
3296
3297 cmd->cmd = 0;
3298 cmd->src = msm_virt_to_dma(chip,
3299 &dma_buffer->data.adm_default_mux);
3300 cmd->dst = EBI2_NAND_ADM_MUX;
3301 cmd->len = 4;
3302 cmd++;
3303
3304 /* disable CS1 */
3305 cmd->cmd = CMD_OCU | CMD_LC;
3306 cmd->src = msm_virt_to_dma(chip,
3307 &dma_buffer->data.default_ebi2_chip_select_cfg0);
3308 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3309 cmd->len = 4;
3310 cmd++;
3311
3312 BUILD_BUG_ON(17 != ARRAY_SIZE(dma_buffer->cmd) - 1);
3313 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3314
3315 dma_buffer->cmdptr =
3316 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3317
3318 mb();
3319 msm_dmov_exec_cmd(
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]3320 chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3321 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3322 mb();
3323
3324 /* we fail if there was an operation error, a mpu error, or the
3325 * erase success bit was not set.
3326 */
3327
3328 if (dma_buffer->data.flash_status[0] & 0x110 ||
3329 !(dma_buffer->data.flash_status[0] & 0x80) ||
3330 dma_buffer->data.flash_status[1] & 0x110 ||
3331 !(dma_buffer->data.flash_status[1] & 0x80))
3332 err = -EIO;
3333 else
3334 err = 0;
3335
3336 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
3337 if (err) {
3338 pr_err("%s: erase failed, 0x%llx\n", __func__, instr->addr);
3339 instr->fail_addr = instr->addr;
3340 instr->state = MTD_ERASE_FAILED;
3341 } else {
3342 instr->state = MTD_ERASE_DONE;
3343 instr->fail_addr = 0xffffffff;
3344 mtd_erase_callback(instr);
3345 }
3346 return err;
3347}
3348
3349static int
3350msm_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
3351{
3352 struct msm_nand_chip *chip = mtd->priv;
3353 int ret;
3354 struct {
3355 dmov_s cmd[5];
3356 unsigned cmdptr;
3357 struct {
3358 uint32_t cmd;
3359 uint32_t addr0;
3360 uint32_t addr1;
3361 uint32_t chipsel;
3362 uint32_t cfg0;
3363 uint32_t cfg1;
3364 uint32_t eccbchcfg;
3365 uint32_t exec;
3366 uint32_t ecccfg;
3367 struct {
3368 uint32_t flash_status;
3369 uint32_t buffer_status;
3370 } result;
3371 } data;
3372 } *dma_buffer;
3373 dmov_s *cmd;
3374 uint8_t *buf;
3375 unsigned page = 0;
3376 unsigned cwperpage;
3377
3378 if (mtd->writesize == 2048)
3379 page = ofs >> 11;
3380
3381 if (mtd->writesize == 4096)
3382 page = ofs >> 12;
3383
3384 cwperpage = (mtd->writesize >> 9);
3385
3386 /* Check for invalid offset */
3387 if (ofs > mtd->size)
3388 return -EINVAL;
3389 if (ofs & (mtd->erasesize - 1)) {
3390 pr_err("%s: unsupported block address, 0x%x\n",
3391 __func__, (uint32_t)ofs);
3392 return -EINVAL;
3393 }
3394
3395 wait_event(chip->wait_queue,
3396 (dma_buffer = msm_nand_get_dma_buffer(chip ,
3397 sizeof(*dma_buffer) + 4)));
3398 buf = (uint8_t *)dma_buffer + sizeof(*dma_buffer);
3399
3400 /* Read 4 bytes starting from the bad block marker location
3401 * in the last code word of the page
3402 */
3403
3404 cmd = dma_buffer->cmd;
3405
3406 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
3407 dma_buffer->data.cfg0 = chip->CFG0_RAW & ~(7U << 6);
3408 dma_buffer->data.cfg1 = chip->CFG1_RAW |
3409 (chip->CFG1 & CFG1_WIDE_FLASH);
3410 if (enable_bch_ecc)
3411 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
3412
3413 if (chip->CFG1 & CFG1_WIDE_FLASH)
3414 dma_buffer->data.addr0 = (page << 16) |
3415 ((chip->cw_size * (cwperpage-1)) >> 1);
3416 else
3417 dma_buffer->data.addr0 = (page << 16) |
3418 (chip->cw_size * (cwperpage-1));
3419
3420 dma_buffer->data.addr1 = (page >> 16) & 0xff;
3421 dma_buffer->data.chipsel = 0 | 4;
3422
3423 dma_buffer->data.exec = 1;
3424
3425 dma_buffer->data.result.flash_status = 0xeeeeeeee;
3426 dma_buffer->data.result.buffer_status = 0xeeeeeeee;
3427
3428 cmd->cmd = DST_CRCI_NAND_CMD;
3429 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3430 cmd->dst = MSM_NAND_FLASH_CMD;
3431 cmd->len = 16;
3432 cmd++;
3433
3434 cmd->cmd = 0;
3435 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3436 cmd->dst = MSM_NAND_DEV0_CFG0;
3437 if (enable_bch_ecc)
3438 cmd->len = 12;
3439 else
3440 cmd->len = 8;
3441 cmd++;
3442
3443 cmd->cmd = 0;
3444 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3445 cmd->dst = MSM_NAND_EXEC_CMD;
3446 cmd->len = 4;
3447 cmd++;
3448
3449 cmd->cmd = SRC_CRCI_NAND_DATA;
3450 cmd->src = MSM_NAND_FLASH_STATUS;
3451 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result);
3452 cmd->len = 8;
3453 cmd++;
3454
3455 cmd->cmd = 0;
3456 cmd->src = MSM_NAND_FLASH_BUFFER +
3457 (mtd->writesize - (chip->cw_size * (cwperpage-1)));
3458 cmd->dst = msm_virt_to_dma(chip, buf);
3459 cmd->len = 4;
3460 cmd++;
3461
3462 BUILD_BUG_ON(5 != ARRAY_SIZE(dma_buffer->cmd));
3463 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3464 dma_buffer->cmd[0].cmd |= CMD_OCB;
3465 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3466
3467 dma_buffer->cmdptr = (msm_virt_to_dma(chip,
3468 dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3469
3470 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]3471 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3472 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3473 mb();
3474
3475 ret = 0;
3476 if (dma_buffer->data.result.flash_status & 0x110)
3477 ret = -EIO;
3478
3479 if (!ret) {
3480 /* Check for bad block marker byte */
3481 if (chip->CFG1 & CFG1_WIDE_FLASH) {
3482 if (buf[0] != 0xFF || buf[1] != 0xFF)
3483 ret = 1;
3484 } else {
3485 if (buf[0] != 0xFF)
3486 ret = 1;
3487 }
3488 }
3489
3490 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer) + 4);
3491 return ret;
3492}
3493
3494static int
3495msm_nand_block_isbad_dualnandc(struct mtd_info *mtd, loff_t ofs)
3496{
3497 struct msm_nand_chip *chip = mtd->priv;
3498 int ret;
3499 struct {
3500 dmov_s cmd[18];
3501 unsigned cmdptr;
3502 struct {
3503 uint32_t cmd;
3504 uint32_t addr0;
3505 uint32_t addr1;
3506 uint32_t chipsel_cs0;
3507 uint32_t chipsel_cs1;
3508 uint32_t cfg0;
3509 uint32_t cfg1;
3510 uint32_t exec;
3511 uint32_t ecccfg;
3512 uint32_t ebi2_chip_select_cfg0;
3513 uint32_t adm_mux_data_ack_req_nc01;
3514 uint32_t adm_mux_cmd_ack_req_nc01;
3515 uint32_t adm_mux_data_ack_req_nc10;
3516 uint32_t adm_mux_cmd_ack_req_nc10;
3517 uint32_t adm_default_mux;
3518 uint32_t default_ebi2_chip_select_cfg0;
3519 struct {
3520 uint32_t flash_status;
3521 uint32_t buffer_status;
3522 } result[2];
3523 } data;
3524 } *dma_buffer;
3525 dmov_s *cmd;
3526 uint8_t *buf01;
3527 uint8_t *buf10;
3528 unsigned page = 0;
3529 unsigned cwperpage;
3530
3531 if (mtd->writesize == 2048)
3532 page = ofs >> 11;
3533
3534 if (mtd->writesize == 4096)
3535 page = ofs >> 12;
3536
3537 if (mtd->writesize == 8192)
3538 page = (ofs >> 1) >> 12;
3539
3540 cwperpage = ((mtd->writesize >> 1) >> 9);
3541
3542 /* Check for invalid offset */
3543 if (ofs > mtd->size)
3544 return -EINVAL;
3545 if (ofs & (mtd->erasesize - 1)) {
3546 pr_err("%s: unsupported block address, 0x%x\n",
3547 __func__, (uint32_t)ofs);
3548 return -EINVAL;
3549 }
3550
3551 wait_event(chip->wait_queue,
3552 (dma_buffer = msm_nand_get_dma_buffer(chip ,
3553 sizeof(*dma_buffer) + 8)));
3554 buf01 = (uint8_t *)dma_buffer + sizeof(*dma_buffer);
3555 buf10 = buf01 + 4;
3556
3557 /* Read 4 bytes starting from the bad block marker location
3558 * in the last code word of the page
3559 */
3560 cmd = dma_buffer->cmd;
3561
3562 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
3563 dma_buffer->data.cfg0 = chip->CFG0_RAW & ~(7U << 6);
3564 dma_buffer->data.cfg1 = chip->CFG1_RAW |
3565 (chip->CFG1 & CFG1_WIDE_FLASH);
3566
3567 if (chip->CFG1 & CFG1_WIDE_FLASH)
3568 dma_buffer->data.addr0 = (page << 16) |
3569 ((528*(cwperpage-1)) >> 1);
3570 else
3571 dma_buffer->data.addr0 = (page << 16) |
3572 (528*(cwperpage-1));
3573
3574 dma_buffer->data.addr1 = (page >> 16) & 0xff;
3575 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
3576 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
3577
3578 dma_buffer->data.exec = 1;
3579
3580 dma_buffer->data.result[0].flash_status = 0xeeeeeeee;
3581 dma_buffer->data.result[0].buffer_status = 0xeeeeeeee;
3582 dma_buffer->data.result[1].flash_status = 0xeeeeeeee;
3583 dma_buffer->data.result[1].buffer_status = 0xeeeeeeee;
3584
3585 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
3586 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
3587 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
3588 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
3589 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
3590 dma_buffer->data.adm_default_mux = 0x00000FC0;
3591 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
3592
3593 /* Reading last code word from NC01 */
3594 /* enable CS1 */
3595 cmd->cmd = 0;
3596 cmd->src = msm_virt_to_dma(chip,
3597 &dma_buffer->data.ebi2_chip_select_cfg0);
3598 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3599 cmd->len = 4;
3600 cmd++;
3601
3602 /* 0xF14 */
3603 cmd->cmd = 0;
3604 cmd->src = msm_virt_to_dma(chip,
3605 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
3606 cmd->dst = EBI2_NAND_ADM_MUX;
3607 cmd->len = 4;
3608 cmd++;
3609
3610 cmd->cmd = DST_CRCI_NAND_CMD;
3611 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3612 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
3613 cmd->len = 16;
3614 cmd++;
3615
3616 cmd->cmd = 0;
3617 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3618 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
3619 cmd->len = 8;
3620 cmd++;
3621
3622 cmd->cmd = 0;
3623 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3624 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
3625 cmd->len = 4;
3626 cmd++;
3627
3628 /* 0xF28 */
3629 cmd->cmd = 0;
3630 cmd->src = msm_virt_to_dma(chip,
3631 &dma_buffer->data.adm_mux_data_ack_req_nc10);
3632 cmd->dst = EBI2_NAND_ADM_MUX;
3633 cmd->len = 4;
3634 cmd++;
3635
3636 cmd->cmd = SRC_CRCI_NAND_DATA;
3637 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
3638 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result[0]);
3639 cmd->len = 8;
3640 cmd++;
3641
3642 cmd->cmd = 0;
3643 cmd->src = NC01(MSM_NAND_FLASH_BUFFER) + ((mtd->writesize >> 1) -
3644 (528*(cwperpage-1)));
3645 cmd->dst = msm_virt_to_dma(chip, buf01);
3646 cmd->len = 4;
3647 cmd++;
3648
3649 /* Reading last code word from NC10 */
3650 /* 0x53C */
3651 cmd->cmd = 0;
3652 cmd->src = msm_virt_to_dma(chip,
3653 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
3654 cmd->dst = EBI2_NAND_ADM_MUX;
3655 cmd->len = 4;
3656 cmd++;
3657
3658 cmd->cmd = DST_CRCI_NAND_CMD;
3659 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3660 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
3661 cmd->len = 12;
3662 cmd++;
3663
3664 cmd->cmd = 0;
3665 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.chipsel_cs1);
3666 cmd->dst = NC10(MSM_NAND_FLASH_CHIP_SELECT);
3667 cmd->len = 4;
3668 cmd++;
3669
3670 cmd->cmd = 0;
3671 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3672 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
3673 cmd->len = 8;
3674 cmd++;
3675
3676 cmd->cmd = 0;
3677 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3678 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
3679 cmd->len = 4;
3680 cmd++;
3681
3682 /* A3C */
3683 cmd->cmd = 0;
3684 cmd->src = msm_virt_to_dma(chip,
3685 &dma_buffer->data.adm_mux_data_ack_req_nc01);
3686 cmd->dst = EBI2_NAND_ADM_MUX;
3687 cmd->len = 4;
3688 cmd++;
3689
3690 cmd->cmd = SRC_CRCI_NAND_DATA;
3691 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
3692 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result[1]);
3693 cmd->len = 8;
3694 cmd++;
3695
3696 cmd->cmd = 0;
3697 cmd->src = NC10(MSM_NAND_FLASH_BUFFER) + ((mtd->writesize >> 1) -
3698 (528*(cwperpage-1)));
3699 cmd->dst = msm_virt_to_dma(chip, buf10);
3700 cmd->len = 4;
3701 cmd++;
3702
3703 /* FC0 */
3704 cmd->cmd = 0;
3705 cmd->src = msm_virt_to_dma(chip,
3706 &dma_buffer->data.adm_default_mux);
3707 cmd->dst = EBI2_NAND_ADM_MUX;
3708 cmd->len = 4;
3709 cmd++;
3710
3711 /* disble CS1 */
3712 cmd->cmd = 0;
3713 cmd->src = msm_virt_to_dma(chip,
3714 &dma_buffer->data.ebi2_chip_select_cfg0);
3715 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3716 cmd->len = 4;
3717 cmd++;
3718
3719 BUILD_BUG_ON(18 != ARRAY_SIZE(dma_buffer->cmd));
3720 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3721 dma_buffer->cmd[0].cmd |= CMD_OCB;
3722 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3723
3724 dma_buffer->cmdptr = (msm_virt_to_dma(chip,
3725 dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3726
3727 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]3728 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST |
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3729 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3730 mb();
3731
3732 ret = 0;
3733 if ((dma_buffer->data.result[0].flash_status & 0x110) ||
3734 (dma_buffer->data.result[1].flash_status & 0x110))
3735 ret = -EIO;
3736
3737 if (!ret) {
3738 /* Check for bad block marker byte for NC01 & NC10 */
3739 if (chip->CFG1 & CFG1_WIDE_FLASH) {
3740 if ((buf01[0] != 0xFF || buf01[1] != 0xFF) ||
3741 (buf10[0] != 0xFF || buf10[1] != 0xFF))
3742 ret = 1;
3743 } else {
3744 if (buf01[0] != 0xFF || buf10[0] != 0xFF)
3745 ret = 1;
3746 }
3747 }
3748
3749 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer) + 8);
3750 return ret;
3751}
3752
3753static int
3754msm_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3755{
3756 struct mtd_oob_ops ops;
3757 int ret;
3758 uint8_t *buf;
3759
3760 /* Check for invalid offset */
3761 if (ofs > mtd->size)
3762 return -EINVAL;
3763 if (ofs & (mtd->erasesize - 1)) {
3764 pr_err("%s: unsupported block address, 0x%x\n",
3765 __func__, (uint32_t)ofs);
3766 return -EINVAL;
3767 }
3768
3769 /*
3770 Write all 0s to the first page
3771 This will set the BB marker to 0
3772 */
3773 buf = page_address(ZERO_PAGE());
3774
3775 ops.mode = MTD_OOB_RAW;
3776 ops.len = mtd->writesize + mtd->oobsize;
3777 ops.retlen = 0;
3778 ops.ooblen = 0;
3779 ops.datbuf = buf;
3780 ops.oobbuf = NULL;
3781 if (!interleave_enable)
3782 ret = msm_nand_write_oob(mtd, ofs, &ops);
3783 else
3784 ret = msm_nand_write_oob_dualnandc(mtd, ofs, &ops);
3785
3786 return ret;
3787}
3788
3789/**
3790 * msm_nand_suspend - [MTD Interface] Suspend the msm_nand flash
3791 * @param mtd MTD device structure
3792 */
3793static int msm_nand_suspend(struct mtd_info *mtd)
3794{
3795 return 0;
3796}
3797
3798/**
3799 * msm_nand_resume - [MTD Interface] Resume the msm_nand flash
3800 * @param mtd MTD device structure
3801 */
3802static void msm_nand_resume(struct mtd_info *mtd)
3803{
3804}
3805
3806struct onenand_information {
3807 uint16_t manufacturer_id;
3808 uint16_t device_id;
3809 uint16_t version_id;
3810 uint16_t data_buf_size;
3811 uint16_t boot_buf_size;
3812 uint16_t num_of_buffers;
3813 uint16_t technology;
3814};
3815
3816static struct onenand_information onenand_info;
3817static uint32_t nand_sfcmd_mode;
3818
3819uint32_t flash_onenand_probe(struct msm_nand_chip *chip)
3820{
3821 struct {
3822 dmov_s cmd[7];
3823 unsigned cmdptr;
3824 struct {
3825 uint32_t bcfg;
3826 uint32_t cmd;
3827 uint32_t exec;
3828 uint32_t status;
3829 uint32_t addr0;
3830 uint32_t addr1;
3831 uint32_t addr2;
3832 uint32_t addr3;
3833 uint32_t addr4;
3834 uint32_t addr5;
3835 uint32_t addr6;
3836 uint32_t data0;
3837 uint32_t data1;
3838 uint32_t data2;
3839 uint32_t data3;
3840 uint32_t data4;
3841 uint32_t data5;
3842 uint32_t data6;
3843 } data;
3844 } *dma_buffer;
3845 dmov_s *cmd;
3846
3847 int err = 0;
3848 uint32_t initialsflashcmd = 0;
3849
3850 initialsflashcmd = flash_rd_reg(chip, MSM_NAND_SFLASHC_CMD);
3851
3852 if ((initialsflashcmd & 0x10) == 0x10)
3853 nand_sfcmd_mode = MSM_NAND_SFCMD_ASYNC;
3854 else
3855 nand_sfcmd_mode = MSM_NAND_SFCMD_BURST;
3856
3857 printk(KERN_INFO "SFLASHC Async Mode bit: %x \n", nand_sfcmd_mode);
3858
3859 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
3860 (chip, sizeof(*dma_buffer))));
3861
3862 cmd = dma_buffer->cmd;
3863
3864 dma_buffer->data.bcfg = SFLASH_BCFG |
3865 (nand_sfcmd_mode ? 0 : (1 << 24));
3866 dma_buffer->data.cmd = SFLASH_PREPCMD(7, 0, 0,
3867 MSM_NAND_SFCMD_DATXS,
3868 nand_sfcmd_mode,
3869 MSM_NAND_SFCMD_REGRD);
3870 dma_buffer->data.exec = 1;
3871 dma_buffer->data.status = CLEAN_DATA_32;
3872 dma_buffer->data.addr0 = (ONENAND_DEVICE_ID << 16) |
3873 (ONENAND_MANUFACTURER_ID);
3874 dma_buffer->data.addr1 = (ONENAND_DATA_BUFFER_SIZE << 16) |
3875 (ONENAND_VERSION_ID);
3876 dma_buffer->data.addr2 = (ONENAND_AMOUNT_OF_BUFFERS << 16) |
3877 (ONENAND_BOOT_BUFFER_SIZE);
3878 dma_buffer->data.addr3 = (CLEAN_DATA_16 << 16) |
3879 (ONENAND_TECHNOLOGY << 0);
3880 dma_buffer->data.data0 = CLEAN_DATA_32;
3881 dma_buffer->data.data1 = CLEAN_DATA_32;
3882 dma_buffer->data.data2 = CLEAN_DATA_32;
3883 dma_buffer->data.data3 = CLEAN_DATA_32;
3884
3885 /* Enable and configure the SFlash controller */
3886 cmd->cmd = 0;
3887 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.bcfg);
3888 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
3889 cmd->len = 4;
3890 cmd++;
3891
3892 /* Block on cmd ready and write CMD register */
3893 cmd->cmd = DST_CRCI_NAND_CMD;
3894 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3895 cmd->dst = MSM_NAND_SFLASHC_CMD;
3896 cmd->len = 4;
3897 cmd++;
3898
3899 /* Configure the ADDR0 and ADDR1 registers */
3900 cmd->cmd = 0;
3901 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
3902 cmd->dst = MSM_NAND_ADDR0;
3903 cmd->len = 8;
3904 cmd++;
3905
3906 /* Configure the ADDR2 and ADDR3 registers */
3907 cmd->cmd = 0;
3908 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
3909 cmd->dst = MSM_NAND_ADDR2;
3910 cmd->len = 8;
3911 cmd++;
3912
3913 /* Kick the execute command */
3914 cmd->cmd = 0;
3915 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3916 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
3917 cmd->len = 4;
3918 cmd++;
3919
3920 /* Block on data ready, and read the two status registers */
3921 cmd->cmd = SRC_CRCI_NAND_DATA;
3922 cmd->src = MSM_NAND_SFLASHC_STATUS;
3923 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.status);
3924 cmd->len = 4;
3925 cmd++;
3926
3927 /* Read data registers - valid only if status says success */
3928 cmd->cmd = 0;
3929 cmd->src = MSM_NAND_GENP_REG0;
3930 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data0);
3931 cmd->len = 16;
3932 cmd++;
3933
3934 BUILD_BUG_ON(7 != ARRAY_SIZE(dma_buffer->cmd));
3935 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3936 dma_buffer->cmd[0].cmd |= CMD_OCB;
3937 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3938
3939 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
3940 >> 3) | CMD_PTR_LP;
3941
3942 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]3943 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3944 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
3945 &dma_buffer->cmdptr)));
3946 mb();
3947
3948 /* Check for errors, protection violations etc */
3949 if (dma_buffer->data.status & 0x110) {
3950 pr_info("%s: MPU/OP error"
3951 "(0x%x) during Onenand probe\n",
3952 __func__, dma_buffer->data.status);
3953 err = -EIO;
3954 } else {
3955
3956 onenand_info.manufacturer_id =
3957 (dma_buffer->data.data0 >> 0) & 0x0000FFFF;
3958 onenand_info.device_id =
3959 (dma_buffer->data.data0 >> 16) & 0x0000FFFF;
3960 onenand_info.version_id =
3961 (dma_buffer->data.data1 >> 0) & 0x0000FFFF;
3962 onenand_info.data_buf_size =
3963 (dma_buffer->data.data1 >> 16) & 0x0000FFFF;
3964 onenand_info.boot_buf_size =
3965 (dma_buffer->data.data2 >> 0) & 0x0000FFFF;
3966 onenand_info.num_of_buffers =
3967 (dma_buffer->data.data2 >> 16) & 0x0000FFFF;
3968 onenand_info.technology =
3969 (dma_buffer->data.data3 >> 0) & 0x0000FFFF;
3970
3971
3972 pr_info("======================================="
3973 "==========================\n");
3974
3975 pr_info("%s: manufacturer_id = 0x%x\n"
3976 , __func__, onenand_info.manufacturer_id);
3977 pr_info("%s: device_id = 0x%x\n"
3978 , __func__, onenand_info.device_id);
3979 pr_info("%s: version_id = 0x%x\n"
3980 , __func__, onenand_info.version_id);
3981 pr_info("%s: data_buf_size = 0x%x\n"
3982 , __func__, onenand_info.data_buf_size);
3983 pr_info("%s: boot_buf_size = 0x%x\n"
3984 , __func__, onenand_info.boot_buf_size);
3985 pr_info("%s: num_of_buffers = 0x%x\n"
3986 , __func__, onenand_info.num_of_buffers);
3987 pr_info("%s: technology = 0x%x\n"
3988 , __func__, onenand_info.technology);
3989
3990 pr_info("======================================="
3991 "==========================\n");
3992
3993 if ((onenand_info.manufacturer_id != 0x00EC)
3994 || ((onenand_info.device_id & 0x0040) != 0x0040)
3995 || (onenand_info.data_buf_size != 0x0800)
3996 || (onenand_info.boot_buf_size != 0x0200)
3997 || (onenand_info.num_of_buffers != 0x0201)
3998 || (onenand_info.technology != 0)) {
3999
4000 pr_info("%s: Detected an unsupported device\n"
4001 , __func__);
4002 err = -EIO;
4003 }
4004 }
4005
4006 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
4007
4008 return err;
4009}
4010
4011int msm_onenand_read_oob(struct mtd_info *mtd,
4012 loff_t from, struct mtd_oob_ops *ops)
4013{
4014 struct msm_nand_chip *chip = mtd->priv;
4015
4016 struct {
4017 dmov_s cmd[53];
4018 unsigned cmdptr;
4019 struct {
4020 uint32_t sfbcfg;
4021 uint32_t sfcmd[9];
4022 uint32_t sfexec;
4023 uint32_t sfstat[9];
4024 uint32_t addr0;
4025 uint32_t addr1;
4026 uint32_t addr2;
4027 uint32_t addr3;
4028 uint32_t addr4;
4029 uint32_t addr5;
4030 uint32_t addr6;
4031 uint32_t data0;
4032 uint32_t data1;
4033 uint32_t data2;
4034 uint32_t data3;
4035 uint32_t data4;
4036 uint32_t data5;
4037 uint32_t data6;
4038 uint32_t macro[5];
4039 } data;
4040 } *dma_buffer;
4041 dmov_s *cmd;
4042
4043 int err = 0;
4044 int i;
4045 dma_addr_t data_dma_addr = 0;
4046 dma_addr_t oob_dma_addr = 0;
4047 dma_addr_t data_dma_addr_curr = 0;
4048 dma_addr_t oob_dma_addr_curr = 0;
4049
4050 loff_t from_curr = 0;
4051 unsigned page_count;
4052 unsigned pages_read = 0;
4053
4054 uint16_t onenand_startaddr1;
4055 uint16_t onenand_startaddr8;
4056 uint16_t onenand_startaddr2;
4057 uint16_t onenand_startbuffer;
4058 uint16_t onenand_sysconfig1;
4059 uint16_t controller_status;
4060 uint16_t interrupt_status;
4061 uint16_t ecc_status;
4062#if VERBOSE
4063 pr_info("================================================="
4064 "================\n");
4065 pr_info("%s: from 0x%llx mode %d \ndatbuf 0x%p datlen 0x%x"
4066 "\noobbuf 0x%p ooblen 0x%x\n",
4067 __func__, from, ops->mode, ops->datbuf, ops->len,
4068 ops->oobbuf, ops->ooblen);
4069#endif
4070 if (!mtd) {
4071 pr_err("%s: invalid mtd pointer, 0x%x\n", __func__,
4072 (uint32_t)mtd);
4073 return -EINVAL;
4074 }
4075 if (from & (mtd->writesize - 1)) {
4076 pr_err("%s: unsupported from, 0x%llx\n", __func__,
4077 from);
4078 return -EINVAL;
4079 }
4080
4081 if ((ops->mode != MTD_OOB_PLACE) && (ops->mode != MTD_OOB_AUTO) &&
4082 (ops->mode != MTD_OOB_RAW)) {
4083 pr_err("%s: unsupported ops->mode, %d\n", __func__,
4084 ops->mode);
4085 return -EINVAL;
4086 }
4087
4088 if (((ops->datbuf == NULL) || (ops->len == 0)) &&
4089 ((ops->oobbuf == NULL) || (ops->ooblen == 0))) {
4090 pr_err("%s: incorrect ops fields - nothing to do\n",
4091 __func__);
4092 return -EINVAL;
4093 }
4094
4095 if ((ops->datbuf != NULL) && (ops->len == 0)) {
4096 pr_err("%s: data buffer passed but length 0\n",
4097 __func__);
4098 return -EINVAL;
4099 }
4100
4101 if ((ops->oobbuf != NULL) && (ops->ooblen == 0)) {
4102 pr_err("%s: oob buffer passed but length 0\n",
4103 __func__);
4104 return -EINVAL;
4105 }
4106
4107 if (ops->mode != MTD_OOB_RAW) {
4108 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
4109 /* when ops->datbuf is NULL, ops->len can be ooblen */
4110 pr_err("%s: unsupported ops->len, %d\n", __func__,
4111 ops->len);
4112 return -EINVAL;
4113 }
4114 } else {
4115 if (ops->datbuf != NULL &&
4116 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
4117 pr_err("%s: unsupported ops->len,"
4118 " %d for MTD_OOB_RAW\n", __func__, ops->len);
4119 return -EINVAL;
4120 }
4121 }
4122
4123 if ((ops->mode == MTD_OOB_RAW) && (ops->oobbuf)) {
4124 pr_err("%s: unsupported operation, oobbuf pointer "
4125 "passed in for RAW mode, %x\n", __func__,
4126 (uint32_t)ops->oobbuf);
4127 return -EINVAL;
4128 }
4129
4130 if (ops->oobbuf && !ops->datbuf) {
4131 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
4132 mtd->oobavail : mtd->oobsize);
4133 if ((page_count == 0) && (ops->ooblen))
4134 page_count = 1;
4135 } else if (ops->mode != MTD_OOB_RAW)
4136 page_count = ops->len / mtd->writesize;
4137 else
4138 page_count = ops->len / (mtd->writesize + mtd->oobsize);
4139
4140 if ((ops->mode == MTD_OOB_PLACE) && (ops->oobbuf != NULL)) {
4141 if (page_count * mtd->oobsize > ops->ooblen) {
4142 pr_err("%s: unsupported ops->ooblen for "
4143 "PLACE, %d\n", __func__, ops->ooblen);
4144 return -EINVAL;
4145 }
4146 }
4147
4148 if ((ops->mode == MTD_OOB_PLACE) && (ops->ooblen != 0) &&
4149 (ops->ooboffs != 0)) {
4150 pr_err("%s: unsupported ops->ooboffs, %d\n", __func__,
4151 ops->ooboffs);
4152 return -EINVAL;
4153 }
4154
4155 if (ops->datbuf) {
4156 memset(ops->datbuf, 0x55, ops->len);
4157 data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev,
4158 ops->datbuf, ops->len, DMA_FROM_DEVICE);
4159 if (dma_mapping_error(chip->dev, data_dma_addr)) {
4160 pr_err("%s: failed to get dma addr for %p\n",
4161 __func__, ops->datbuf);
4162 return -EIO;
4163 }
4164 }
4165 if (ops->oobbuf) {
4166 memset(ops->oobbuf, 0x55, ops->ooblen);
4167 oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev,
4168 ops->oobbuf, ops->ooblen, DMA_FROM_DEVICE);
4169 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
4170 pr_err("%s: failed to get dma addr for %p\n",
4171 __func__, ops->oobbuf);
4172 err = -EIO;
4173 goto err_dma_map_oobbuf_failed;
4174 }
4175 }
4176
4177 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
4178 (chip, sizeof(*dma_buffer))));
4179
4180 from_curr = from;
4181
4182 while (page_count-- > 0) {
4183
4184 cmd = dma_buffer->cmd;
4185
4186 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
4187 && (from_curr >= (mtd->size>>1))) { /* DDP Device */
4188 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
4189 (((uint32_t)(from_curr-(mtd->size>>1))
4190 / mtd->erasesize));
4191 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
4192 } else {
4193 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
4194 ((uint32_t)from_curr / mtd->erasesize) ;
4195 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
4196 }
4197
4198 onenand_startaddr8 = (((uint32_t)from_curr &
4199 (mtd->erasesize - 1)) / mtd->writesize) << 2;
4200 onenand_startbuffer = DATARAM0_0 << 8;
4201 onenand_sysconfig1 = (ops->mode == MTD_OOB_RAW) ?
4202 ONENAND_SYSCFG1_ECCDIS(nand_sfcmd_mode) :
4203 ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode);
4204
4205 dma_buffer->data.sfbcfg = SFLASH_BCFG |
4206 (nand_sfcmd_mode ? 0 : (1 << 24));
4207 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
4208 MSM_NAND_SFCMD_CMDXS,
4209 nand_sfcmd_mode,
4210 MSM_NAND_SFCMD_REGWR);
4211 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
4212 MSM_NAND_SFCMD_CMDXS,
4213 nand_sfcmd_mode,
4214 MSM_NAND_SFCMD_INTHI);
4215 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
4216 MSM_NAND_SFCMD_DATXS,
4217 nand_sfcmd_mode,
4218 MSM_NAND_SFCMD_REGRD);
4219 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
4220 MSM_NAND_SFCMD_DATXS,
4221 nand_sfcmd_mode,
4222 MSM_NAND_SFCMD_DATRD);
4223 dma_buffer->data.sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
4224 MSM_NAND_SFCMD_DATXS,
4225 nand_sfcmd_mode,
4226 MSM_NAND_SFCMD_DATRD);
4227 dma_buffer->data.sfcmd[5] = SFLASH_PREPCMD(256, 0, 0,
4228 MSM_NAND_SFCMD_DATXS,
4229 nand_sfcmd_mode,
4230 MSM_NAND_SFCMD_DATRD);
4231 dma_buffer->data.sfcmd[6] = SFLASH_PREPCMD(256, 0, 0,
4232 MSM_NAND_SFCMD_DATXS,
4233 nand_sfcmd_mode,
4234 MSM_NAND_SFCMD_DATRD);
4235 dma_buffer->data.sfcmd[7] = SFLASH_PREPCMD(32, 0, 0,
4236 MSM_NAND_SFCMD_DATXS,
4237 nand_sfcmd_mode,
4238 MSM_NAND_SFCMD_DATRD);
4239 dma_buffer->data.sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
4240 MSM_NAND_SFCMD_CMDXS,
4241 nand_sfcmd_mode,
4242 MSM_NAND_SFCMD_REGWR);
4243 dma_buffer->data.sfexec = 1;
4244 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
4245 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
4246 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
4247 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
4248 dma_buffer->data.sfstat[4] = CLEAN_DATA_32;
4249 dma_buffer->data.sfstat[5] = CLEAN_DATA_32;
4250 dma_buffer->data.sfstat[6] = CLEAN_DATA_32;
4251 dma_buffer->data.sfstat[7] = CLEAN_DATA_32;
4252 dma_buffer->data.sfstat[8] = CLEAN_DATA_32;
4253 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
4254 (ONENAND_SYSTEM_CONFIG_1);
4255 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
4256 (ONENAND_START_ADDRESS_1);
4257 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
4258 (ONENAND_START_ADDRESS_2);
4259 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
4260 (ONENAND_COMMAND);
4261 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
4262 (ONENAND_INTERRUPT_STATUS);
4263 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
4264 (ONENAND_SYSTEM_CONFIG_1);
4265 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
4266 (ONENAND_START_ADDRESS_1);
4267 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
4268 (onenand_sysconfig1);
4269 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
4270 (onenand_startaddr1);
4271 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
4272 (onenand_startaddr2);
4273 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4274 (ONENAND_CMDLOADSPARE);
4275 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
4276 (CLEAN_DATA_16);
4277 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
4278 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
4279 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
4280 (ONENAND_STARTADDR1_RES);
4281 dma_buffer->data.macro[0] = 0x0200;
4282 dma_buffer->data.macro[1] = 0x0300;
4283 dma_buffer->data.macro[2] = 0x0400;
4284 dma_buffer->data.macro[3] = 0x0500;
4285 dma_buffer->data.macro[4] = 0x8010;
4286
4287 /*************************************************************/
4288 /* Write necessary address registers in the onenand device */
4289 /*************************************************************/
4290
4291 /* Enable and configure the SFlash controller */
4292 cmd->cmd = 0;
4293 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
4294 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
4295 cmd->len = 4;
4296 cmd++;
4297
4298 /* Block on cmd ready and write CMD register */
4299 cmd->cmd = DST_CRCI_NAND_CMD;
4300 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
4301 cmd->dst = MSM_NAND_SFLASHC_CMD;
4302 cmd->len = 4;
4303 cmd++;
4304
4305 /* Write the ADDR0 and ADDR1 registers */
4306 cmd->cmd = 0;
4307 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
4308 cmd->dst = MSM_NAND_ADDR0;
4309 cmd->len = 8;
4310 cmd++;
4311
4312 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
4313 cmd->cmd = 0;
4314 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
4315 cmd->dst = MSM_NAND_ADDR2;
4316 cmd->len = 16;
4317 cmd++;
4318
4319 /* Write the ADDR6 registers */
4320 cmd->cmd = 0;
4321 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
4322 cmd->dst = MSM_NAND_ADDR6;
4323 cmd->len = 4;
4324 cmd++;
4325
4326 /* Write the GENP0, GENP1, GENP2, GENP3 registers */
4327 cmd->cmd = 0;
4328 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
4329 cmd->dst = MSM_NAND_GENP_REG0;
4330 cmd->len = 16;
4331 cmd++;
4332
4333 /* Write the FLASH_DEV_CMD4,5,6 registers */
4334 cmd->cmd = 0;
4335 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
4336 cmd->dst = MSM_NAND_DEV_CMD4;
4337 cmd->len = 12;
4338 cmd++;
4339
4340 /* Kick the execute command */
4341 cmd->cmd = 0;
4342 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4343 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4344 cmd->len = 4;
4345 cmd++;
4346
4347 /* Block on data ready, and read the status register */
4348 cmd->cmd = SRC_CRCI_NAND_DATA;
4349 cmd->src = MSM_NAND_SFLASHC_STATUS;
4350 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
4351 cmd->len = 4;
4352 cmd++;
4353
4354 /*************************************************************/
4355 /* Wait for the interrupt from the Onenand device controller */
4356 /*************************************************************/
4357
4358 /* Block on cmd ready and write CMD register */
4359 cmd->cmd = DST_CRCI_NAND_CMD;
4360 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
4361 cmd->dst = MSM_NAND_SFLASHC_CMD;
4362 cmd->len = 4;
4363 cmd++;
4364
4365 /* Kick the execute command */
4366 cmd->cmd = 0;
4367 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4368 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4369 cmd->len = 4;
4370 cmd++;
4371
4372 /* Block on data ready, and read the status register */
4373 cmd->cmd = SRC_CRCI_NAND_DATA;
4374 cmd->src = MSM_NAND_SFLASHC_STATUS;
4375 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
4376 cmd->len = 4;
4377 cmd++;
4378
4379 /*************************************************************/
4380 /* Read necessary status registers from the onenand device */
4381 /*************************************************************/
4382
4383 /* Block on cmd ready and write CMD register */
4384 cmd->cmd = DST_CRCI_NAND_CMD;
4385 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
4386 cmd->dst = MSM_NAND_SFLASHC_CMD;
4387 cmd->len = 4;
4388 cmd++;
4389
4390 /* Kick the execute command */
4391 cmd->cmd = 0;
4392 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4393 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4394 cmd->len = 4;
4395 cmd++;
4396
4397 /* Block on data ready, and read the status register */
4398 cmd->cmd = SRC_CRCI_NAND_DATA;
4399 cmd->src = MSM_NAND_SFLASHC_STATUS;
4400 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
4401 cmd->len = 4;
4402 cmd++;
4403
4404 /* Read the GENP3 register */
4405 cmd->cmd = 0;
4406 cmd->src = MSM_NAND_GENP_REG3;
4407 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
4408 cmd->len = 4;
4409 cmd++;
4410
4411 /* Read the DEVCMD4 register */
4412 cmd->cmd = 0;
4413 cmd->src = MSM_NAND_DEV_CMD4;
4414 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
4415 cmd->len = 4;
4416 cmd++;
4417
4418 /*************************************************************/
4419 /* Read the data ram area from the onenand buffer ram */
4420 /*************************************************************/
4421
4422 if (ops->datbuf) {
4423
4424 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4425 (ONENAND_CMDLOAD);
4426
4427 for (i = 0; i < 4; i++) {
4428
4429 /* Block on cmd ready and write CMD register */
4430 cmd->cmd = DST_CRCI_NAND_CMD;
4431 cmd->src = msm_virt_to_dma(chip,
4432 &dma_buffer->data.sfcmd[3+i]);
4433 cmd->dst = MSM_NAND_SFLASHC_CMD;
4434 cmd->len = 4;
4435 cmd++;
4436
4437 /* Write the MACRO1 register */
4438 cmd->cmd = 0;
4439 cmd->src = msm_virt_to_dma(chip,
4440 &dma_buffer->data.macro[i]);
4441 cmd->dst = MSM_NAND_MACRO1_REG;
4442 cmd->len = 4;
4443 cmd++;
4444
4445 /* Kick the execute command */
4446 cmd->cmd = 0;
4447 cmd->src = msm_virt_to_dma(chip,
4448 &dma_buffer->data.sfexec);
4449 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4450 cmd->len = 4;
4451 cmd++;
4452
4453 /* Block on data rdy, & read status register */
4454 cmd->cmd = SRC_CRCI_NAND_DATA;
4455 cmd->src = MSM_NAND_SFLASHC_STATUS;
4456 cmd->dst = msm_virt_to_dma(chip,
4457 &dma_buffer->data.sfstat[3+i]);
4458 cmd->len = 4;
4459 cmd++;
4460
4461 /* Transfer nand ctlr buf contents to usr buf */
4462 cmd->cmd = 0;
4463 cmd->src = MSM_NAND_FLASH_BUFFER;
4464 cmd->dst = data_dma_addr_curr;
4465 cmd->len = 512;
4466 data_dma_addr_curr += 512;
4467 cmd++;
4468 }
4469 }
4470
4471 if ((ops->oobbuf) || (ops->mode == MTD_OOB_RAW)) {
4472
4473 /* Block on cmd ready and write CMD register */
4474 cmd->cmd = DST_CRCI_NAND_CMD;
4475 cmd->src = msm_virt_to_dma(chip,
4476 &dma_buffer->data.sfcmd[7]);
4477 cmd->dst = MSM_NAND_SFLASHC_CMD;
4478 cmd->len = 4;
4479 cmd++;
4480
4481 /* Write the MACRO1 register */
4482 cmd->cmd = 0;
4483 cmd->src = msm_virt_to_dma(chip,
4484 &dma_buffer->data.macro[4]);
4485 cmd->dst = MSM_NAND_MACRO1_REG;
4486 cmd->len = 4;
4487 cmd++;
4488
4489 /* Kick the execute command */
4490 cmd->cmd = 0;
4491 cmd->src = msm_virt_to_dma(chip,
4492 &dma_buffer->data.sfexec);
4493 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4494 cmd->len = 4;
4495 cmd++;
4496
4497 /* Block on data ready, and read status register */
4498 cmd->cmd = SRC_CRCI_NAND_DATA;
4499 cmd->src = MSM_NAND_SFLASHC_STATUS;
4500 cmd->dst = msm_virt_to_dma(chip,
4501 &dma_buffer->data.sfstat[7]);
4502 cmd->len = 4;
4503 cmd++;
4504
4505 /* Transfer nand ctlr buffer contents into usr buf */
4506 if (ops->mode == MTD_OOB_AUTO) {
4507 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) {
4508 cmd->cmd = 0;
4509 cmd->src = MSM_NAND_FLASH_BUFFER +
4510 mtd->ecclayout->oobfree[i].offset;
4511 cmd->dst = oob_dma_addr_curr;
4512 cmd->len =
4513 mtd->ecclayout->oobfree[i].length;
4514 oob_dma_addr_curr +=
4515 mtd->ecclayout->oobfree[i].length;
4516 cmd++;
4517 }
4518 }
4519 if (ops->mode == MTD_OOB_PLACE) {
4520 cmd->cmd = 0;
4521 cmd->src = MSM_NAND_FLASH_BUFFER;
4522 cmd->dst = oob_dma_addr_curr;
4523 cmd->len = mtd->oobsize;
4524 oob_dma_addr_curr += mtd->oobsize;
4525 cmd++;
4526 }
4527 if (ops->mode == MTD_OOB_RAW) {
4528 cmd->cmd = 0;
4529 cmd->src = MSM_NAND_FLASH_BUFFER;
4530 cmd->dst = data_dma_addr_curr;
4531 cmd->len = mtd->oobsize;
4532 data_dma_addr_curr += mtd->oobsize;
4533 cmd++;
4534 }
4535 }
4536
4537 /*************************************************************/
4538 /* Restore the necessary registers to proper values */
4539 /*************************************************************/
4540
4541 /* Block on cmd ready and write CMD register */
4542 cmd->cmd = DST_CRCI_NAND_CMD;
4543 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[8]);
4544 cmd->dst = MSM_NAND_SFLASHC_CMD;
4545 cmd->len = 4;
4546 cmd++;
4547
4548 /* Kick the execute command */
4549 cmd->cmd = 0;
4550 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4551 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4552 cmd->len = 4;
4553 cmd++;
4554
4555 /* Block on data ready, and read the status register */
4556 cmd->cmd = SRC_CRCI_NAND_DATA;
4557 cmd->src = MSM_NAND_SFLASHC_STATUS;
4558 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[8]);
4559 cmd->len = 4;
4560 cmd++;
4561
4562
4563 BUILD_BUG_ON(53 != ARRAY_SIZE(dma_buffer->cmd));
4564 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
4565 dma_buffer->cmd[0].cmd |= CMD_OCB;
4566 cmd[-1].cmd |= CMD_OCU | CMD_LC;
4567
4568 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
4569 >> 3) | CMD_PTR_LP;
4570
4571 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]4572 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]4573 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
4574 &dma_buffer->cmdptr)));
4575 mb();
4576
4577 ecc_status = (dma_buffer->data.data3 >> 16) &
4578 0x0000FFFF;
4579 interrupt_status = (dma_buffer->data.data4 >> 0) &
4580 0x0000FFFF;
4581 controller_status = (dma_buffer->data.data4 >> 16) &
4582 0x0000FFFF;
4583
4584#if VERBOSE
4585 pr_info("\n%s: sflash status %x %x %x %x %x %x %x"
4586 "%x %x\n", __func__,
4587 dma_buffer->data.sfstat[0],
4588 dma_buffer->data.sfstat[1],
4589 dma_buffer->data.sfstat[2],
4590 dma_buffer->data.sfstat[3],
4591 dma_buffer->data.sfstat[4],
4592 dma_buffer->data.sfstat[5],
4593 dma_buffer->data.sfstat[6],
4594 dma_buffer->data.sfstat[7],
4595 dma_buffer->data.sfstat[8]);
4596
4597 pr_info("%s: controller_status = %x\n", __func__,
4598 controller_status);
4599 pr_info("%s: interrupt_status = %x\n", __func__,
4600 interrupt_status);
4601 pr_info("%s: ecc_status = %x\n", __func__,
4602 ecc_status);
4603#endif
4604 /* Check for errors, protection violations etc */
4605 if ((controller_status != 0)
4606 || (dma_buffer->data.sfstat[0] & 0x110)
4607 || (dma_buffer->data.sfstat[1] & 0x110)
4608 || (dma_buffer->data.sfstat[2] & 0x110)
4609 || (dma_buffer->data.sfstat[8] & 0x110)
4610 || ((dma_buffer->data.sfstat[3] & 0x110) &&
4611 (ops->datbuf))
4612 || ((dma_buffer->data.sfstat[4] & 0x110) &&
4613 (ops->datbuf))
4614 || ((dma_buffer->data.sfstat[5] & 0x110) &&
4615 (ops->datbuf))
4616 || ((dma_buffer->data.sfstat[6] & 0x110) &&
4617 (ops->datbuf))
4618 || ((dma_buffer->data.sfstat[7] & 0x110) &&
4619 ((ops->oobbuf)
4620 || (ops->mode == MTD_OOB_RAW)))) {
4621 pr_info("%s: ECC/MPU/OP error\n", __func__);
4622 err = -EIO;
4623 }
4624
4625 if (err)
4626 break;
4627 pages_read++;
4628 from_curr += mtd->writesize;
4629 }
4630
4631 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
4632
4633 if (ops->oobbuf) {
4634 dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen,
4635 DMA_FROM_DEVICE);
4636 }
4637err_dma_map_oobbuf_failed:
4638 if (ops->datbuf) {
4639 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
4640 DMA_FROM_DEVICE);
4641 }
4642
4643 if (err) {
4644 pr_err("%s: %llx %x %x failed\n", __func__, from_curr,
4645 ops->datbuf ? ops->len : 0, ops->ooblen);
4646 } else {
4647 ops->retlen = ops->oobretlen = 0;
4648 if (ops->datbuf != NULL) {
4649 if (ops->mode != MTD_OOB_RAW)
4650 ops->retlen = mtd->writesize * pages_read;
4651 else
4652 ops->retlen = (mtd->writesize + mtd->oobsize)
4653 * pages_read;
4654 }
4655 if (ops->oobbuf != NULL) {
4656 if (ops->mode == MTD_OOB_AUTO)
4657 ops->oobretlen = mtd->oobavail * pages_read;
4658 else
4659 ops->oobretlen = mtd->oobsize * pages_read;
4660 }
4661 }
4662
4663#if VERBOSE
4664 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
4665 __func__, err, ops->retlen, ops->oobretlen);
4666
4667 pr_info("==================================================="
4668 "==============\n");
4669#endif
4670 return err;
4671}
4672
4673int msm_onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
4674 size_t *retlen, u_char *buf)
4675{
4676 int ret;
4677 struct mtd_oob_ops ops;
4678
4679 ops.mode = MTD_OOB_PLACE;
4680 ops.datbuf = buf;
4681 ops.len = len;
4682 ops.retlen = 0;
4683 ops.oobbuf = NULL;
4684 ops.ooblen = 0;
4685 ops.oobretlen = 0;
4686 ret = msm_onenand_read_oob(mtd, from, &ops);
4687 *retlen = ops.retlen;
4688
4689 return ret;
4690}
4691
4692static int msm_onenand_write_oob(struct mtd_info *mtd, loff_t to,
4693 struct mtd_oob_ops *ops)
4694{
4695 struct msm_nand_chip *chip = mtd->priv;
4696
4697 struct {
4698 dmov_s cmd[53];
4699 unsigned cmdptr;
4700 struct {
4701 uint32_t sfbcfg;
4702 uint32_t sfcmd[10];
4703 uint32_t sfexec;
4704 uint32_t sfstat[10];
4705 uint32_t addr0;
4706 uint32_t addr1;
4707 uint32_t addr2;
4708 uint32_t addr3;
4709 uint32_t addr4;
4710 uint32_t addr5;
4711 uint32_t addr6;
4712 uint32_t data0;
4713 uint32_t data1;
4714 uint32_t data2;
4715 uint32_t data3;
4716 uint32_t data4;
4717 uint32_t data5;
4718 uint32_t data6;
4719 uint32_t macro[5];
4720 } data;
4721 } *dma_buffer;
4722 dmov_s *cmd;
4723
4724 int err = 0;
4725 int i, j, k;
4726 dma_addr_t data_dma_addr = 0;
4727 dma_addr_t oob_dma_addr = 0;
4728 dma_addr_t init_dma_addr = 0;
4729 dma_addr_t data_dma_addr_curr = 0;
4730 dma_addr_t oob_dma_addr_curr = 0;
4731 uint8_t *init_spare_bytes;
4732
4733 loff_t to_curr = 0;
4734 unsigned page_count;
4735 unsigned pages_written = 0;
4736
4737 uint16_t onenand_startaddr1;
4738 uint16_t onenand_startaddr8;
4739 uint16_t onenand_startaddr2;
4740 uint16_t onenand_startbuffer;
4741 uint16_t onenand_sysconfig1;
4742
4743 uint16_t controller_status;
4744 uint16_t interrupt_status;
4745 uint16_t ecc_status;
4746
4747#if VERBOSE
4748 pr_info("================================================="
4749 "================\n");
4750 pr_info("%s: to 0x%llx mode %d \ndatbuf 0x%p datlen 0x%x"
4751 "\noobbuf 0x%p ooblen 0x%x\n",
4752 __func__, to, ops->mode, ops->datbuf, ops->len,
4753 ops->oobbuf, ops->ooblen);
4754#endif
4755 if (!mtd) {
4756 pr_err("%s: invalid mtd pointer, 0x%x\n", __func__,
4757 (uint32_t)mtd);
4758 return -EINVAL;
4759 }
4760 if (to & (mtd->writesize - 1)) {
4761 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
4762 return -EINVAL;
4763 }
4764
4765 if ((ops->mode != MTD_OOB_PLACE) && (ops->mode != MTD_OOB_AUTO) &&
4766 (ops->mode != MTD_OOB_RAW)) {
4767 pr_err("%s: unsupported ops->mode, %d\n", __func__,
4768 ops->mode);
4769 return -EINVAL;
4770 }
4771
4772 if (((ops->datbuf == NULL) || (ops->len == 0)) &&
4773 ((ops->oobbuf == NULL) || (ops->ooblen == 0))) {
4774 pr_err("%s: incorrect ops fields - nothing to do\n",
4775 __func__);
4776 return -EINVAL;
4777 }
4778
4779 if ((ops->datbuf != NULL) && (ops->len == 0)) {
4780 pr_err("%s: data buffer passed but length 0\n",
4781 __func__);
4782 return -EINVAL;
4783 }
4784
4785 if ((ops->oobbuf != NULL) && (ops->ooblen == 0)) {
4786 pr_err("%s: oob buffer passed but length 0\n",
4787 __func__);
4788 return -EINVAL;
4789 }
4790
4791 if (ops->mode != MTD_OOB_RAW) {
4792 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
4793 /* when ops->datbuf is NULL, ops->len can be ooblen */
4794 pr_err("%s: unsupported ops->len, %d\n", __func__,
4795 ops->len);
4796 return -EINVAL;
4797 }
4798 } else {
4799 if (ops->datbuf != NULL &&
4800 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
4801 pr_err("%s: unsupported ops->len,"
4802 " %d for MTD_OOB_RAW\n", __func__, ops->len);
4803 return -EINVAL;
4804 }
4805 }
4806
4807 if ((ops->mode == MTD_OOB_RAW) && (ops->oobbuf)) {
4808 pr_err("%s: unsupported operation, oobbuf pointer "
4809 "passed in for RAW mode, %x\n", __func__,
4810 (uint32_t)ops->oobbuf);
4811 return -EINVAL;
4812 }
4813
4814 if (ops->oobbuf && !ops->datbuf) {
4815 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
4816 mtd->oobavail : mtd->oobsize);
4817 if ((page_count == 0) && (ops->ooblen))
4818 page_count = 1;
4819 } else if (ops->mode != MTD_OOB_RAW)
4820 page_count = ops->len / mtd->writesize;
4821 else
4822 page_count = ops->len / (mtd->writesize + mtd->oobsize);
4823
4824 if ((ops->mode == MTD_OOB_AUTO) && (ops->oobbuf != NULL)) {
4825 if (page_count > 1) {
4826 pr_err("%s: unsupported ops->ooblen for"
4827 "AUTO, %d\n", __func__, ops->ooblen);
4828 return -EINVAL;
4829 }
4830 }
4831
4832 if ((ops->mode == MTD_OOB_PLACE) && (ops->oobbuf != NULL)) {
4833 if (page_count * mtd->oobsize > ops->ooblen) {
4834 pr_err("%s: unsupported ops->ooblen for"
4835 "PLACE, %d\n", __func__, ops->ooblen);
4836 return -EINVAL;
4837 }
4838 }
4839
4840 if ((ops->mode == MTD_OOB_PLACE) && (ops->ooblen != 0) &&
4841 (ops->ooboffs != 0)) {
4842 pr_err("%s: unsupported ops->ooboffs, %d\n",
4843 __func__, ops->ooboffs);
4844 return -EINVAL;
4845 }
4846
4847 init_spare_bytes = kmalloc(64, GFP_KERNEL);
4848 if (!init_spare_bytes) {
4849 pr_err("%s: failed to alloc init_spare_bytes buffer\n",
4850 __func__);
4851 return -ENOMEM;
4852 }
4853 for (i = 0; i < 64; i++)
4854 init_spare_bytes[i] = 0xFF;
4855
4856 if ((ops->oobbuf) && (ops->mode == MTD_OOB_AUTO)) {
4857 for (i = 0, k = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++)
4858 for (j = 0; j < mtd->ecclayout->oobfree[i].length;
4859 j++) {
4860 init_spare_bytes[j +
4861 mtd->ecclayout->oobfree[i].offset]
4862 = (ops->oobbuf)[k];
4863 k++;
4864 }
4865 }
4866
4867 if (ops->datbuf) {
4868 data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev,
4869 ops->datbuf, ops->len, DMA_TO_DEVICE);
4870 if (dma_mapping_error(chip->dev, data_dma_addr)) {
4871 pr_err("%s: failed to get dma addr for %p\n",
4872 __func__, ops->datbuf);
4873 return -EIO;
4874 }
4875 }
4876 if (ops->oobbuf) {
4877 oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev,
4878 ops->oobbuf, ops->ooblen, DMA_TO_DEVICE);
4879 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
4880 pr_err("%s: failed to get dma addr for %p\n",
4881 __func__, ops->oobbuf);
4882 err = -EIO;
4883 goto err_dma_map_oobbuf_failed;
4884 }
4885 }
4886
4887 init_dma_addr = msm_nand_dma_map(chip->dev, init_spare_bytes, 64,
4888 DMA_TO_DEVICE);
4889 if (dma_mapping_error(chip->dev, init_dma_addr)) {
4890 pr_err("%s: failed to get dma addr for %p\n",
4891 __func__, init_spare_bytes);
4892 err = -EIO;
4893 goto err_dma_map_initbuf_failed;
4894 }
4895
4896
4897 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
4898 (chip, sizeof(*dma_buffer))));
4899
4900 to_curr = to;
4901
4902 while (page_count-- > 0) {
4903 cmd = dma_buffer->cmd;
4904
4905 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
4906 && (to_curr >= (mtd->size>>1))) { /* DDP Device */
4907 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
4908 (((uint32_t)(to_curr-(mtd->size>>1))
4909 / mtd->erasesize));
4910 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
4911 } else {
4912 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
4913 ((uint32_t)to_curr / mtd->erasesize) ;
4914 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
4915 }
4916
4917 onenand_startaddr8 = (((uint32_t)to_curr &
4918 (mtd->erasesize - 1)) / mtd->writesize) << 2;
4919 onenand_startbuffer = DATARAM0_0 << 8;
4920 onenand_sysconfig1 = (ops->mode == MTD_OOB_RAW) ?
4921 ONENAND_SYSCFG1_ECCDIS(nand_sfcmd_mode) :
4922 ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode);
4923
4924 dma_buffer->data.sfbcfg = SFLASH_BCFG |
4925 (nand_sfcmd_mode ? 0 : (1 << 24));
4926 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(6, 0, 0,
4927 MSM_NAND_SFCMD_CMDXS,
4928 nand_sfcmd_mode,
4929 MSM_NAND_SFCMD_REGWR);
4930 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(256, 0, 0,
4931 MSM_NAND_SFCMD_CMDXS,
4932 nand_sfcmd_mode,
4933 MSM_NAND_SFCMD_DATWR);
4934 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(256, 0, 0,
4935 MSM_NAND_SFCMD_CMDXS,
4936 nand_sfcmd_mode,
4937 MSM_NAND_SFCMD_DATWR);
4938 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
4939 MSM_NAND_SFCMD_CMDXS,
4940 nand_sfcmd_mode,
4941 MSM_NAND_SFCMD_DATWR);
4942 dma_buffer->data.sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
4943 MSM_NAND_SFCMD_CMDXS,
4944 nand_sfcmd_mode,
4945 MSM_NAND_SFCMD_DATWR);
4946 dma_buffer->data.sfcmd[5] = SFLASH_PREPCMD(32, 0, 0,
4947 MSM_NAND_SFCMD_CMDXS,
4948 nand_sfcmd_mode,
4949 MSM_NAND_SFCMD_DATWR);
4950 dma_buffer->data.sfcmd[6] = SFLASH_PREPCMD(1, 6, 0,
4951 MSM_NAND_SFCMD_CMDXS,
4952 nand_sfcmd_mode,
4953 MSM_NAND_SFCMD_REGWR);
4954 dma_buffer->data.sfcmd[7] = SFLASH_PREPCMD(0, 0, 32,
4955 MSM_NAND_SFCMD_CMDXS,
4956 nand_sfcmd_mode,
4957 MSM_NAND_SFCMD_INTHI);
4958 dma_buffer->data.sfcmd[8] = SFLASH_PREPCMD(3, 7, 0,
4959 MSM_NAND_SFCMD_DATXS,
4960 nand_sfcmd_mode,
4961 MSM_NAND_SFCMD_REGRD);
4962 dma_buffer->data.sfcmd[9] = SFLASH_PREPCMD(4, 10, 0,
4963 MSM_NAND_SFCMD_CMDXS,
4964 nand_sfcmd_mode,
4965 MSM_NAND_SFCMD_REGWR);
4966 dma_buffer->data.sfexec = 1;
4967 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
4968 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
4969 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
4970 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
4971 dma_buffer->data.sfstat[4] = CLEAN_DATA_32;
4972 dma_buffer->data.sfstat[5] = CLEAN_DATA_32;
4973 dma_buffer->data.sfstat[6] = CLEAN_DATA_32;
4974 dma_buffer->data.sfstat[7] = CLEAN_DATA_32;
4975 dma_buffer->data.sfstat[8] = CLEAN_DATA_32;
4976 dma_buffer->data.sfstat[9] = CLEAN_DATA_32;
4977 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
4978 (ONENAND_SYSTEM_CONFIG_1);
4979 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
4980 (ONENAND_START_ADDRESS_1);
4981 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
4982 (ONENAND_START_ADDRESS_2);
4983 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
4984 (ONENAND_COMMAND);
4985 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
4986 (ONENAND_INTERRUPT_STATUS);
4987 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
4988 (ONENAND_SYSTEM_CONFIG_1);
4989 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
4990 (ONENAND_START_ADDRESS_1);
4991 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
4992 (onenand_sysconfig1);
4993 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
4994 (onenand_startaddr1);
4995 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
4996 (onenand_startaddr2);
4997 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4998 (ONENAND_CMDPROGSPARE);
4999 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
5000 (CLEAN_DATA_16);
5001 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
5002 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5003 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
5004 (ONENAND_STARTADDR1_RES);
5005 dma_buffer->data.macro[0] = 0x0200;
5006 dma_buffer->data.macro[1] = 0x0300;
5007 dma_buffer->data.macro[2] = 0x0400;
5008 dma_buffer->data.macro[3] = 0x0500;
5009 dma_buffer->data.macro[4] = 0x8010;
5010
5011
5012 /*************************************************************/
5013 /* Write necessary address registers in the onenand device */
5014 /*************************************************************/
5015
5016 /* Enable and configure the SFlash controller */
5017 cmd->cmd = 0;
5018 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
5019 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
5020 cmd->len = 4;
5021 cmd++;
5022
5023 /* Block on cmd ready and write CMD register */
5024 cmd->cmd = DST_CRCI_NAND_CMD;
5025 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
5026 cmd->dst = MSM_NAND_SFLASHC_CMD;
5027 cmd->len = 4;
5028 cmd++;
5029
5030 /* Write the ADDR0 and ADDR1 registers */
5031 cmd->cmd = 0;
5032 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
5033 cmd->dst = MSM_NAND_ADDR0;
5034 cmd->len = 8;
5035 cmd++;
5036
5037 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
5038 cmd->cmd = 0;
5039 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
5040 cmd->dst = MSM_NAND_ADDR2;
5041 cmd->len = 16;
5042 cmd++;
5043
5044 /* Write the ADDR6 registers */
5045 cmd->cmd = 0;
5046 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
5047 cmd->dst = MSM_NAND_ADDR6;
5048 cmd->len = 4;
5049 cmd++;
5050
5051 /* Write the GENP0, GENP1, GENP2, GENP3 registers */
5052 cmd->cmd = 0;
5053 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
5054 cmd->dst = MSM_NAND_GENP_REG0;
5055 cmd->len = 16;
5056 cmd++;
5057
5058 /* Write the FLASH_DEV_CMD4,5,6 registers */
5059 cmd->cmd = 0;
5060 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5061 cmd->dst = MSM_NAND_DEV_CMD4;
5062 cmd->len = 12;
5063 cmd++;
5064
5065 /* Kick the execute command */
5066 cmd->cmd = 0;
5067 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5068 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5069 cmd->len = 4;
5070 cmd++;
5071
5072 /* Block on data ready, and read the status register */
5073 cmd->cmd = SRC_CRCI_NAND_DATA;
5074 cmd->src = MSM_NAND_SFLASHC_STATUS;
5075 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
5076 cmd->len = 4;
5077 cmd++;
5078
5079 /*************************************************************/
5080 /* Write the data ram area in the onenand buffer ram */
5081 /*************************************************************/
5082
5083 if (ops->datbuf) {
5084 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
5085 (ONENAND_CMDPROG);
5086
5087 for (i = 0; i < 4; i++) {
5088
5089 /* Block on cmd ready and write CMD register */
5090 cmd->cmd = DST_CRCI_NAND_CMD;
5091 cmd->src = msm_virt_to_dma(chip,
5092 &dma_buffer->data.sfcmd[1+i]);
5093 cmd->dst = MSM_NAND_SFLASHC_CMD;
5094 cmd->len = 4;
5095 cmd++;
5096
5097 /* Trnsfr usr buf contents to nand ctlr buf */
5098 cmd->cmd = 0;
5099 cmd->src = data_dma_addr_curr;
5100 cmd->dst = MSM_NAND_FLASH_BUFFER;
5101 cmd->len = 512;
5102 data_dma_addr_curr += 512;
5103 cmd++;
5104
5105 /* Write the MACRO1 register */
5106 cmd->cmd = 0;
5107 cmd->src = msm_virt_to_dma(chip,
5108 &dma_buffer->data.macro[i]);
5109 cmd->dst = MSM_NAND_MACRO1_REG;
5110 cmd->len = 4;
5111 cmd++;
5112
5113 /* Kick the execute command */
5114 cmd->cmd = 0;
5115 cmd->src = msm_virt_to_dma(chip,
5116 &dma_buffer->data.sfexec);
5117 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5118 cmd->len = 4;
5119 cmd++;
5120
5121 /* Block on data rdy, & read status register */
5122 cmd->cmd = SRC_CRCI_NAND_DATA;
5123 cmd->src = MSM_NAND_SFLASHC_STATUS;
5124 cmd->dst = msm_virt_to_dma(chip,
5125 &dma_buffer->data.sfstat[1+i]);
5126 cmd->len = 4;
5127 cmd++;
5128
5129 }
5130 }
5131
5132 /* Block on cmd ready and write CMD register */
5133 cmd->cmd = DST_CRCI_NAND_CMD;
5134 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[5]);
5135 cmd->dst = MSM_NAND_SFLASHC_CMD;
5136 cmd->len = 4;
5137 cmd++;
5138
5139 if ((ops->oobbuf) || (ops->mode == MTD_OOB_RAW)) {
5140
5141 /* Transfer user buf contents into nand ctlr buffer */
5142 if (ops->mode == MTD_OOB_AUTO) {
5143 cmd->cmd = 0;
5144 cmd->src = init_dma_addr;
5145 cmd->dst = MSM_NAND_FLASH_BUFFER;
5146 cmd->len = mtd->oobsize;
5147 cmd++;
5148 }
5149 if (ops->mode == MTD_OOB_PLACE) {
5150 cmd->cmd = 0;
5151 cmd->src = oob_dma_addr_curr;
5152 cmd->dst = MSM_NAND_FLASH_BUFFER;
5153 cmd->len = mtd->oobsize;
5154 oob_dma_addr_curr += mtd->oobsize;
5155 cmd++;
5156 }
5157 if (ops->mode == MTD_OOB_RAW) {
5158 cmd->cmd = 0;
5159 cmd->src = data_dma_addr_curr;
5160 cmd->dst = MSM_NAND_FLASH_BUFFER;
5161 cmd->len = mtd->oobsize;
5162 data_dma_addr_curr += mtd->oobsize;
5163 cmd++;
5164 }
5165 } else {
5166 cmd->cmd = 0;
5167 cmd->src = init_dma_addr;
5168 cmd->dst = MSM_NAND_FLASH_BUFFER;
5169 cmd->len = mtd->oobsize;
5170 cmd++;
5171 }
5172
5173 /* Write the MACRO1 register */
5174 cmd->cmd = 0;
5175 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.macro[4]);
5176 cmd->dst = MSM_NAND_MACRO1_REG;
5177 cmd->len = 4;
5178 cmd++;
5179
5180 /* Kick the execute command */
5181 cmd->cmd = 0;
5182 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5183 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5184 cmd->len = 4;
5185 cmd++;
5186
5187 /* Block on data ready, and read the status register */
5188 cmd->cmd = SRC_CRCI_NAND_DATA;
5189 cmd->src = MSM_NAND_SFLASHC_STATUS;
5190 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[5]);
5191 cmd->len = 4;
5192 cmd++;
5193
5194 /*********************************************************/
5195 /* Issuing write command */
5196 /*********************************************************/
5197
5198 /* Block on cmd ready and write CMD register */
5199 cmd->cmd = DST_CRCI_NAND_CMD;
5200 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[6]);
5201 cmd->dst = MSM_NAND_SFLASHC_CMD;
5202 cmd->len = 4;
5203 cmd++;
5204
5205 /* Kick the execute command */
5206 cmd->cmd = 0;
5207 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5208 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5209 cmd->len = 4;
5210 cmd++;
5211
5212 /* Block on data ready, and read the status register */
5213 cmd->cmd = SRC_CRCI_NAND_DATA;
5214 cmd->src = MSM_NAND_SFLASHC_STATUS;
5215 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[6]);
5216 cmd->len = 4;
5217 cmd++;
5218
5219 /*************************************************************/
5220 /* Wait for the interrupt from the Onenand device controller */
5221 /*************************************************************/
5222
5223 /* Block on cmd ready and write CMD register */
5224 cmd->cmd = DST_CRCI_NAND_CMD;
5225 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[7]);
5226 cmd->dst = MSM_NAND_SFLASHC_CMD;
5227 cmd->len = 4;
5228 cmd++;
5229
5230 /* Kick the execute command */
5231 cmd->cmd = 0;
5232 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5233 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5234 cmd->len = 4;
5235 cmd++;
5236
5237 /* Block on data ready, and read the status register */
5238 cmd->cmd = SRC_CRCI_NAND_DATA;
5239 cmd->src = MSM_NAND_SFLASHC_STATUS;
5240 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[7]);
5241 cmd->len = 4;
5242 cmd++;
5243
5244 /*************************************************************/
5245 /* Read necessary status registers from the onenand device */
5246 /*************************************************************/
5247
5248 /* Block on cmd ready and write CMD register */
5249 cmd->cmd = DST_CRCI_NAND_CMD;
5250 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[8]);
5251 cmd->dst = MSM_NAND_SFLASHC_CMD;
5252 cmd->len = 4;
5253 cmd++;
5254
5255 /* Kick the execute command */
5256 cmd->cmd = 0;
5257 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5258 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5259 cmd->len = 4;
5260 cmd++;
5261
5262 /* Block on data ready, and read the status register */
5263 cmd->cmd = SRC_CRCI_NAND_DATA;
5264 cmd->src = MSM_NAND_SFLASHC_STATUS;
5265 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[8]);
5266 cmd->len = 4;
5267 cmd++;
5268
5269 /* Read the GENP3 register */
5270 cmd->cmd = 0;
5271 cmd->src = MSM_NAND_GENP_REG3;
5272 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
5273 cmd->len = 4;
5274 cmd++;
5275
5276 /* Read the DEVCMD4 register */
5277 cmd->cmd = 0;
5278 cmd->src = MSM_NAND_DEV_CMD4;
5279 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5280 cmd->len = 4;
5281 cmd++;
5282
5283 /*************************************************************/
5284 /* Restore the necessary registers to proper values */
5285 /*************************************************************/
5286
5287 /* Block on cmd ready and write CMD register */
5288 cmd->cmd = DST_CRCI_NAND_CMD;
5289 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[9]);
5290 cmd->dst = MSM_NAND_SFLASHC_CMD;
5291 cmd->len = 4;
5292 cmd++;
5293
5294 /* Kick the execute command */
5295 cmd->cmd = 0;
5296 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5297 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5298 cmd->len = 4;
5299 cmd++;
5300
5301 /* Block on data ready, and read the status register */
5302 cmd->cmd = SRC_CRCI_NAND_DATA;
5303 cmd->src = MSM_NAND_SFLASHC_STATUS;
5304 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[9]);
5305 cmd->len = 4;
5306 cmd++;
5307
5308
5309 BUILD_BUG_ON(53 != ARRAY_SIZE(dma_buffer->cmd));
5310 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
5311 dma_buffer->cmd[0].cmd |= CMD_OCB;
5312 cmd[-1].cmd |= CMD_OCU | CMD_LC;
5313
5314 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
5315 >> 3) | CMD_PTR_LP;
5316
5317 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]5318 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]5319 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
5320 &dma_buffer->cmdptr)));
5321 mb();
5322
5323 ecc_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
5324 interrupt_status = (dma_buffer->data.data4 >> 0)&0x0000FFFF;
5325 controller_status = (dma_buffer->data.data4 >> 16)&0x0000FFFF;
5326
5327#if VERBOSE
5328 pr_info("\n%s: sflash status %x %x %x %x %x %x %x"
5329 " %x %x %x\n", __func__,
5330 dma_buffer->data.sfstat[0],
5331 dma_buffer->data.sfstat[1],
5332 dma_buffer->data.sfstat[2],
5333 dma_buffer->data.sfstat[3],
5334 dma_buffer->data.sfstat[4],
5335 dma_buffer->data.sfstat[5],
5336 dma_buffer->data.sfstat[6],
5337 dma_buffer->data.sfstat[7],
5338 dma_buffer->data.sfstat[8],
5339 dma_buffer->data.sfstat[9]);
5340
5341 pr_info("%s: controller_status = %x\n", __func__,
5342 controller_status);
5343 pr_info("%s: interrupt_status = %x\n", __func__,
5344 interrupt_status);
5345 pr_info("%s: ecc_status = %x\n", __func__,
5346 ecc_status);
5347#endif
5348 /* Check for errors, protection violations etc */
5349 if ((controller_status != 0)
5350 || (dma_buffer->data.sfstat[0] & 0x110)
5351 || (dma_buffer->data.sfstat[6] & 0x110)
5352 || (dma_buffer->data.sfstat[7] & 0x110)
5353 || (dma_buffer->data.sfstat[8] & 0x110)
5354 || (dma_buffer->data.sfstat[9] & 0x110)
5355 || ((dma_buffer->data.sfstat[1] & 0x110) &&
5356 (ops->datbuf))
5357 || ((dma_buffer->data.sfstat[2] & 0x110) &&
5358 (ops->datbuf))
5359 || ((dma_buffer->data.sfstat[3] & 0x110) &&
5360 (ops->datbuf))
5361 || ((dma_buffer->data.sfstat[4] & 0x110) &&
5362 (ops->datbuf))
5363 || ((dma_buffer->data.sfstat[5] & 0x110) &&
5364 ((ops->oobbuf)
5365 || (ops->mode == MTD_OOB_RAW)))) {
5366 pr_info("%s: ECC/MPU/OP error\n", __func__);
5367 err = -EIO;
5368 }
5369
5370 if (err)
5371 break;
5372 pages_written++;
5373 to_curr += mtd->writesize;
5374 }
5375
5376 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
5377
5378 dma_unmap_page(chip->dev, init_dma_addr, 64, DMA_TO_DEVICE);
5379
5380err_dma_map_initbuf_failed:
5381 if (ops->oobbuf) {
5382 dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen,
5383 DMA_TO_DEVICE);
5384 }
5385err_dma_map_oobbuf_failed:
5386 if (ops->datbuf) {
5387 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
5388 DMA_TO_DEVICE);
5389 }
5390
5391 if (err) {
5392 pr_err("%s: %llx %x %x failed\n", __func__, to_curr,
5393 ops->datbuf ? ops->len : 0, ops->ooblen);
5394 } else {
5395 ops->retlen = ops->oobretlen = 0;
5396 if (ops->datbuf != NULL) {
5397 if (ops->mode != MTD_OOB_RAW)
5398 ops->retlen = mtd->writesize * pages_written;
5399 else
5400 ops->retlen = (mtd->writesize + mtd->oobsize)
5401 * pages_written;
5402 }
5403 if (ops->oobbuf != NULL) {
5404 if (ops->mode == MTD_OOB_AUTO)
5405 ops->oobretlen = mtd->oobavail * pages_written;
5406 else
5407 ops->oobretlen = mtd->oobsize * pages_written;
5408 }
5409 }
5410
5411#if VERBOSE
5412 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
5413 __func__, err, ops->retlen, ops->oobretlen);
5414
5415 pr_info("================================================="
5416 "================\n");
5417#endif
5418 kfree(init_spare_bytes);
5419 return err;
5420}
5421
5422static int msm_onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
5423 size_t *retlen, const u_char *buf)
5424{
5425 int ret;
5426 struct mtd_oob_ops ops;
5427
5428 ops.mode = MTD_OOB_PLACE;
5429 ops.datbuf = (uint8_t *)buf;
5430 ops.len = len;
5431 ops.retlen = 0;
5432 ops.oobbuf = NULL;
5433 ops.ooblen = 0;
5434 ops.oobretlen = 0;
5435 ret = msm_onenand_write_oob(mtd, to, &ops);
5436 *retlen = ops.retlen;
5437
5438 return ret;
5439}
5440
5441static int msm_onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
5442{
5443 struct msm_nand_chip *chip = mtd->priv;
5444
5445 struct {
5446 dmov_s cmd[20];
5447 unsigned cmdptr;
5448 struct {
5449 uint32_t sfbcfg;
5450 uint32_t sfcmd[4];
5451 uint32_t sfexec;
5452 uint32_t sfstat[4];
5453 uint32_t addr0;
5454 uint32_t addr1;
5455 uint32_t addr2;
5456 uint32_t addr3;
5457 uint32_t addr4;
5458 uint32_t addr5;
5459 uint32_t addr6;
5460 uint32_t data0;
5461 uint32_t data1;
5462 uint32_t data2;
5463 uint32_t data3;
5464 uint32_t data4;
5465 uint32_t data5;
5466 uint32_t data6;
5467 } data;
5468 } *dma_buffer;
5469 dmov_s *cmd;
5470
5471 int err = 0;
5472
5473 uint16_t onenand_startaddr1;
5474 uint16_t onenand_startaddr8;
5475 uint16_t onenand_startaddr2;
5476 uint16_t onenand_startbuffer;
5477
5478 uint16_t controller_status;
5479 uint16_t interrupt_status;
5480 uint16_t ecc_status;
5481
5482 uint64_t temp;
5483
5484#if VERBOSE
5485 pr_info("================================================="
5486 "================\n");
5487 pr_info("%s: addr 0x%llx len 0x%llx\n",
5488 __func__, instr->addr, instr->len);
5489#endif
5490 if (instr->addr & (mtd->erasesize - 1)) {
5491 pr_err("%s: Unsupported erase address, 0x%llx\n",
5492 __func__, instr->addr);
5493 return -EINVAL;
5494 }
5495 if (instr->len != mtd->erasesize) {
5496 pr_err("%s: Unsupported erase len, %lld\n",
5497 __func__, instr->len);
5498 return -EINVAL;
5499 }
5500
5501 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
5502 (chip, sizeof(*dma_buffer))));
5503
5504 cmd = dma_buffer->cmd;
5505
5506 temp = instr->addr;
5507
5508 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
5509 && (temp >= (mtd->size>>1))) { /* DDP Device */
5510 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
5511 (((uint32_t)(temp-(mtd->size>>1))
5512 / mtd->erasesize));
5513 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
5514 } else {
5515 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
5516 ((uint32_t)temp / mtd->erasesize) ;
5517 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
5518 }
5519
5520 onenand_startaddr8 = 0x0000;
5521 onenand_startbuffer = DATARAM0_0 << 8;
5522
5523 dma_buffer->data.sfbcfg = SFLASH_BCFG |
5524 (nand_sfcmd_mode ? 0 : (1 << 24));
5525 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
5526 MSM_NAND_SFCMD_CMDXS,
5527 nand_sfcmd_mode,
5528 MSM_NAND_SFCMD_REGWR);
5529 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
5530 MSM_NAND_SFCMD_CMDXS,
5531 nand_sfcmd_mode,
5532 MSM_NAND_SFCMD_INTHI);
5533 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
5534 MSM_NAND_SFCMD_DATXS,
5535 nand_sfcmd_mode,
5536 MSM_NAND_SFCMD_REGRD);
5537 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
5538 MSM_NAND_SFCMD_CMDXS,
5539 nand_sfcmd_mode,
5540 MSM_NAND_SFCMD_REGWR);
5541 dma_buffer->data.sfexec = 1;
5542 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
5543 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
5544 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
5545 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
5546 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
5547 (ONENAND_SYSTEM_CONFIG_1);
5548 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
5549 (ONENAND_START_ADDRESS_1);
5550 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
5551 (ONENAND_START_ADDRESS_2);
5552 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
5553 (ONENAND_COMMAND);
5554 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
5555 (ONENAND_INTERRUPT_STATUS);
5556 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
5557 (ONENAND_SYSTEM_CONFIG_1);
5558 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
5559 (ONENAND_START_ADDRESS_1);
5560 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
5561 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5562 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
5563 (onenand_startaddr1);
5564 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
5565 (onenand_startaddr2);
5566 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
5567 (ONENAND_CMDERAS);
5568 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
5569 (CLEAN_DATA_16);
5570 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
5571 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5572 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
5573 (ONENAND_STARTADDR1_RES);
5574
5575 /***************************************************************/
5576 /* Write the necessary address registers in the onenand device */
5577 /***************************************************************/
5578
5579 /* Enable and configure the SFlash controller */
5580 cmd->cmd = 0;
5581 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
5582 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
5583 cmd->len = 4;
5584 cmd++;
5585
5586 /* Block on cmd ready and write CMD register */
5587 cmd->cmd = DST_CRCI_NAND_CMD;
5588 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
5589 cmd->dst = MSM_NAND_SFLASHC_CMD;
5590 cmd->len = 4;
5591 cmd++;
5592
5593 /* Write the ADDR0 and ADDR1 registers */
5594 cmd->cmd = 0;
5595 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
5596 cmd->dst = MSM_NAND_ADDR0;
5597 cmd->len = 8;
5598 cmd++;
5599
5600 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
5601 cmd->cmd = 0;
5602 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
5603 cmd->dst = MSM_NAND_ADDR2;
5604 cmd->len = 16;
5605 cmd++;
5606
5607 /* Write the ADDR6 registers */
5608 cmd->cmd = 0;
5609 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
5610 cmd->dst = MSM_NAND_ADDR6;
5611 cmd->len = 4;
5612 cmd++;
5613
5614 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
5615 cmd->cmd = 0;
5616 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
5617 cmd->dst = MSM_NAND_GENP_REG0;
5618 cmd->len = 16;
5619 cmd++;
5620
5621 /* Write the FLASH_DEV_CMD4,5,6 registers */
5622 cmd->cmd = 0;
5623 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5624 cmd->dst = MSM_NAND_DEV_CMD4;
5625 cmd->len = 12;
5626 cmd++;
5627
5628 /* Kick the execute command */
5629 cmd->cmd = 0;
5630 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5631 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5632 cmd->len = 4;
5633 cmd++;
5634
5635 /* Block on data ready, and read the status register */
5636 cmd->cmd = SRC_CRCI_NAND_DATA;
5637 cmd->src = MSM_NAND_SFLASHC_STATUS;
5638 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
5639 cmd->len = 4;
5640 cmd++;
5641
5642 /***************************************************************/
5643 /* Wait for the interrupt from the Onenand device controller */
5644 /***************************************************************/
5645
5646 /* Block on cmd ready and write CMD register */
5647 cmd->cmd = DST_CRCI_NAND_CMD;
5648 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
5649 cmd->dst = MSM_NAND_SFLASHC_CMD;
5650 cmd->len = 4;
5651 cmd++;
5652
5653 /* Kick the execute command */
5654 cmd->cmd = 0;
5655 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5656 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5657 cmd->len = 4;
5658 cmd++;
5659
5660 /* Block on data ready, and read the status register */
5661 cmd->cmd = SRC_CRCI_NAND_DATA;
5662 cmd->src = MSM_NAND_SFLASHC_STATUS;
5663 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
5664 cmd->len = 4;
5665 cmd++;
5666
5667 /***************************************************************/
5668 /* Read the necessary status registers from the onenand device */
5669 /***************************************************************/
5670
5671 /* Block on cmd ready and write CMD register */
5672 cmd->cmd = DST_CRCI_NAND_CMD;
5673 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
5674 cmd->dst = MSM_NAND_SFLASHC_CMD;
5675 cmd->len = 4;
5676 cmd++;
5677
5678 /* Kick the execute command */
5679 cmd->cmd = 0;
5680 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5681 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5682 cmd->len = 4;
5683 cmd++;
5684
5685 /* Block on data ready, and read the status register */
5686 cmd->cmd = SRC_CRCI_NAND_DATA;
5687 cmd->src = MSM_NAND_SFLASHC_STATUS;
5688 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
5689 cmd->len = 4;
5690 cmd++;
5691
5692 /* Read the GENP3 register */
5693 cmd->cmd = 0;
5694 cmd->src = MSM_NAND_GENP_REG3;
5695 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
5696 cmd->len = 4;
5697 cmd++;
5698
5699 /* Read the DEVCMD4 register */
5700 cmd->cmd = 0;
5701 cmd->src = MSM_NAND_DEV_CMD4;
5702 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5703 cmd->len = 4;
5704 cmd++;
5705
5706 /***************************************************************/
5707 /* Restore the necessary registers to proper values */
5708 /***************************************************************/
5709
5710 /* Block on cmd ready and write CMD register */
5711 cmd->cmd = DST_CRCI_NAND_CMD;
5712 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
5713 cmd->dst = MSM_NAND_SFLASHC_CMD;
5714 cmd->len = 4;
5715 cmd++;
5716
5717 /* Kick the execute command */
5718 cmd->cmd = 0;
5719 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5720 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5721 cmd->len = 4;
5722 cmd++;
5723
5724 /* Block on data ready, and read the status register */
5725 cmd->cmd = SRC_CRCI_NAND_DATA;
5726 cmd->src = MSM_NAND_SFLASHC_STATUS;
5727 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
5728 cmd->len = 4;
5729 cmd++;
5730
5731
5732 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
5733 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
5734 dma_buffer->cmd[0].cmd |= CMD_OCB;
5735 cmd[-1].cmd |= CMD_OCU | CMD_LC;
5736
5737 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
5738 >> 3) | CMD_PTR_LP;
5739
5740 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]5741 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]5742 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
5743 &dma_buffer->cmdptr)));
5744 mb();
5745
5746 ecc_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
5747 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
5748 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
5749
5750#if VERBOSE
5751 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
5752 dma_buffer->data.sfstat[0],
5753 dma_buffer->data.sfstat[1],
5754 dma_buffer->data.sfstat[2],
5755 dma_buffer->data.sfstat[3]);
5756
5757 pr_info("%s: controller_status = %x\n", __func__,
5758 controller_status);
5759 pr_info("%s: interrupt_status = %x\n", __func__,
5760 interrupt_status);
5761 pr_info("%s: ecc_status = %x\n", __func__,
5762 ecc_status);
5763#endif
5764 /* Check for errors, protection violations etc */
5765 if ((controller_status != 0)
5766 || (dma_buffer->data.sfstat[0] & 0x110)
5767 || (dma_buffer->data.sfstat[1] & 0x110)
5768 || (dma_buffer->data.sfstat[2] & 0x110)
5769 || (dma_buffer->data.sfstat[3] & 0x110)) {
5770 pr_err("%s: ECC/MPU/OP error\n", __func__);
5771 err = -EIO;
5772 }
5773
5774 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
5775
5776 if (err) {
5777 pr_err("%s: Erase failed, 0x%llx\n", __func__,
5778 instr->addr);
5779 instr->fail_addr = instr->addr;
5780 instr->state = MTD_ERASE_FAILED;
5781 } else {
5782 instr->state = MTD_ERASE_DONE;
5783 instr->fail_addr = 0xffffffff;
5784 mtd_erase_callback(instr);
5785 }
5786
5787#if VERBOSE
5788 pr_info("\n%s: ret %d\n", __func__, err);
5789 pr_info("===================================================="
5790 "=============\n");
5791#endif
5792 return err;
5793}
5794
5795static int msm_onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
5796{
5797 struct mtd_oob_ops ops;
5798 int rval, i;
5799 int ret = 0;
5800 uint8_t *buffer;
5801 uint8_t *oobptr;
5802
5803 if ((ofs > mtd->size) || (ofs & (mtd->erasesize - 1))) {
5804 pr_err("%s: unsupported block address, 0x%x\n",
5805 __func__, (uint32_t)ofs);
5806 return -EINVAL;
5807 }
5808
5809 buffer = kmalloc(2112, GFP_KERNEL|GFP_DMA);
5810 if (buffer == 0) {
5811 pr_err("%s: Could not kmalloc for buffer\n",
5812 __func__);
5813 return -ENOMEM;
5814 }
5815
5816 memset(buffer, 0x00, 2112);
5817 oobptr = &(buffer[2048]);
5818
5819 ops.mode = MTD_OOB_RAW;
5820 ops.len = 2112;
5821 ops.retlen = 0;
5822 ops.ooblen = 0;
5823 ops.oobretlen = 0;
5824 ops.ooboffs = 0;
5825 ops.datbuf = buffer;
5826 ops.oobbuf = NULL;
5827
5828 for (i = 0; i < 2; i++) {
5829 ofs = ofs + i*mtd->writesize;
5830 rval = msm_onenand_read_oob(mtd, ofs, &ops);
5831 if (rval) {
5832 pr_err("%s: Error in reading bad blk info\n",
5833 __func__);
5834 ret = rval;
5835 break;
5836 }
5837 if ((oobptr[0] != 0xFF) || (oobptr[1] != 0xFF) ||
5838 (oobptr[16] != 0xFF) || (oobptr[17] != 0xFF) ||
5839 (oobptr[32] != 0xFF) || (oobptr[33] != 0xFF) ||
5840 (oobptr[48] != 0xFF) || (oobptr[49] != 0xFF)
5841 ) {
5842 ret = 1;
5843 break;
5844 }
5845 }
5846
5847 kfree(buffer);
5848
5849#if VERBOSE
5850 if (ret == 1)
5851 pr_info("%s : Block containing 0x%x is bad\n",
5852 __func__, (unsigned int)ofs);
5853#endif
5854 return ret;
5855}
5856
5857static int msm_onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
5858{
5859 struct mtd_oob_ops ops;
5860 int rval, i;
5861 int ret = 0;
5862 uint8_t *buffer;
5863
5864 if ((ofs > mtd->size) || (ofs & (mtd->erasesize - 1))) {
5865 pr_err("%s: unsupported block address, 0x%x\n",
5866 __func__, (uint32_t)ofs);
5867 return -EINVAL;
5868 }
5869
5870 buffer = page_address(ZERO_PAGE());
5871
5872 ops.mode = MTD_OOB_RAW;
5873 ops.len = 2112;
5874 ops.retlen = 0;
5875 ops.ooblen = 0;
5876 ops.oobretlen = 0;
5877 ops.ooboffs = 0;
5878 ops.datbuf = buffer;
5879 ops.oobbuf = NULL;
5880
5881 for (i = 0; i < 2; i++) {
5882 ofs = ofs + i*mtd->writesize;
5883 rval = msm_onenand_write_oob(mtd, ofs, &ops);
5884 if (rval) {
5885 pr_err("%s: Error in writing bad blk info\n",
5886 __func__);
5887 ret = rval;
5888 break;
5889 }
5890 }
5891
5892 return ret;
5893}
5894
5895static int msm_onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
5896{
5897 struct msm_nand_chip *chip = mtd->priv;
5898
5899 struct {
5900 dmov_s cmd[20];
5901 unsigned cmdptr;
5902 struct {
5903 uint32_t sfbcfg;
5904 uint32_t sfcmd[4];
5905 uint32_t sfexec;
5906 uint32_t sfstat[4];
5907 uint32_t addr0;
5908 uint32_t addr1;
5909 uint32_t addr2;
5910 uint32_t addr3;
5911 uint32_t addr4;
5912 uint32_t addr5;
5913 uint32_t addr6;
5914 uint32_t data0;
5915 uint32_t data1;
5916 uint32_t data2;
5917 uint32_t data3;
5918 uint32_t data4;
5919 uint32_t data5;
5920 uint32_t data6;
5921 } data;
5922 } *dma_buffer;
5923 dmov_s *cmd;
5924
5925 int err = 0;
5926
5927 uint16_t onenand_startaddr1;
5928 uint16_t onenand_startaddr8;
5929 uint16_t onenand_startaddr2;
5930 uint16_t onenand_startblock;
5931
5932 uint16_t controller_status;
5933 uint16_t interrupt_status;
5934 uint16_t write_prot_status;
5935
5936 uint64_t start_ofs;
5937
5938#if VERBOSE
5939 pr_info("===================================================="
5940 "=============\n");
5941 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
5942#endif
5943 /* 'ofs' & 'len' should align to block size */
5944 if (ofs&(mtd->erasesize - 1)) {
5945 pr_err("%s: Unsupported ofs address, 0x%llx\n",
5946 __func__, ofs);
5947 return -EINVAL;
5948 }
5949
5950 if (len&(mtd->erasesize - 1)) {
5951 pr_err("%s: Unsupported len, %lld\n",
5952 __func__, len);
5953 return -EINVAL;
5954 }
5955
5956 if (ofs+len > mtd->size) {
5957 pr_err("%s: Maximum chip size exceeded\n", __func__);
5958 return -EINVAL;
5959 }
5960
5961 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
5962 (chip, sizeof(*dma_buffer))));
5963
5964 for (start_ofs = ofs; ofs < start_ofs+len; ofs = ofs+mtd->erasesize) {
5965#if VERBOSE
5966 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
5967#endif
5968
5969 cmd = dma_buffer->cmd;
5970 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
5971 && (ofs >= (mtd->size>>1))) { /* DDP Device */
5972 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
5973 (((uint32_t)(ofs - (mtd->size>>1))
5974 / mtd->erasesize));
5975 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
5976 onenand_startblock = ((uint32_t)(ofs - (mtd->size>>1))
5977 / mtd->erasesize);
5978 } else {
5979 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
5980 ((uint32_t)ofs / mtd->erasesize) ;
5981 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
5982 onenand_startblock = ((uint32_t)ofs
5983 / mtd->erasesize);
5984 }
5985
5986 onenand_startaddr8 = 0x0000;
5987 dma_buffer->data.sfbcfg = SFLASH_BCFG |
5988 (nand_sfcmd_mode ? 0 : (1 << 24));
5989 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
5990 MSM_NAND_SFCMD_CMDXS,
5991 nand_sfcmd_mode,
5992 MSM_NAND_SFCMD_REGWR);
5993 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
5994 MSM_NAND_SFCMD_CMDXS,
5995 nand_sfcmd_mode,
5996 MSM_NAND_SFCMD_INTHI);
5997 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
5998 MSM_NAND_SFCMD_DATXS,
5999 nand_sfcmd_mode,
6000 MSM_NAND_SFCMD_REGRD);
6001 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
6002 MSM_NAND_SFCMD_CMDXS,
6003 nand_sfcmd_mode,
6004 MSM_NAND_SFCMD_REGWR);
6005 dma_buffer->data.sfexec = 1;
6006 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
6007 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
6008 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
6009 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
6010 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
6011 (ONENAND_SYSTEM_CONFIG_1);
6012 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
6013 (ONENAND_START_ADDRESS_1);
6014 dma_buffer->data.addr2 = (ONENAND_START_BLOCK_ADDRESS << 16) |
6015 (ONENAND_START_ADDRESS_2);
6016 dma_buffer->data.addr3 = (ONENAND_WRITE_PROT_STATUS << 16) |
6017 (ONENAND_COMMAND);
6018 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
6019 (ONENAND_INTERRUPT_STATUS);
6020 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
6021 (ONENAND_SYSTEM_CONFIG_1);
6022 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
6023 (ONENAND_START_ADDRESS_1);
6024 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
6025 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6026 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
6027 (onenand_startaddr1);
6028 dma_buffer->data.data2 = (onenand_startblock << 16) |
6029 (onenand_startaddr2);
6030 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
6031 (ONENAND_CMD_UNLOCK);
6032 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
6033 (CLEAN_DATA_16);
6034 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
6035 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6036 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
6037 (ONENAND_STARTADDR1_RES);
6038
6039 /*************************************************************/
6040 /* Write the necessary address reg in the onenand device */
6041 /*************************************************************/
6042
6043 /* Enable and configure the SFlash controller */
6044 cmd->cmd = 0;
6045 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
6046 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
6047 cmd->len = 4;
6048 cmd++;
6049
6050 /* Block on cmd ready and write CMD register */
6051 cmd->cmd = DST_CRCI_NAND_CMD;
6052 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
6053 cmd->dst = MSM_NAND_SFLASHC_CMD;
6054 cmd->len = 4;
6055 cmd++;
6056
6057 /* Write the ADDR0 and ADDR1 registers */
6058 cmd->cmd = 0;
6059 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
6060 cmd->dst = MSM_NAND_ADDR0;
6061 cmd->len = 8;
6062 cmd++;
6063
6064 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
6065 cmd->cmd = 0;
6066 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
6067 cmd->dst = MSM_NAND_ADDR2;
6068 cmd->len = 16;
6069 cmd++;
6070
6071 /* Write the ADDR6 registers */
6072 cmd->cmd = 0;
6073 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
6074 cmd->dst = MSM_NAND_ADDR6;
6075 cmd->len = 4;
6076 cmd++;
6077
6078 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
6079 cmd->cmd = 0;
6080 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
6081 cmd->dst = MSM_NAND_GENP_REG0;
6082 cmd->len = 16;
6083 cmd++;
6084
6085 /* Write the FLASH_DEV_CMD4,5,6 registers */
6086 cmd->cmd = 0;
6087 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6088 cmd->dst = MSM_NAND_DEV_CMD4;
6089 cmd->len = 12;
6090 cmd++;
6091
6092 /* Kick the execute command */
6093 cmd->cmd = 0;
6094 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6095 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6096 cmd->len = 4;
6097 cmd++;
6098
6099 /* Block on data ready, and read the status register */
6100 cmd->cmd = SRC_CRCI_NAND_DATA;
6101 cmd->src = MSM_NAND_SFLASHC_STATUS;
6102 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
6103 cmd->len = 4;
6104 cmd++;
6105
6106 /*************************************************************/
6107 /* Wait for the interrupt from the Onenand device controller */
6108 /*************************************************************/
6109
6110 /* Block on cmd ready and write CMD register */
6111 cmd->cmd = DST_CRCI_NAND_CMD;
6112 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
6113 cmd->dst = MSM_NAND_SFLASHC_CMD;
6114 cmd->len = 4;
6115 cmd++;
6116
6117 /* Kick the execute command */
6118 cmd->cmd = 0;
6119 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6120 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6121 cmd->len = 4;
6122 cmd++;
6123
6124 /* Block on data ready, and read the status register */
6125 cmd->cmd = SRC_CRCI_NAND_DATA;
6126 cmd->src = MSM_NAND_SFLASHC_STATUS;
6127 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
6128 cmd->len = 4;
6129 cmd++;
6130
6131 /*********************************************************/
6132 /* Read the necessary status reg from the onenand device */
6133 /*********************************************************/
6134
6135 /* Block on cmd ready and write CMD register */
6136 cmd->cmd = DST_CRCI_NAND_CMD;
6137 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
6138 cmd->dst = MSM_NAND_SFLASHC_CMD;
6139 cmd->len = 4;
6140 cmd++;
6141
6142 /* Kick the execute command */
6143 cmd->cmd = 0;
6144 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6145 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6146 cmd->len = 4;
6147 cmd++;
6148
6149 /* Block on data ready, and read the status register */
6150 cmd->cmd = SRC_CRCI_NAND_DATA;
6151 cmd->src = MSM_NAND_SFLASHC_STATUS;
6152 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
6153 cmd->len = 4;
6154 cmd++;
6155
6156 /* Read the GENP3 register */
6157 cmd->cmd = 0;
6158 cmd->src = MSM_NAND_GENP_REG3;
6159 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
6160 cmd->len = 4;
6161 cmd++;
6162
6163 /* Read the DEVCMD4 register */
6164 cmd->cmd = 0;
6165 cmd->src = MSM_NAND_DEV_CMD4;
6166 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6167 cmd->len = 4;
6168 cmd++;
6169
6170 /************************************************************/
6171 /* Restore the necessary registers to proper values */
6172 /************************************************************/
6173
6174 /* Block on cmd ready and write CMD register */
6175 cmd->cmd = DST_CRCI_NAND_CMD;
6176 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
6177 cmd->dst = MSM_NAND_SFLASHC_CMD;
6178 cmd->len = 4;
6179 cmd++;
6180
6181 /* Kick the execute command */
6182 cmd->cmd = 0;
6183 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6184 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6185 cmd->len = 4;
6186 cmd++;
6187
6188 /* Block on data ready, and read the status register */
6189 cmd->cmd = SRC_CRCI_NAND_DATA;
6190 cmd->src = MSM_NAND_SFLASHC_STATUS;
6191 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
6192 cmd->len = 4;
6193 cmd++;
6194
6195
6196 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
6197 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6198 dma_buffer->cmd[0].cmd |= CMD_OCB;
6199 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6200
6201 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
6202 >> 3) | CMD_PTR_LP;
6203
6204 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]6205 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6206 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6207 &dma_buffer->cmdptr)));
6208 mb();
6209
6210 write_prot_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
6211 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
6212 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
6213
6214#if VERBOSE
6215 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
6216 dma_buffer->data.sfstat[0],
6217 dma_buffer->data.sfstat[1],
6218 dma_buffer->data.sfstat[2],
6219 dma_buffer->data.sfstat[3]);
6220
6221 pr_info("%s: controller_status = %x\n", __func__,
6222 controller_status);
6223 pr_info("%s: interrupt_status = %x\n", __func__,
6224 interrupt_status);
6225 pr_info("%s: write_prot_status = %x\n", __func__,
6226 write_prot_status);
6227#endif
6228 /* Check for errors, protection violations etc */
6229 if ((controller_status != 0)
6230 || (dma_buffer->data.sfstat[0] & 0x110)
6231 || (dma_buffer->data.sfstat[1] & 0x110)
6232 || (dma_buffer->data.sfstat[2] & 0x110)
6233 || (dma_buffer->data.sfstat[3] & 0x110)) {
6234 pr_err("%s: ECC/MPU/OP error\n", __func__);
6235 err = -EIO;
6236 }
6237
6238 if (!(write_prot_status & ONENAND_WP_US)) {
6239 pr_err("%s: Unexpected status ofs = 0x%llx,"
6240 "wp_status = %x\n",
6241 __func__, ofs, write_prot_status);
6242 err = -EIO;
6243 }
6244
6245 if (err)
6246 break;
6247 }
6248
6249 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6250
6251#if VERBOSE
6252 pr_info("\n%s: ret %d\n", __func__, err);
6253 pr_info("===================================================="
6254 "=============\n");
6255#endif
6256 return err;
6257}
6258
6259static int msm_onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
6260{
6261 struct msm_nand_chip *chip = mtd->priv;
6262
6263 struct {
6264 dmov_s cmd[20];
6265 unsigned cmdptr;
6266 struct {
6267 uint32_t sfbcfg;
6268 uint32_t sfcmd[4];
6269 uint32_t sfexec;
6270 uint32_t sfstat[4];
6271 uint32_t addr0;
6272 uint32_t addr1;
6273 uint32_t addr2;
6274 uint32_t addr3;
6275 uint32_t addr4;
6276 uint32_t addr5;
6277 uint32_t addr6;
6278 uint32_t data0;
6279 uint32_t data1;
6280 uint32_t data2;
6281 uint32_t data3;
6282 uint32_t data4;
6283 uint32_t data5;
6284 uint32_t data6;
6285 } data;
6286 } *dma_buffer;
6287 dmov_s *cmd;
6288
6289 int err = 0;
6290
6291 uint16_t onenand_startaddr1;
6292 uint16_t onenand_startaddr8;
6293 uint16_t onenand_startaddr2;
6294 uint16_t onenand_startblock;
6295
6296 uint16_t controller_status;
6297 uint16_t interrupt_status;
6298 uint16_t write_prot_status;
6299
6300 uint64_t start_ofs;
6301
6302#if VERBOSE
6303 pr_info("===================================================="
6304 "=============\n");
6305 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
6306#endif
6307 /* 'ofs' & 'len' should align to block size */
6308 if (ofs&(mtd->erasesize - 1)) {
6309 pr_err("%s: Unsupported ofs address, 0x%llx\n",
6310 __func__, ofs);
6311 return -EINVAL;
6312 }
6313
6314 if (len&(mtd->erasesize - 1)) {
6315 pr_err("%s: Unsupported len, %lld\n",
6316 __func__, len);
6317 return -EINVAL;
6318 }
6319
6320 if (ofs+len > mtd->size) {
6321 pr_err("%s: Maximum chip size exceeded\n", __func__);
6322 return -EINVAL;
6323 }
6324
6325 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
6326 (chip, sizeof(*dma_buffer))));
6327
6328 for (start_ofs = ofs; ofs < start_ofs+len; ofs = ofs+mtd->erasesize) {
6329#if VERBOSE
6330 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
6331#endif
6332
6333 cmd = dma_buffer->cmd;
6334 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
6335 && (ofs >= (mtd->size>>1))) { /* DDP Device */
6336 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
6337 (((uint32_t)(ofs - (mtd->size>>1))
6338 / mtd->erasesize));
6339 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
6340 onenand_startblock = ((uint32_t)(ofs - (mtd->size>>1))
6341 / mtd->erasesize);
6342 } else {
6343 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
6344 ((uint32_t)ofs / mtd->erasesize) ;
6345 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
6346 onenand_startblock = ((uint32_t)ofs
6347 / mtd->erasesize);
6348 }
6349
6350 onenand_startaddr8 = 0x0000;
6351 dma_buffer->data.sfbcfg = SFLASH_BCFG |
6352 (nand_sfcmd_mode ? 0 : (1 << 24));
6353 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
6354 MSM_NAND_SFCMD_CMDXS,
6355 nand_sfcmd_mode,
6356 MSM_NAND_SFCMD_REGWR);
6357 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
6358 MSM_NAND_SFCMD_CMDXS,
6359 nand_sfcmd_mode,
6360 MSM_NAND_SFCMD_INTHI);
6361 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
6362 MSM_NAND_SFCMD_DATXS,
6363 nand_sfcmd_mode,
6364 MSM_NAND_SFCMD_REGRD);
6365 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
6366 MSM_NAND_SFCMD_CMDXS,
6367 nand_sfcmd_mode,
6368 MSM_NAND_SFCMD_REGWR);
6369 dma_buffer->data.sfexec = 1;
6370 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
6371 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
6372 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
6373 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
6374 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
6375 (ONENAND_SYSTEM_CONFIG_1);
6376 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
6377 (ONENAND_START_ADDRESS_1);
6378 dma_buffer->data.addr2 = (ONENAND_START_BLOCK_ADDRESS << 16) |
6379 (ONENAND_START_ADDRESS_2);
6380 dma_buffer->data.addr3 = (ONENAND_WRITE_PROT_STATUS << 16) |
6381 (ONENAND_COMMAND);
6382 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
6383 (ONENAND_INTERRUPT_STATUS);
6384 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
6385 (ONENAND_SYSTEM_CONFIG_1);
6386 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
6387 (ONENAND_START_ADDRESS_1);
6388 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
6389 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6390 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
6391 (onenand_startaddr1);
6392 dma_buffer->data.data2 = (onenand_startblock << 16) |
6393 (onenand_startaddr2);
6394 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
6395 (ONENAND_CMD_LOCK);
6396 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
6397 (CLEAN_DATA_16);
6398 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
6399 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6400 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
6401 (ONENAND_STARTADDR1_RES);
6402
6403 /*************************************************************/
6404 /* Write the necessary address reg in the onenand device */
6405 /*************************************************************/
6406
6407 /* Enable and configure the SFlash controller */
6408 cmd->cmd = 0;
6409 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
6410 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
6411 cmd->len = 4;
6412 cmd++;
6413
6414 /* Block on cmd ready and write CMD register */
6415 cmd->cmd = DST_CRCI_NAND_CMD;
6416 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
6417 cmd->dst = MSM_NAND_SFLASHC_CMD;
6418 cmd->len = 4;
6419 cmd++;
6420
6421 /* Write the ADDR0 and ADDR1 registers */
6422 cmd->cmd = 0;
6423 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
6424 cmd->dst = MSM_NAND_ADDR0;
6425 cmd->len = 8;
6426 cmd++;
6427
6428 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
6429 cmd->cmd = 0;
6430 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
6431 cmd->dst = MSM_NAND_ADDR2;
6432 cmd->len = 16;
6433 cmd++;
6434
6435 /* Write the ADDR6 registers */
6436 cmd->cmd = 0;
6437 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
6438 cmd->dst = MSM_NAND_ADDR6;
6439 cmd->len = 4;
6440 cmd++;
6441
6442 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
6443 cmd->cmd = 0;
6444 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
6445 cmd->dst = MSM_NAND_GENP_REG0;
6446 cmd->len = 16;
6447 cmd++;
6448
6449 /* Write the FLASH_DEV_CMD4,5,6 registers */
6450 cmd->cmd = 0;
6451 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6452 cmd->dst = MSM_NAND_DEV_CMD4;
6453 cmd->len = 12;
6454 cmd++;
6455
6456 /* Kick the execute command */
6457 cmd->cmd = 0;
6458 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6459 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6460 cmd->len = 4;
6461 cmd++;
6462
6463 /* Block on data ready, and read the status register */
6464 cmd->cmd = SRC_CRCI_NAND_DATA;
6465 cmd->src = MSM_NAND_SFLASHC_STATUS;
6466 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
6467 cmd->len = 4;
6468 cmd++;
6469
6470 /*************************************************************/
6471 /* Wait for the interrupt from the Onenand device controller */
6472 /*************************************************************/
6473
6474 /* Block on cmd ready and write CMD register */
6475 cmd->cmd = DST_CRCI_NAND_CMD;
6476 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
6477 cmd->dst = MSM_NAND_SFLASHC_CMD;
6478 cmd->len = 4;
6479 cmd++;
6480
6481 /* Kick the execute command */
6482 cmd->cmd = 0;
6483 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6484 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6485 cmd->len = 4;
6486 cmd++;
6487
6488 /* Block on data ready, and read the status register */
6489 cmd->cmd = SRC_CRCI_NAND_DATA;
6490 cmd->src = MSM_NAND_SFLASHC_STATUS;
6491 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
6492 cmd->len = 4;
6493 cmd++;
6494
6495 /*********************************************************/
6496 /* Read the necessary status reg from the onenand device */
6497 /*********************************************************/
6498
6499 /* Block on cmd ready and write CMD register */
6500 cmd->cmd = DST_CRCI_NAND_CMD;
6501 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
6502 cmd->dst = MSM_NAND_SFLASHC_CMD;
6503 cmd->len = 4;
6504 cmd++;
6505
6506 /* Kick the execute command */
6507 cmd->cmd = 0;
6508 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6509 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6510 cmd->len = 4;
6511 cmd++;
6512
6513 /* Block on data ready, and read the status register */
6514 cmd->cmd = SRC_CRCI_NAND_DATA;
6515 cmd->src = MSM_NAND_SFLASHC_STATUS;
6516 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
6517 cmd->len = 4;
6518 cmd++;
6519
6520 /* Read the GENP3 register */
6521 cmd->cmd = 0;
6522 cmd->src = MSM_NAND_GENP_REG3;
6523 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
6524 cmd->len = 4;
6525 cmd++;
6526
6527 /* Read the DEVCMD4 register */
6528 cmd->cmd = 0;
6529 cmd->src = MSM_NAND_DEV_CMD4;
6530 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6531 cmd->len = 4;
6532 cmd++;
6533
6534 /************************************************************/
6535 /* Restore the necessary registers to proper values */
6536 /************************************************************/
6537
6538 /* Block on cmd ready and write CMD register */
6539 cmd->cmd = DST_CRCI_NAND_CMD;
6540 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
6541 cmd->dst = MSM_NAND_SFLASHC_CMD;
6542 cmd->len = 4;
6543 cmd++;
6544
6545 /* Kick the execute command */
6546 cmd->cmd = 0;
6547 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6548 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6549 cmd->len = 4;
6550 cmd++;
6551
6552 /* Block on data ready, and read the status register */
6553 cmd->cmd = SRC_CRCI_NAND_DATA;
6554 cmd->src = MSM_NAND_SFLASHC_STATUS;
6555 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
6556 cmd->len = 4;
6557 cmd++;
6558
6559
6560 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
6561 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6562 dma_buffer->cmd[0].cmd |= CMD_OCB;
6563 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6564
6565 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
6566 >> 3) | CMD_PTR_LP;
6567
6568 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]6569 msm_dmov_exec_cmd(chip->dma_channel,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6570 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6571 &dma_buffer->cmdptr)));
6572 mb();
6573
6574 write_prot_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
6575 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
6576 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
6577
6578#if VERBOSE
6579 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
6580 dma_buffer->data.sfstat[0],
6581 dma_buffer->data.sfstat[1],
6582 dma_buffer->data.sfstat[2],
6583 dma_buffer->data.sfstat[3]);
6584
6585 pr_info("%s: controller_status = %x\n", __func__,
6586 controller_status);
6587 pr_info("%s: interrupt_status = %x\n", __func__,
6588 interrupt_status);
6589 pr_info("%s: write_prot_status = %x\n", __func__,
6590 write_prot_status);
6591#endif
6592 /* Check for errors, protection violations etc */
6593 if ((controller_status != 0)
6594 || (dma_buffer->data.sfstat[0] & 0x110)
6595 || (dma_buffer->data.sfstat[1] & 0x110)
6596 || (dma_buffer->data.sfstat[2] & 0x110)
6597 || (dma_buffer->data.sfstat[3] & 0x110)) {
6598 pr_err("%s: ECC/MPU/OP error\n", __func__);
6599 err = -EIO;
6600 }
6601
6602 if (!(write_prot_status & ONENAND_WP_LS)) {
6603 pr_err("%s: Unexpected status ofs = 0x%llx,"
6604 "wp_status = %x\n",
6605 __func__, ofs, write_prot_status);
6606 err = -EIO;
6607 }
6608
6609 if (err)
6610 break;
6611 }
6612
6613 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6614
6615#if VERBOSE
6616 pr_info("\n%s: ret %d\n", __func__, err);
6617 pr_info("===================================================="
6618 "=============\n");
6619#endif
6620 return err;
6621}
6622
6623static int msm_onenand_suspend(struct mtd_info *mtd)
6624{
6625 return 0;
6626}
6627
6628static void msm_onenand_resume(struct mtd_info *mtd)
6629{
6630}
6631
6632int msm_onenand_scan(struct mtd_info *mtd, int maxchips)
6633{
6634 struct msm_nand_chip *chip = mtd->priv;
6635
6636 /* Probe and check whether onenand device is present */
6637 if (flash_onenand_probe(chip))
6638 return -ENODEV;
6639
6640 mtd->size = 0x1000000 << ((onenand_info.device_id & 0xF0) >> 4);
6641 mtd->writesize = onenand_info.data_buf_size;
6642 mtd->oobsize = mtd->writesize >> 5;
6643 mtd->erasesize = mtd->writesize << 6;
6644 mtd->oobavail = msm_onenand_oob_64.oobavail;
6645 mtd->ecclayout = &msm_onenand_oob_64;
6646
6647 mtd->type = MTD_NANDFLASH;
6648 mtd->flags = MTD_CAP_NANDFLASH;
6649 mtd->erase = msm_onenand_erase;
6650 mtd->point = NULL;
6651 mtd->unpoint = NULL;
6652 mtd->read = msm_onenand_read;
6653 mtd->write = msm_onenand_write;
6654 mtd->read_oob = msm_onenand_read_oob;
6655 mtd->write_oob = msm_onenand_write_oob;
6656 mtd->lock = msm_onenand_lock;
6657 mtd->unlock = msm_onenand_unlock;
6658 mtd->suspend = msm_onenand_suspend;
6659 mtd->resume = msm_onenand_resume;
6660 mtd->block_isbad = msm_onenand_block_isbad;
6661 mtd->block_markbad = msm_onenand_block_markbad;
6662 mtd->owner = THIS_MODULE;
6663
6664 pr_info("Found a supported onenand device\n");
6665
6666 return 0;
6667}
6668
6669/**
6670 * msm_nand_scan - [msm_nand Interface] Scan for the msm_nand device
6671 * @param mtd MTD device structure
6672 * @param maxchips Number of chips to scan for
6673 *
6674 * This fills out all the not initialized function pointers
6675 * with the defaults.
6676 * The flash ID is read and the mtd/chip structures are
6677 * filled with the appropriate values.
6678 */
6679int msm_nand_scan(struct mtd_info *mtd, int maxchips)
6680{
6681 struct msm_nand_chip *chip = mtd->priv;
6682 uint32_t flash_id = 0, i, mtd_writesize;
6683 uint8_t dev_found = 0;
6684 uint8_t wide_bus;
6685 uint32_t manid;
6686 uint32_t devid;
6687 uint32_t devcfg;
6688 struct nand_flash_dev *flashdev = NULL;
6689 struct nand_manufacturers *flashman = NULL;
6690
6691 /* Probe the Flash device for ONFI compliance */
6692 if (!flash_onfi_probe(chip)) {
6693 dev_found = 1;
6694 } else {
6695 /* Read the Flash ID from the Nand Flash Device */
6696 flash_id = flash_read_id(chip);
6697 manid = flash_id & 0xFF;
6698 devid = (flash_id >> 8) & 0xFF;
6699 devcfg = (flash_id >> 24) & 0xFF;
6700
6701 for (i = 0; !flashman && nand_manuf_ids[i].id; ++i)
6702 if (nand_manuf_ids[i].id == manid)
6703 flashman = &nand_manuf_ids[i];
6704 for (i = 0; !flashdev && nand_flash_ids[i].id; ++i)
6705 if (nand_flash_ids[i].id == devid)
6706 flashdev = &nand_flash_ids[i];
6707 if (!flashdev || !flashman) {
6708 pr_err("ERROR: unknown nand device manuf=%x devid=%x\n",
6709 manid, devid);
6710 return -ENOENT;
6711 } else
6712 dev_found = 1;
6713
6714 if (!flashdev->pagesize) {
6715 supported_flash.flash_id = flash_id;
6716 supported_flash.density = flashdev->chipsize << 20;
6717 supported_flash.widebus = devcfg & (1 << 6) ? 1 : 0;
6718 supported_flash.pagesize = 1024 << (devcfg & 0x3);
6719 supported_flash.blksize = (64 * 1024) <<
6720 ((devcfg >> 4) & 0x3);
Krishna Konda99e362f2012-02-29 21:16:34 -0800[diff] [blame]6721 supported_flash.oobsize = (8 << ((devcfg >> 2) & 0x3)) *
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6722 (supported_flash.pagesize >> 9);
Krishna Kondad9d4dae52012-02-29 21:33:14 -0800[diff] [blame^]6723
6724 if ((supported_flash.oobsize > 64) &&
6725 (supported_flash.pagesize == 2048)) {
6726 pr_info("msm_nand: Found a 2K page device with"
6727 " %d oobsize - changing oobsize to 64 "
6728 "bytes.\n", supported_flash.oobsize);
6729 supported_flash.oobsize = 64;
6730 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6731 } else {
6732 supported_flash.flash_id = flash_id;
6733 supported_flash.density = flashdev->chipsize << 20;
6734 supported_flash.widebus = flashdev->options &
6735 NAND_BUSWIDTH_16 ? 1 : 0;
6736 supported_flash.pagesize = flashdev->pagesize;
6737 supported_flash.blksize = flashdev->erasesize;
6738 supported_flash.oobsize = flashdev->pagesize >> 5;
6739 }
6740 }
6741
6742 if (dev_found) {
6743 (!interleave_enable) ? (i = 1) : (i = 2);
6744 wide_bus = supported_flash.widebus;
6745 mtd->size = supported_flash.density * i;
6746 mtd->writesize = supported_flash.pagesize * i;
6747 mtd->oobsize = supported_flash.oobsize * i;
6748 mtd->erasesize = supported_flash.blksize * i;
6749
6750 if (!interleave_enable)
6751 mtd_writesize = mtd->writesize;
6752 else
6753 mtd_writesize = mtd->writesize >> 1;
6754
6755 /* Check whether controller and NAND device support 8bit ECC*/
6756 if ((flash_rd_reg(chip, MSM_NAND_HW_INFO) == 0x307)
6757 && (supported_flash.ecc_correctability >= 8)) {
6758 pr_info("Found supported NAND device for %dbit ECC\n",
6759 supported_flash.ecc_correctability);
6760 enable_bch_ecc = 1;
6761 } else {
6762 pr_info("Found a supported NAND device\n");
6763 }
6764 pr_info("NAND Id : 0x%x\n", supported_flash.flash_id);
6765 pr_info("Buswidth : %d Bits\n", (wide_bus) ? 16 : 8);
6766 pr_info("Density : %lld MByte\n", (mtd->size>>20));
6767 pr_info("Pagesize : %d Bytes\n", mtd->writesize);
6768 pr_info("Erasesize: %d Bytes\n", mtd->erasesize);
6769 pr_info("Oobsize : %d Bytes\n", mtd->oobsize);
6770 } else {
6771 pr_err("Unsupported Nand,Id: 0x%x \n", flash_id);
6772 return -ENODEV;
6773 }
6774
6775 /* Size of each codeword is 532Bytes incase of 8bit BCH ECC*/
6776 chip->cw_size = enable_bch_ecc ? 532 : 528;
6777 chip->CFG0 = (((mtd_writesize >> 9)-1) << 6) /* 4/8 cw/pg for 2/4k */
6778 | (516 << 9) /* 516 user data bytes */
6779 | (10 << 19) /* 10 parity bytes */
6780 | (5 << 27) /* 5 address cycles */
6781 | (0 << 30) /* Do not read status before data */
6782 | (1 << 31) /* Send read cmd */
6783 /* 0 spare bytes for 16 bit nand or 1/2 spare bytes for 8 bit */
6784 | (wide_bus ? 0 << 23 : (enable_bch_ecc ? 2 << 23 : 1 << 23));
6785
6786 chip->CFG1 = (0 << 0) /* Enable ecc */
6787 | (7 << 2) /* 8 recovery cycles */
6788 | (0 << 5) /* Allow CS deassertion */
6789 /* Bad block marker location */
6790 | ((mtd_writesize - (chip->cw_size * (
6791 (mtd_writesize >> 9) - 1)) + 1) << 6)
6792 | (0 << 16) /* Bad block in user data area */
6793 | (2 << 17) /* 6 cycle tWB/tRB */
6794 | ((wide_bus) ? CFG1_WIDE_FLASH : 0); /* Wide flash bit */
6795
6796 chip->ecc_buf_cfg = 0x203;
6797 chip->CFG0_RAW = 0xA80420C0;
6798 chip->CFG1_RAW = 0x5045D;
6799
6800 if (enable_bch_ecc) {
6801 chip->CFG1 |= (1 << 27); /* Enable BCH engine */
6802 chip->ecc_bch_cfg = (0 << 0) /* Enable ECC*/
6803 | (0 << 1) /* Enable/Disable SW reset of ECC engine */
6804 | (1 << 4) /* 8bit ecc*/
6805 | ((wide_bus) ? (14 << 8) : (13 << 8))/*parity bytes*/
6806 | (516 << 16) /* 516 user data bytes */
6807 | (1 << 30); /* Turn on ECC engine clocks always */
6808 chip->CFG0_RAW = 0xA80428C0; /* CW size is increased to 532B */
6809 }
6810
6811 /*
6812 * For 4bit RS ECC (default ECC), parity bytes = 10 (for x8 and x16 I/O)
6813 * For 8bit BCH ECC, parity bytes = 13 (x8) or 14 (x16 I/O).
6814 */
6815 chip->ecc_parity_bytes = enable_bch_ecc ? (wide_bus ? 14 : 13) : 10;
6816
6817 pr_info("CFG0 Init : 0x%08x\n", chip->CFG0);
6818 pr_info("CFG1 Init : 0x%08x\n", chip->CFG1);
6819 pr_info("ECCBUFCFG : 0x%08x\n", chip->ecc_buf_cfg);
6820
6821 if (mtd->oobsize == 64) {
6822 mtd->oobavail = msm_nand_oob_64.oobavail;
6823 mtd->ecclayout = &msm_nand_oob_64;
6824 } else if (mtd->oobsize == 128) {
6825 mtd->oobavail = msm_nand_oob_128.oobavail;
6826 mtd->ecclayout = &msm_nand_oob_128;
6827 } else if (mtd->oobsize == 224) {
6828 mtd->oobavail = wide_bus ? msm_nand_oob_224_x16.oobavail :
6829 msm_nand_oob_224_x8.oobavail;
6830 mtd->ecclayout = wide_bus ? &msm_nand_oob_224_x16 :
6831 &msm_nand_oob_224_x8;
6832 } else if (mtd->oobsize == 256) {
6833 mtd->oobavail = msm_nand_oob_256.oobavail;
6834 mtd->ecclayout = &msm_nand_oob_256;
6835 } else {
6836 pr_err("Unsupported Nand, oobsize: 0x%x \n",
6837 mtd->oobsize);
6838 return -ENODEV;
6839 }
6840
6841 /* Fill in remaining MTD driver data */
6842 mtd->type = MTD_NANDFLASH;
6843 mtd->flags = MTD_CAP_NANDFLASH;
6844 /* mtd->ecctype = MTD_ECC_SW; */
6845 mtd->erase = msm_nand_erase;
6846 mtd->block_isbad = msm_nand_block_isbad;
6847 mtd->block_markbad = msm_nand_block_markbad;
6848 mtd->point = NULL;
6849 mtd->unpoint = NULL;
6850 mtd->read = msm_nand_read;
6851 mtd->write = msm_nand_write;
6852 mtd->read_oob = msm_nand_read_oob;
6853 mtd->write_oob = msm_nand_write_oob;
6854 if (dual_nand_ctlr_present) {
6855 mtd->read_oob = msm_nand_read_oob_dualnandc;
6856 mtd->write_oob = msm_nand_write_oob_dualnandc;
6857 if (interleave_enable) {
6858 mtd->erase = msm_nand_erase_dualnandc;
6859 mtd->block_isbad = msm_nand_block_isbad_dualnandc;
6860 }
6861 }
6862
6863 /* mtd->sync = msm_nand_sync; */
6864 mtd->lock = NULL;
6865 /* mtd->unlock = msm_nand_unlock; */
6866 mtd->suspend = msm_nand_suspend;
6867 mtd->resume = msm_nand_resume;
6868 mtd->owner = THIS_MODULE;
6869
6870 /* Unlock whole block */
6871 /* msm_nand_unlock_all(mtd); */
6872
6873 /* return this->scan_bbt(mtd); */
6874 return 0;
6875}
6876EXPORT_SYMBOL_GPL(msm_nand_scan);
6877
6878/**
6879 * msm_nand_release - [msm_nand Interface] Free resources held by the msm_nand device
6880 * @param mtd MTD device structure
6881 */
6882void msm_nand_release(struct mtd_info *mtd)
6883{
6884 /* struct msm_nand_chip *this = mtd->priv; */
6885
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6886 /* Deregister the device */
6887 mtd_device_unregister(mtd);
6888}
6889EXPORT_SYMBOL_GPL(msm_nand_release);
6890
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6891struct msm_nand_info {
6892 struct mtd_info mtd;
6893 struct mtd_partition *parts;
6894 struct msm_nand_chip msm_nand;
6895};
6896
6897/* duplicating the NC01 XFR contents to NC10 */
6898static int msm_nand_nc10_xfr_settings(struct mtd_info *mtd)
6899{
6900 struct msm_nand_chip *chip = mtd->priv;
6901
6902 struct {
6903 dmov_s cmd[2];
6904 unsigned cmdptr;
6905 } *dma_buffer;
6906 dmov_s *cmd;
6907
6908 wait_event(chip->wait_queue,
6909 (dma_buffer = msm_nand_get_dma_buffer(
6910 chip, sizeof(*dma_buffer))));
6911
6912 cmd = dma_buffer->cmd;
6913
6914 /* Copying XFR register contents from NC01 --> NC10 */
6915 cmd->cmd = 0;
6916 cmd->src = NC01(MSM_NAND_XFR_STEP1);
6917 cmd->dst = NC10(MSM_NAND_XFR_STEP1);
6918 cmd->len = 28;
6919 cmd++;
6920
6921 BUILD_BUG_ON(2 != ARRAY_SIZE(dma_buffer->cmd));
6922 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6923 dma_buffer->cmd[0].cmd |= CMD_OCB;
6924 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6925 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
6926 | CMD_PTR_LP;
6927
6928 mb();
Jeff Ohlsteindc39f972011-09-02 13:55:16 -0700[diff] [blame]6929 msm_dmov_exec_cmd(chip->dma_channel, DMOV_CMD_PTR_LIST
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6930 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6931 &dma_buffer->cmdptr)));
6932 mb();
6933 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6934 return 0;
6935}
6936
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame]6937static int setup_mtd_device(struct platform_device *pdev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6938 struct msm_nand_info *info)
6939{
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame]6940 int i, err;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6941 struct flash_platform_data *pdata = pdev->dev.platform_data;
6942
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame]6943 if (pdata) {
6944 for (i = 0; i < pdata->nr_parts; i++) {
6945 pdata->parts[i].offset = pdata->parts[i].offset
6946 * info->mtd.erasesize;
6947 pdata->parts[i].size = pdata->parts[i].size
6948 * info->mtd.erasesize;
6949 }
6950 err = mtd_device_register(&info->mtd, pdata->parts,
6951 pdata->nr_parts);
6952 } else {
6953 err = mtd_device_register(&info->mtd, NULL, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6954 }
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame]6955 return err;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6956}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6957
6958static int __devinit msm_nand_probe(struct platform_device *pdev)
6959{
6960 struct msm_nand_info *info;
6961 struct resource *res;
6962 int err;
6963 struct flash_platform_data *plat_data;
6964
6965 plat_data = pdev->dev.platform_data;
6966
6967 res = platform_get_resource_byname(pdev,
6968 IORESOURCE_MEM, "msm_nand_phys");
6969 if (!res || !res->start) {
6970 pr_err("%s: msm_nand_phys resource invalid/absent\n",
6971 __func__);
6972 return -ENODEV;
6973 }
6974 msm_nand_phys = res->start;
6975 pr_info("%s: phys addr 0x%lx \n", __func__, msm_nand_phys);
6976
6977 res = platform_get_resource_byname(pdev,
6978 IORESOURCE_MEM, "msm_nandc01_phys");
6979 if (!res || !res->start)
6980 goto no_dual_nand_ctlr_support;
6981 msm_nandc01_phys = res->start;
6982
6983 res = platform_get_resource_byname(pdev,
6984 IORESOURCE_MEM, "msm_nandc10_phys");
6985 if (!res || !res->start)
6986 goto no_dual_nand_ctlr_support;
6987 msm_nandc10_phys = res->start;
6988
6989 res = platform_get_resource_byname(pdev,
6990 IORESOURCE_MEM, "msm_nandc11_phys");
6991 if (!res || !res->start)
6992 goto no_dual_nand_ctlr_support;
6993 msm_nandc11_phys = res->start;
6994
6995 res = platform_get_resource_byname(pdev,
6996 IORESOURCE_MEM, "ebi2_reg_base");
6997 if (!res || !res->start)
6998 goto no_dual_nand_ctlr_support;
6999 ebi2_register_base = res->start;
7000
7001 dual_nand_ctlr_present = 1;
7002 if (plat_data != NULL)
7003 interleave_enable = plat_data->interleave;
7004 else
7005 interleave_enable = 0;
7006
7007 if (!interleave_enable)
7008 pr_info("%s: Dual Nand Ctrl in ping-pong mode\n", __func__);
7009 else
7010 pr_info("%s: Dual Nand Ctrl in interleave mode\n", __func__);
7011
7012no_dual_nand_ctlr_support:
7013 res = platform_get_resource_byname(pdev,
7014 IORESOURCE_DMA, "msm_nand_dmac");
7015 if (!res || !res->start) {
7016 pr_err("%s: invalid msm_nand_dmac resource\n", __func__);
7017 return -ENODEV;
7018 }
7019
7020 info = kzalloc(sizeof(struct msm_nand_info), GFP_KERNEL);
7021 if (!info) {
7022 pr_err("%s: No memory for msm_nand_info\n", __func__);
7023 return -ENOMEM;
7024 }
7025
7026 info->msm_nand.dev = &pdev->dev;
7027
7028 init_waitqueue_head(&info->msm_nand.wait_queue);
7029
7030 info->msm_nand.dma_channel = res->start;
7031 pr_info("%s: dmac 0x%x\n", __func__, info->msm_nand.dma_channel);
7032
7033 /* this currently fails if dev is passed in */
7034 info->msm_nand.dma_buffer =
7035 dma_alloc_coherent(/*dev*/ NULL, MSM_NAND_DMA_BUFFER_SIZE,
7036 &info->msm_nand.dma_addr, GFP_KERNEL);
7037 if (info->msm_nand.dma_buffer == NULL) {
7038 pr_err("%s: No memory for msm_nand.dma_buffer\n", __func__);
7039 err = -ENOMEM;
7040 goto out_free_info;
7041 }
7042
7043 pr_info("%s: allocated dma buffer at %p, dma_addr %x\n",
7044 __func__, info->msm_nand.dma_buffer, info->msm_nand.dma_addr);
7045
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]7046 info->mtd.name = dev_name(&pdev->dev);
7047 info->mtd.priv = &info->msm_nand;
7048 info->mtd.owner = THIS_MODULE;
7049
7050 /* config ebi2_cfg register only for ping pong mode!!! */
7051 if (!interleave_enable && dual_nand_ctlr_present)
7052 flash_wr_reg(&info->msm_nand, EBI2_CFG_REG, 0x4010080);
7053
7054 if (dual_nand_ctlr_present)
7055 msm_nand_nc10_xfr_settings(&info->mtd);
7056
7057 if (msm_nand_scan(&info->mtd, 1))
7058 if (msm_onenand_scan(&info->mtd, 1)) {
7059 pr_err("%s: No nand device found\n", __func__);
7060 err = -ENXIO;
7061 goto out_free_dma_buffer;
7062 }
7063
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame]7064 err = setup_mtd_device(pdev, info);
7065 if (err < 0) {
7066 pr_err("%s: setup_mtd_device failed with err=%d\n",
7067 __func__, err);
7068 goto out_free_dma_buffer;
7069 }
7070
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]7071 dev_set_drvdata(&pdev->dev, info);
7072
7073 return 0;
7074
7075out_free_dma_buffer:
7076 dma_free_coherent(NULL, MSM_NAND_DMA_BUFFER_SIZE,
7077 info->msm_nand.dma_buffer,
7078 info->msm_nand.dma_addr);
7079out_free_info:
7080 kfree(info);
7081
7082 return err;
7083}
7084
7085static int __devexit msm_nand_remove(struct platform_device *pdev)
7086{
7087 struct msm_nand_info *info = dev_get_drvdata(&pdev->dev);
7088
7089 dev_set_drvdata(&pdev->dev, NULL);
7090
7091 if (info) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]7092 msm_nand_release(&info->mtd);
7093 dma_free_coherent(NULL, MSM_NAND_DMA_BUFFER_SIZE,
7094 info->msm_nand.dma_buffer,
7095 info->msm_nand.dma_addr);
7096 kfree(info);
7097 }
7098
7099 return 0;
7100}
7101
7102#define DRIVER_NAME "msm_nand"
7103
7104static struct platform_driver msm_nand_driver = {
7105 .probe = msm_nand_probe,
7106 .remove = __devexit_p(msm_nand_remove),
7107 .driver = {
7108 .name = DRIVER_NAME,
7109 }
7110};
7111
7112MODULE_ALIAS(DRIVER_NAME);
7113
7114static int __init msm_nand_init(void)
7115{
7116 return platform_driver_register(&msm_nand_driver);
7117}
7118
7119static void __exit msm_nand_exit(void)
7120{
7121 platform_driver_unregister(&msm_nand_driver);
7122}
7123
7124module_init(msm_nand_init);
7125module_exit(msm_nand_exit);
7126
7127MODULE_LICENSE("GPL");
7128MODULE_DESCRIPTION("msm_nand flash driver code");