blob: 62f68d6181c652b3bd8be030463b78e260f89db0 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
11 * Includes support for the following PHYs: QS6612, LXT970, LXT971/2.
12 *
13 * Right now, I am very wasteful with the buffers. I allocate memory
14 * pages and then divide them into 2K frame buffers. This way I know I
15 * have buffers large enough to hold one frame within one buffer descriptor.
16 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
17 * will be much more memory efficient and will easily handle lots of
18 * small packets.
19 *
20 * Much better multiple PHY support by Magnus Damm.
21 * Copyright (c) 2000 Ericsson Radio Systems AB.
22 *
23 * Make use of MII for PHY control configurable.
24 * Some fixes.
25 * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering.
26 *
27 * Support for AMD AM79C874 added.
28 * Thomas Lange, thomas@corelatus.com
29 */
30
31#include <linux/config.h>
32#include <linux/kernel.h>
33#include <linux/sched.h>
34#include <linux/string.h>
35#include <linux/ptrace.h>
36#include <linux/errno.h>
37#include <linux/ioport.h>
38#include <linux/slab.h>
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/init.h>
42#include <linux/delay.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/skbuff.h>
46#include <linux/spinlock.h>
47#include <linux/bitops.h>
48#ifdef CONFIG_FEC_PACKETHOOK
49#include <linux/pkthook.h>
50#endif
51
52#include <asm/8xx_immap.h>
53#include <asm/pgtable.h>
54#include <asm/mpc8xx.h>
55#include <asm/irq.h>
56#include <asm/uaccess.h>
57#include <asm/commproc.h>
58
59#ifdef CONFIG_USE_MDIO
60/* Forward declarations of some structures to support different PHYs
61*/
62
63typedef struct {
64 uint mii_data;
65 void (*funct)(uint mii_reg, struct net_device *dev);
66} phy_cmd_t;
67
68typedef struct {
69 uint id;
70 char *name;
71
72 const phy_cmd_t *config;
73 const phy_cmd_t *startup;
74 const phy_cmd_t *ack_int;
75 const phy_cmd_t *shutdown;
76} phy_info_t;
77#endif /* CONFIG_USE_MDIO */
78
79/* The number of Tx and Rx buffers. These are allocated from the page
80 * pool. The code may assume these are power of two, so it is best
81 * to keep them that size.
82 * We don't need to allocate pages for the transmitter. We just use
83 * the skbuffer directly.
84 */
85#ifdef CONFIG_ENET_BIG_BUFFERS
86#define FEC_ENET_RX_PAGES 16
87#define FEC_ENET_RX_FRSIZE 2048
88#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
89#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
90#define TX_RING_SIZE 16 /* Must be power of two */
91#define TX_RING_MOD_MASK 15 /* for this to work */
92#else
93#define FEC_ENET_RX_PAGES 4
94#define FEC_ENET_RX_FRSIZE 2048
95#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
96#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
97#define TX_RING_SIZE 8 /* Must be power of two */
98#define TX_RING_MOD_MASK 7 /* for this to work */
99#endif
100
101/* Interrupt events/masks.
102*/
103#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
104#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
105#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
106#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
107#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
108#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
109#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
110#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
111#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
112#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
113
114/*
115*/
116#define FEC_ECNTRL_PINMUX 0x00000004
117#define FEC_ECNTRL_ETHER_EN 0x00000002
118#define FEC_ECNTRL_RESET 0x00000001
119
120#define FEC_RCNTRL_BC_REJ 0x00000010
121#define FEC_RCNTRL_PROM 0x00000008
122#define FEC_RCNTRL_MII_MODE 0x00000004
123#define FEC_RCNTRL_DRT 0x00000002
124#define FEC_RCNTRL_LOOP 0x00000001
125
126#define FEC_TCNTRL_FDEN 0x00000004
127#define FEC_TCNTRL_HBC 0x00000002
128#define FEC_TCNTRL_GTS 0x00000001
129
130/* Delay to wait for FEC reset command to complete (in us)
131*/
132#define FEC_RESET_DELAY 50
133
134/* The FEC stores dest/src/type, data, and checksum for receive packets.
135 */
136#define PKT_MAXBUF_SIZE 1518
137#define PKT_MINBUF_SIZE 64
138#define PKT_MAXBLR_SIZE 1520
139
140/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
147 */
148struct fec_enet_private {
149 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
150 struct sk_buff* tx_skbuff[TX_RING_SIZE];
151 ushort skb_cur;
152 ushort skb_dirty;
153
154 /* CPM dual port RAM relative addresses.
155 */
156 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
157 cbd_t *tx_bd_base;
158 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
159 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
160
161 /* Virtual addresses for the receive buffers because we can't
162 * do a __va() on them anymore.
163 */
164 unsigned char *rx_vaddr[RX_RING_SIZE];
165
166 struct net_device_stats stats;
167 uint tx_full;
168 spinlock_t lock;
169
170#ifdef CONFIG_USE_MDIO
171 uint phy_id;
172 uint phy_id_done;
173 uint phy_status;
174 uint phy_speed;
175 phy_info_t *phy;
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -0700176 struct work_struct phy_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177
178 uint sequence_done;
179
180 uint phy_addr;
181#endif /* CONFIG_USE_MDIO */
182
183 int link;
184 int old_link;
185 int full_duplex;
186
187#ifdef CONFIG_FEC_PACKETHOOK
188 unsigned long ph_lock;
189 fec_ph_func *ph_rxhandler;
190 fec_ph_func *ph_txhandler;
191 __u16 ph_proto;
192 volatile __u32 *ph_regaddr;
193 void *ph_priv;
194#endif
195};
196
197static int fec_enet_open(struct net_device *dev);
198static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
199#ifdef CONFIG_USE_MDIO
200static void fec_enet_mii(struct net_device *dev);
201#endif /* CONFIG_USE_MDIO */
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -0700202static irqreturn_t fec_enet_interrupt(int irq, void * dev_id,
203 struct pt_regs * regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204#ifdef CONFIG_FEC_PACKETHOOK
205static void fec_enet_tx(struct net_device *dev, __u32 regval);
206static void fec_enet_rx(struct net_device *dev, __u32 regval);
207#else
208static void fec_enet_tx(struct net_device *dev);
209static void fec_enet_rx(struct net_device *dev);
210#endif
211static int fec_enet_close(struct net_device *dev);
212static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
213static void set_multicast_list(struct net_device *dev);
214static void fec_restart(struct net_device *dev, int duplex);
215static void fec_stop(struct net_device *dev);
216static ushort my_enet_addr[3];
217
218#ifdef CONFIG_USE_MDIO
219/* MII processing. We keep this as simple as possible. Requests are
220 * placed on the list (if there is room). When the request is finished
221 * by the MII, an optional function may be called.
222 */
223typedef struct mii_list {
224 uint mii_regval;
225 void (*mii_func)(uint val, struct net_device *dev);
226 struct mii_list *mii_next;
227} mii_list_t;
228
229#define NMII 20
230mii_list_t mii_cmds[NMII];
231mii_list_t *mii_free;
232mii_list_t *mii_head;
233mii_list_t *mii_tail;
234
235static int mii_queue(struct net_device *dev, int request,
236 void (*func)(uint, struct net_device *));
237
238/* Make MII read/write commands for the FEC.
239*/
240#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
241#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
242 (VAL & 0xffff))
243#define mk_mii_end 0
244#endif /* CONFIG_USE_MDIO */
245
246/* Transmitter timeout.
247*/
248#define TX_TIMEOUT (2*HZ)
249
250#ifdef CONFIG_USE_MDIO
251/* Register definitions for the PHY.
252*/
253
254#define MII_REG_CR 0 /* Control Register */
255#define MII_REG_SR 1 /* Status Register */
256#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
257#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
258#define MII_REG_ANAR 4 /* A-N Advertisement Register */
259#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
260#define MII_REG_ANER 6 /* A-N Expansion Register */
261#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
262#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
263
264/* values for phy_status */
265
266#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
267#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
268#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
269#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
270#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
271#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
272#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
273
274#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
275#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
276#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
277#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
278#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
279#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
280#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
281#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
282#endif /* CONFIG_USE_MDIO */
283
284#ifdef CONFIG_FEC_PACKETHOOK
285int
286fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun,
287 __u16 proto, volatile __u32 *regaddr, void *priv)
288{
289 struct fec_enet_private *fep;
290 int retval = 0;
291
292 fep = dev->priv;
293
294 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
295 /* Someone is messing with the packet hook */
296 return -EAGAIN;
297 }
298 if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) {
299 retval = -EBUSY;
300 goto out;
301 }
302 fep->ph_rxhandler = rxfun;
303 fep->ph_txhandler = txfun;
304 fep->ph_proto = proto;
305 fep->ph_regaddr = regaddr;
306 fep->ph_priv = priv;
307
308 out:
309 fep->ph_lock = 0;
310
311 return retval;
312}
313
314
315int
316fec_unregister_ph(struct net_device *dev)
317{
318 struct fec_enet_private *fep;
319 int retval = 0;
320
321 fep = dev->priv;
322
323 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
324 /* Someone is messing with the packet hook */
325 return -EAGAIN;
326 }
327
328 fep->ph_rxhandler = fep->ph_txhandler = NULL;
329 fep->ph_proto = 0;
330 fep->ph_regaddr = NULL;
331 fep->ph_priv = NULL;
332
333 fep->ph_lock = 0;
334
335 return retval;
336}
337
338EXPORT_SYMBOL(fec_register_ph);
339EXPORT_SYMBOL(fec_unregister_ph);
340
341#endif /* CONFIG_FEC_PACKETHOOK */
342
343static int
344fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
345{
346 struct fec_enet_private *fep;
347 volatile fec_t *fecp;
348 volatile cbd_t *bdp;
349
350 fep = dev->priv;
351 fecp = (volatile fec_t*)dev->base_addr;
352
353 if (!fep->link) {
354 /* Link is down or autonegotiation is in progress. */
355 return 1;
356 }
357
358 /* Fill in a Tx ring entry */
359 bdp = fep->cur_tx;
360
361#ifndef final_version
362 if (bdp->cbd_sc & BD_ENET_TX_READY) {
363 /* Ooops. All transmit buffers are full. Bail out.
364 * This should not happen, since dev->tbusy should be set.
365 */
366 printk("%s: tx queue full!.\n", dev->name);
367 return 1;
368 }
369#endif
370
371 /* Clear all of the status flags.
372 */
373 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
374
375 /* Set buffer length and buffer pointer.
376 */
377 bdp->cbd_bufaddr = __pa(skb->data);
378 bdp->cbd_datlen = skb->len;
379
380 /* Save skb pointer.
381 */
382 fep->tx_skbuff[fep->skb_cur] = skb;
383
384 fep->stats.tx_bytes += skb->len;
385 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
386
387 /* Push the data cache so the CPM does not get stale memory
388 * data.
389 */
390 flush_dcache_range((unsigned long)skb->data,
391 (unsigned long)skb->data + skb->len);
392
393 /* disable interrupts while triggering transmit */
394 spin_lock_irq(&fep->lock);
395
396 /* Send it on its way. Tell FEC its ready, interrupt when done,
397 * its the last BD of the frame, and to put the CRC on the end.
398 */
399
400 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
401 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
402
403 dev->trans_start = jiffies;
404
405 /* Trigger transmission start */
406 fecp->fec_x_des_active = 0x01000000;
407
408 /* If this was the last BD in the ring, start at the beginning again.
409 */
410 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
411 bdp = fep->tx_bd_base;
412 } else {
413 bdp++;
414 }
415
416 if (bdp->cbd_sc & BD_ENET_TX_READY) {
417 netif_stop_queue(dev);
418 fep->tx_full = 1;
419 }
420
421 fep->cur_tx = (cbd_t *)bdp;
422
423 spin_unlock_irq(&fep->lock);
424
425 return 0;
426}
427
428static void
429fec_timeout(struct net_device *dev)
430{
431 struct fec_enet_private *fep = dev->priv;
432
433 printk("%s: transmit timed out.\n", dev->name);
434 fep->stats.tx_errors++;
435#ifndef final_version
436 {
437 int i;
438 cbd_t *bdp;
439
440 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
441 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
442 (unsigned long)fep->dirty_tx,
443 (unsigned long)fep->cur_rx);
444
445 bdp = fep->tx_bd_base;
446 printk(" tx: %u buffers\n", TX_RING_SIZE);
447 for (i = 0 ; i < TX_RING_SIZE; i++) {
448 printk(" %08x: %04x %04x %08x\n",
449 (uint) bdp,
450 bdp->cbd_sc,
451 bdp->cbd_datlen,
452 bdp->cbd_bufaddr);
453 bdp++;
454 }
455
456 bdp = fep->rx_bd_base;
457 printk(" rx: %lu buffers\n", RX_RING_SIZE);
458 for (i = 0 ; i < RX_RING_SIZE; i++) {
459 printk(" %08x: %04x %04x %08x\n",
460 (uint) bdp,
461 bdp->cbd_sc,
462 bdp->cbd_datlen,
463 bdp->cbd_bufaddr);
464 bdp++;
465 }
466 }
467#endif
468 if (!fep->tx_full)
469 netif_wake_queue(dev);
470}
471
472/* The interrupt handler.
473 * This is called from the MPC core interrupt.
474 */
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -0700475static irqreturn_t
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
477{
478 struct net_device *dev = dev_id;
479 volatile fec_t *fecp;
480 uint int_events;
481#ifdef CONFIG_FEC_PACKETHOOK
482 struct fec_enet_private *fep = dev->priv;
483 __u32 regval;
484
485 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
486#endif
487 fecp = (volatile fec_t*)dev->base_addr;
488
489 /* Get the interrupt events that caused us to be here.
490 */
491 while ((int_events = fecp->fec_ievent) != 0) {
492 fecp->fec_ievent = int_events;
493 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
494 FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
495 printk("FEC ERROR %x\n", int_events);
496 }
497
498 /* Handle receive event in its own function.
499 */
500 if (int_events & FEC_ENET_RXF) {
501#ifdef CONFIG_FEC_PACKETHOOK
502 fec_enet_rx(dev, regval);
503#else
504 fec_enet_rx(dev);
505#endif
506 }
507
508 /* Transmit OK, or non-fatal error. Update the buffer
509 descriptors. FEC handles all errors, we just discover
510 them as part of the transmit process.
511 */
512 if (int_events & FEC_ENET_TXF) {
513#ifdef CONFIG_FEC_PACKETHOOK
514 fec_enet_tx(dev, regval);
515#else
516 fec_enet_tx(dev);
517#endif
518 }
519
520 if (int_events & FEC_ENET_MII) {
521#ifdef CONFIG_USE_MDIO
522 fec_enet_mii(dev);
523#else
524printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
525#endif /* CONFIG_USE_MDIO */
526 }
527
528 }
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -0700529 return IRQ_RETVAL(IRQ_HANDLED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530}
531
532
533static void
534#ifdef CONFIG_FEC_PACKETHOOK
535fec_enet_tx(struct net_device *dev, __u32 regval)
536#else
537fec_enet_tx(struct net_device *dev)
538#endif
539{
540 struct fec_enet_private *fep;
541 volatile cbd_t *bdp;
542 struct sk_buff *skb;
543
544 fep = dev->priv;
545 /* lock while transmitting */
546 spin_lock(&fep->lock);
547 bdp = fep->dirty_tx;
548
549 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
550 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
551
552 skb = fep->tx_skbuff[fep->skb_dirty];
553 /* Check for errors. */
554 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
555 BD_ENET_TX_RL | BD_ENET_TX_UN |
556 BD_ENET_TX_CSL)) {
557 fep->stats.tx_errors++;
558 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
559 fep->stats.tx_heartbeat_errors++;
560 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
561 fep->stats.tx_window_errors++;
562 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
563 fep->stats.tx_aborted_errors++;
564 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
565 fep->stats.tx_fifo_errors++;
566 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
567 fep->stats.tx_carrier_errors++;
568 } else {
569#ifdef CONFIG_FEC_PACKETHOOK
570 /* Packet hook ... */
571 if (fep->ph_txhandler &&
572 ((struct ethhdr *)skb->data)->h_proto
573 == fep->ph_proto) {
574 fep->ph_txhandler((__u8*)skb->data, skb->len,
575 regval, fep->ph_priv);
576 }
577#endif
578 fep->stats.tx_packets++;
579 }
580
581#ifndef final_version
582 if (bdp->cbd_sc & BD_ENET_TX_READY)
583 printk("HEY! Enet xmit interrupt and TX_READY.\n");
584#endif
585 /* Deferred means some collisions occurred during transmit,
586 * but we eventually sent the packet OK.
587 */
588 if (bdp->cbd_sc & BD_ENET_TX_DEF)
589 fep->stats.collisions++;
590
591 /* Free the sk buffer associated with this last transmit.
592 */
593#if 0
594printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty);
595#endif
596 dev_kfree_skb_irq (skb/*, FREE_WRITE*/);
597 fep->tx_skbuff[fep->skb_dirty] = NULL;
598 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
599
600 /* Update pointer to next buffer descriptor to be transmitted.
601 */
602 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
603 bdp = fep->tx_bd_base;
604 else
605 bdp++;
606
607 /* Since we have freed up a buffer, the ring is no longer
608 * full.
609 */
610 if (fep->tx_full) {
611 fep->tx_full = 0;
612 if (netif_queue_stopped(dev))
613 netif_wake_queue(dev);
614 }
615#ifdef CONFIG_FEC_PACKETHOOK
616 /* Re-read register. Not exactly guaranteed to be correct,
617 but... */
618 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
619#endif
620 }
621 fep->dirty_tx = (cbd_t *)bdp;
622 spin_unlock(&fep->lock);
623}
624
625
626/* During a receive, the cur_rx points to the current incoming buffer.
627 * When we update through the ring, if the next incoming buffer has
628 * not been given to the system, we just set the empty indicator,
629 * effectively tossing the packet.
630 */
631static void
632#ifdef CONFIG_FEC_PACKETHOOK
633fec_enet_rx(struct net_device *dev, __u32 regval)
634#else
635fec_enet_rx(struct net_device *dev)
636#endif
637{
638 struct fec_enet_private *fep;
639 volatile fec_t *fecp;
640 volatile cbd_t *bdp;
641 struct sk_buff *skb;
642 ushort pkt_len;
643 __u8 *data;
644
645 fep = dev->priv;
646 fecp = (volatile fec_t*)dev->base_addr;
647
648 /* First, grab all of the stats for the incoming packet.
649 * These get messed up if we get called due to a busy condition.
650 */
651 bdp = fep->cur_rx;
652
653while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
654
655#ifndef final_version
656 /* Since we have allocated space to hold a complete frame,
657 * the last indicator should be set.
658 */
659 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
660 printk("FEC ENET: rcv is not +last\n");
661#endif
662
663 /* Check for errors. */
664 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
665 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
666 fep->stats.rx_errors++;
667 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
668 /* Frame too long or too short. */
669 fep->stats.rx_length_errors++;
670 }
671 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
672 fep->stats.rx_frame_errors++;
673 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
674 fep->stats.rx_crc_errors++;
675 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
676 fep->stats.rx_crc_errors++;
677 }
678
679 /* Report late collisions as a frame error.
680 * On this error, the BD is closed, but we don't know what we
681 * have in the buffer. So, just drop this frame on the floor.
682 */
683 if (bdp->cbd_sc & BD_ENET_RX_CL) {
684 fep->stats.rx_errors++;
685 fep->stats.rx_frame_errors++;
686 goto rx_processing_done;
687 }
688
689 /* Process the incoming frame.
690 */
691 fep->stats.rx_packets++;
692 pkt_len = bdp->cbd_datlen;
693 fep->stats.rx_bytes += pkt_len;
694 data = fep->rx_vaddr[bdp - fep->rx_bd_base];
695
696#ifdef CONFIG_FEC_PACKETHOOK
697 /* Packet hook ... */
698 if (fep->ph_rxhandler) {
699 if (((struct ethhdr *)data)->h_proto == fep->ph_proto) {
700 switch (fep->ph_rxhandler(data, pkt_len, regval,
701 fep->ph_priv)) {
702 case 1:
703 goto rx_processing_done;
704 break;
705 case 0:
706 break;
707 default:
708 fep->stats.rx_errors++;
709 goto rx_processing_done;
710 }
711 }
712 }
713
714 /* If it wasn't filtered - copy it to an sk buffer. */
715#endif
716
717 /* This does 16 byte alignment, exactly what we need.
718 * The packet length includes FCS, but we don't want to
719 * include that when passing upstream as it messes up
720 * bridging applications.
721 */
722 skb = dev_alloc_skb(pkt_len-4);
723
724 if (skb == NULL) {
725 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
726 fep->stats.rx_dropped++;
727 } else {
728 skb->dev = dev;
729 skb_put(skb,pkt_len-4); /* Make room */
730 eth_copy_and_sum(skb, data, pkt_len-4, 0);
731 skb->protocol=eth_type_trans(skb,dev);
732 netif_rx(skb);
733 }
734 rx_processing_done:
735
736 /* Clear the status flags for this buffer.
737 */
738 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
739
740 /* Mark the buffer empty.
741 */
742 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
743
744 /* Update BD pointer to next entry.
745 */
746 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
747 bdp = fep->rx_bd_base;
748 else
749 bdp++;
750
751#if 1
752 /* Doing this here will keep the FEC running while we process
753 * incoming frames. On a heavily loaded network, we should be
754 * able to keep up at the expense of system resources.
755 */
756 fecp->fec_r_des_active = 0x01000000;
757#endif
758#ifdef CONFIG_FEC_PACKETHOOK
759 /* Re-read register. Not exactly guaranteed to be correct,
760 but... */
761 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
762#endif
763 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
764 fep->cur_rx = (cbd_t *)bdp;
765
766#if 0
767 /* Doing this here will allow us to process all frames in the
768 * ring before the FEC is allowed to put more there. On a heavily
769 * loaded network, some frames may be lost. Unfortunately, this
770 * increases the interrupt overhead since we can potentially work
771 * our way back to the interrupt return only to come right back
772 * here.
773 */
774 fecp->fec_r_des_active = 0x01000000;
775#endif
776}
777
778
779#ifdef CONFIG_USE_MDIO
780static void
781fec_enet_mii(struct net_device *dev)
782{
783 struct fec_enet_private *fep;
784 volatile fec_t *ep;
785 mii_list_t *mip;
786 uint mii_reg;
787
788 fep = (struct fec_enet_private *)dev->priv;
789 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
790 mii_reg = ep->fec_mii_data;
791
792 if ((mip = mii_head) == NULL) {
793 printk("MII and no head!\n");
794 return;
795 }
796
797 if (mip->mii_func != NULL)
798 (*(mip->mii_func))(mii_reg, dev);
799
800 mii_head = mip->mii_next;
801 mip->mii_next = mii_free;
802 mii_free = mip;
803
804 if ((mip = mii_head) != NULL) {
805 ep->fec_mii_data = mip->mii_regval;
806
807 }
808}
809
810static int
811mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
812{
813 struct fec_enet_private *fep;
814 unsigned long flags;
815 mii_list_t *mip;
816 int retval;
817
818 /* Add PHY address to register command.
819 */
820 fep = dev->priv;
821 regval |= fep->phy_addr << 23;
822
823 retval = 0;
824
825 /* lock while modifying mii_list */
826 spin_lock_irqsave(&fep->lock, flags);
827
828 if ((mip = mii_free) != NULL) {
829 mii_free = mip->mii_next;
830 mip->mii_regval = regval;
831 mip->mii_func = func;
832 mip->mii_next = NULL;
833 if (mii_head) {
834 mii_tail->mii_next = mip;
835 mii_tail = mip;
836 } else {
837 mii_head = mii_tail = mip;
838 (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
839 }
840 } else {
841 retval = 1;
842 }
843
844 spin_unlock_irqrestore(&fep->lock, flags);
845
846 return(retval);
847}
848
849static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
850{
851 int k;
852
853 if(!c)
854 return;
855
856 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
857 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
858}
859
860static void mii_parse_sr(uint mii_reg, struct net_device *dev)
861{
862 struct fec_enet_private *fep = dev->priv;
863 volatile uint *s = &(fep->phy_status);
864
865 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
866
867 if (mii_reg & 0x0004)
868 *s |= PHY_STAT_LINK;
869 if (mii_reg & 0x0010)
870 *s |= PHY_STAT_FAULT;
871 if (mii_reg & 0x0020)
872 *s |= PHY_STAT_ANC;
873
874 fep->link = (*s & PHY_STAT_LINK) ? 1 : 0;
875}
876
877static void mii_parse_cr(uint mii_reg, struct net_device *dev)
878{
879 struct fec_enet_private *fep = dev->priv;
880 volatile uint *s = &(fep->phy_status);
881
882 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
883
884 if (mii_reg & 0x1000)
885 *s |= PHY_CONF_ANE;
886 if (mii_reg & 0x4000)
887 *s |= PHY_CONF_LOOP;
888}
889
890static void mii_parse_anar(uint mii_reg, struct net_device *dev)
891{
892 struct fec_enet_private *fep = dev->priv;
893 volatile uint *s = &(fep->phy_status);
894
895 *s &= ~(PHY_CONF_SPMASK);
896
897 if (mii_reg & 0x0020)
898 *s |= PHY_CONF_10HDX;
899 if (mii_reg & 0x0040)
900 *s |= PHY_CONF_10FDX;
901 if (mii_reg & 0x0080)
902 *s |= PHY_CONF_100HDX;
903 if (mii_reg & 0x00100)
904 *s |= PHY_CONF_100FDX;
905}
906#if 0
907static void mii_disp_reg(uint mii_reg, struct net_device *dev)
908{
909 printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff);
910}
911#endif
912
913/* ------------------------------------------------------------------------- */
914/* The Level one LXT970 is used by many boards */
915
916#ifdef CONFIG_FEC_LXT970
917
918#define MII_LXT970_MIRROR 16 /* Mirror register */
919#define MII_LXT970_IER 17 /* Interrupt Enable Register */
920#define MII_LXT970_ISR 18 /* Interrupt Status Register */
921#define MII_LXT970_CONFIG 19 /* Configuration Register */
922#define MII_LXT970_CSR 20 /* Chip Status Register */
923
924static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
925{
926 struct fec_enet_private *fep = dev->priv;
927 volatile uint *s = &(fep->phy_status);
928
929 *s &= ~(PHY_STAT_SPMASK);
930
931 if (mii_reg & 0x0800) {
932 if (mii_reg & 0x1000)
933 *s |= PHY_STAT_100FDX;
934 else
935 *s |= PHY_STAT_100HDX;
936 }
937 else {
938 if (mii_reg & 0x1000)
939 *s |= PHY_STAT_10FDX;
940 else
941 *s |= PHY_STAT_10HDX;
942 }
943}
944
945static phy_info_t phy_info_lxt970 = {
946 0x07810000,
947 "LXT970",
948
949 (const phy_cmd_t []) { /* config */
950#if 0
951// { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
952
953 /* Set default operation of 100-TX....for some reason
954 * some of these bits are set on power up, which is wrong.
955 */
956 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
957#endif
958 { mk_mii_read(MII_REG_CR), mii_parse_cr },
959 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
960 { mk_mii_end, }
961 },
962 (const phy_cmd_t []) { /* startup - enable interrupts */
963 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
964 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
965 { mk_mii_end, }
966 },
967 (const phy_cmd_t []) { /* ack_int */
968 /* read SR and ISR to acknowledge */
969
970 { mk_mii_read(MII_REG_SR), mii_parse_sr },
971 { mk_mii_read(MII_LXT970_ISR), NULL },
972
973 /* find out the current status */
974
975 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
976 { mk_mii_end, }
977 },
978 (const phy_cmd_t []) { /* shutdown - disable interrupts */
979 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
980 { mk_mii_end, }
981 },
982};
983
984#endif /* CONFIG_FEC_LXT970 */
985
986/* ------------------------------------------------------------------------- */
987/* The Level one LXT971 is used on some of my custom boards */
988
989#ifdef CONFIG_FEC_LXT971
990
991/* register definitions for the 971 */
992
993#define MII_LXT971_PCR 16 /* Port Control Register */
994#define MII_LXT971_SR2 17 /* Status Register 2 */
995#define MII_LXT971_IER 18 /* Interrupt Enable Register */
996#define MII_LXT971_ISR 19 /* Interrupt Status Register */
997#define MII_LXT971_LCR 20 /* LED Control Register */
998#define MII_LXT971_TCR 30 /* Transmit Control Register */
999
1000/*
1001 * I had some nice ideas of running the MDIO faster...
1002 * The 971 should support 8MHz and I tried it, but things acted really
1003 * weird, so 2.5 MHz ought to be enough for anyone...
1004 */
1005
1006static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1007{
1008 struct fec_enet_private *fep = dev->priv;
1009 volatile uint *s = &(fep->phy_status);
1010
1011 *s &= ~(PHY_STAT_SPMASK);
1012
1013 if (mii_reg & 0x4000) {
1014 if (mii_reg & 0x0200)
1015 *s |= PHY_STAT_100FDX;
1016 else
1017 *s |= PHY_STAT_100HDX;
1018 }
1019 else {
1020 if (mii_reg & 0x0200)
1021 *s |= PHY_STAT_10FDX;
1022 else
1023 *s |= PHY_STAT_10HDX;
1024 }
1025 if (mii_reg & 0x0008)
1026 *s |= PHY_STAT_FAULT;
1027}
1028
1029static phy_info_t phy_info_lxt971 = {
1030 0x0001378e,
1031 "LXT971",
1032
1033 (const phy_cmd_t []) { /* config */
1034// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1035 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1036 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1037 { mk_mii_end, }
1038 },
1039 (const phy_cmd_t []) { /* startup - enable interrupts */
1040 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1041 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1042
1043 /* Somehow does the 971 tell me that the link is down
1044 * the first read after power-up.
1045 * read here to get a valid value in ack_int */
1046
1047 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1048 { mk_mii_end, }
1049 },
1050 (const phy_cmd_t []) { /* ack_int */
1051 /* find out the current status */
1052
1053 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1054 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1055
1056 /* we only need to read ISR to acknowledge */
1057
1058 { mk_mii_read(MII_LXT971_ISR), NULL },
1059 { mk_mii_end, }
1060 },
1061 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1062 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1063 { mk_mii_end, }
1064 },
1065};
1066
1067#endif /* CONFIG_FEC_LXT970 */
1068
1069
1070/* ------------------------------------------------------------------------- */
1071/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
1072
1073#ifdef CONFIG_FEC_QS6612
1074
1075/* register definitions */
1076
1077#define MII_QS6612_MCR 17 /* Mode Control Register */
1078#define MII_QS6612_FTR 27 /* Factory Test Register */
1079#define MII_QS6612_MCO 28 /* Misc. Control Register */
1080#define MII_QS6612_ISR 29 /* Interrupt Source Register */
1081#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1082#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1083
1084static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1085{
1086 struct fec_enet_private *fep = dev->priv;
1087 volatile uint *s = &(fep->phy_status);
1088
1089 *s &= ~(PHY_STAT_SPMASK);
1090
1091 switch((mii_reg >> 2) & 7) {
1092 case 1: *s |= PHY_STAT_10HDX; break;
1093 case 2: *s |= PHY_STAT_100HDX; break;
1094 case 5: *s |= PHY_STAT_10FDX; break;
1095 case 6: *s |= PHY_STAT_100FDX; break;
1096 }
1097}
1098
1099static phy_info_t phy_info_qs6612 = {
1100 0x00181440,
1101 "QS6612",
1102
1103 (const phy_cmd_t []) { /* config */
1104// { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1105
1106 /* The PHY powers up isolated on the RPX,
1107 * so send a command to allow operation.
1108 */
1109
1110 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1111
1112 /* parse cr and anar to get some info */
1113
1114 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1115 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1116 { mk_mii_end, }
1117 },
1118 (const phy_cmd_t []) { /* startup - enable interrupts */
1119 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1120 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1121 { mk_mii_end, }
1122 },
1123 (const phy_cmd_t []) { /* ack_int */
1124
1125 /* we need to read ISR, SR and ANER to acknowledge */
1126
1127 { mk_mii_read(MII_QS6612_ISR), NULL },
1128 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1129 { mk_mii_read(MII_REG_ANER), NULL },
1130
1131 /* read pcr to get info */
1132
1133 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1134 { mk_mii_end, }
1135 },
1136 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1137 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1138 { mk_mii_end, }
1139 },
1140};
1141
1142#endif /* CONFIG_FEC_QS6612 */
1143
1144/* ------------------------------------------------------------------------- */
1145/* The Advanced Micro Devices AM79C874 is used on the ICU862 */
1146
1147#ifdef CONFIG_FEC_AM79C874
1148
1149/* register definitions for the 79C874 */
1150
1151#define MII_AM79C874_MFR 16 /* Miscellaneous Features Register */
1152#define MII_AM79C874_ICSR 17 /* Interrupt Control/Status Register */
1153#define MII_AM79C874_DR 18 /* Diagnostic Register */
1154#define MII_AM79C874_PMLR 19 /* Power Management & Loopback Register */
1155#define MII_AM79C874_MCR 21 /* Mode Control Register */
1156#define MII_AM79C874_DC 23 /* Disconnect Counter */
1157#define MII_AM79C874_REC 24 /* Receiver Error Counter */
1158
1159static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data)
1160{
1161 volatile struct fec_enet_private *fep = dev->priv;
1162 uint s = fep->phy_status;
1163
1164 s &= ~(PHY_STAT_SPMASK);
1165
1166 /* Register 18: Bit 10 is data rate, 11 is Duplex */
1167 switch ((mii_reg >> 10) & 3) {
1168 case 0: s |= PHY_STAT_10HDX; break;
1169 case 1: s |= PHY_STAT_100HDX; break;
1170 case 2: s |= PHY_STAT_10FDX; break;
1171 case 3: s |= PHY_STAT_100FDX; break;
1172 }
1173
1174 fep->phy_status = s;
1175}
1176
1177static phy_info_t phy_info_amd79c874 = {
1178 0x00022561,
1179 "AM79C874",
1180
1181 (const phy_cmd_t []) { /* config */
1182// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1183 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1184 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1185 { mk_mii_end, }
1186 },
1187 (const phy_cmd_t []) { /* startup - enable interrupts */
1188 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1189 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1190 { mk_mii_end, }
1191 },
1192 (const phy_cmd_t []) { /* ack_int */
1193 /* find out the current status */
1194
1195 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1196 { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr },
1197
1198 /* we only need to read ICSR to acknowledge */
1199
1200 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1201 { mk_mii_end, }
1202 },
1203 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1204 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1205 { mk_mii_end, }
1206 },
1207};
1208
1209#endif /* CONFIG_FEC_AM79C874 */
1210
1211static phy_info_t *phy_info[] = {
1212
1213#ifdef CONFIG_FEC_LXT970
1214 &phy_info_lxt970,
1215#endif /* CONFIG_FEC_LXT970 */
1216
1217#ifdef CONFIG_FEC_LXT971
1218 &phy_info_lxt971,
1219#endif /* CONFIG_FEC_LXT971 */
1220
1221#ifdef CONFIG_FEC_QS6612
1222 &phy_info_qs6612,
1223#endif /* CONFIG_FEC_QS6612 */
1224
1225#ifdef CONFIG_FEC_AM79C874
1226 &phy_info_amd79c874,
1227#endif /* CONFIG_FEC_AM79C874 */
1228
1229 NULL
1230};
1231
1232static void mii_display_status(struct net_device *dev)
1233{
1234 struct fec_enet_private *fep = dev->priv;
1235 volatile uint *s = &(fep->phy_status);
1236
1237 if (!fep->link && !fep->old_link) {
1238 /* Link is still down - don't print anything */
1239 return;
1240 }
1241
1242 printk("%s: status: ", dev->name);
1243
1244 if (!fep->link) {
1245 printk("link down");
1246 } else {
1247 printk("link up");
1248
1249 switch(*s & PHY_STAT_SPMASK) {
1250 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1251 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1252 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1253 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1254 default:
1255 printk(", Unknown speed/duplex");
1256 }
1257
1258 if (*s & PHY_STAT_ANC)
1259 printk(", auto-negotiation complete");
1260 }
1261
1262 if (*s & PHY_STAT_FAULT)
1263 printk(", remote fault");
1264
1265 printk(".\n");
1266}
1267
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001268static void mii_display_config(void *priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269{
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001270 struct net_device *dev = (struct net_device *)priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271 struct fec_enet_private *fep = dev->priv;
1272 volatile uint *s = &(fep->phy_status);
1273
1274 printk("%s: config: auto-negotiation ", dev->name);
1275
1276 if (*s & PHY_CONF_ANE)
1277 printk("on");
1278 else
1279 printk("off");
1280
1281 if (*s & PHY_CONF_100FDX)
1282 printk(", 100FDX");
1283 if (*s & PHY_CONF_100HDX)
1284 printk(", 100HDX");
1285 if (*s & PHY_CONF_10FDX)
1286 printk(", 10FDX");
1287 if (*s & PHY_CONF_10HDX)
1288 printk(", 10HDX");
1289 if (!(*s & PHY_CONF_SPMASK))
1290 printk(", No speed/duplex selected?");
1291
1292 if (*s & PHY_CONF_LOOP)
1293 printk(", loopback enabled");
1294
1295 printk(".\n");
1296
1297 fep->sequence_done = 1;
1298}
1299
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001300static void mii_relink(void *priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301{
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001302 struct net_device *dev = (struct net_device *)priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303 struct fec_enet_private *fep = dev->priv;
1304 int duplex;
1305
1306 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1307 mii_display_status(dev);
1308 fep->old_link = fep->link;
1309
1310 if (fep->link) {
1311 duplex = 0;
1312 if (fep->phy_status
1313 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1314 duplex = 1;
1315 fec_restart(dev, duplex);
1316 }
1317 else
1318 fec_stop(dev);
1319
1320#if 0
1321 enable_irq(fep->mii_irq);
1322#endif
1323
1324}
1325
1326static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1327{
1328 struct fec_enet_private *fep = dev->priv;
1329
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001330 INIT_WORK(&fep->phy_task, mii_relink, (void *)dev);
1331 schedule_work(&fep->phy_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332}
1333
1334static void mii_queue_config(uint mii_reg, struct net_device *dev)
1335{
1336 struct fec_enet_private *fep = dev->priv;
1337
Aristeu Sergio Rozanski Filho8b0ed2f2005-08-07 09:42:28 -07001338 INIT_WORK(&fep->phy_task, mii_display_config, (void *)dev);
1339 schedule_work(&fep->phy_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340}
1341
1342
1343
1344phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1345 { mk_mii_end, } };
1346phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1347 { mk_mii_end, } };
1348
1349
1350
1351/* Read remainder of PHY ID.
1352*/
1353static void
1354mii_discover_phy3(uint mii_reg, struct net_device *dev)
1355{
1356 struct fec_enet_private *fep;
1357 int i;
1358
1359 fep = dev->priv;
1360 fep->phy_id |= (mii_reg & 0xffff);
1361
1362 for(i = 0; phy_info[i]; i++)
1363 if(phy_info[i]->id == (fep->phy_id >> 4))
1364 break;
1365
1366 if(!phy_info[i])
1367 panic("%s: PHY id 0x%08x is not supported!\n",
1368 dev->name, fep->phy_id);
1369
1370 fep->phy = phy_info[i];
1371 fep->phy_id_done = 1;
1372
1373 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1374 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1375}
1376
1377/* Scan all of the MII PHY addresses looking for someone to respond
1378 * with a valid ID. This usually happens quickly.
1379 */
1380static void
1381mii_discover_phy(uint mii_reg, struct net_device *dev)
1382{
1383 struct fec_enet_private *fep;
1384 uint phytype;
1385
1386 fep = dev->priv;
1387
1388 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1389
1390 /* Got first part of ID, now get remainder.
1391 */
1392 fep->phy_id = phytype << 16;
1393 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1394 } else {
1395 fep->phy_addr++;
1396 if (fep->phy_addr < 32) {
1397 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1398 mii_discover_phy);
1399 } else {
1400 printk("fec: No PHY device found.\n");
1401 }
1402 }
1403}
1404#endif /* CONFIG_USE_MDIO */
1405
1406/* This interrupt occurs when the PHY detects a link change.
1407*/
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -07001408static
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409#ifdef CONFIG_RPXCLASSIC
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -07001410void mii_link_interrupt(void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411#else
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -07001412irqreturn_t mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413#endif
1414{
1415#ifdef CONFIG_USE_MDIO
1416 struct net_device *dev = dev_id;
1417 struct fec_enet_private *fep = dev->priv;
1418 volatile immap_t *immap = (immap_t *)IMAP_ADDR;
1419 volatile fec_t *fecp = &(immap->im_cpm.cp_fec);
1420 unsigned int ecntrl = fecp->fec_ecntrl;
1421
1422 /* We need the FEC enabled to access the MII
1423 */
1424 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1425 fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN;
1426 }
1427#endif /* CONFIG_USE_MDIO */
1428
1429#if 0
1430 disable_irq(fep->mii_irq); /* disable now, enable later */
1431#endif
1432
1433
1434#ifdef CONFIG_USE_MDIO
1435 mii_do_cmd(dev, fep->phy->ack_int);
1436 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1437
1438 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1439 fecp->fec_ecntrl = ecntrl; /* restore old settings */
1440 }
1441#else
1442printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
1443#endif /* CONFIG_USE_MDIO */
1444
Aristeu Sergio Rozanski Filhofbccb3d2005-08-07 09:42:36 -07001445#ifndef CONFIG_RPXCLASSIC
1446 return IRQ_RETVAL(IRQ_HANDLED);
1447#endif /* CONFIG_RPXCLASSIC */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448}
1449
1450static int
1451fec_enet_open(struct net_device *dev)
1452{
1453 struct fec_enet_private *fep = dev->priv;
1454
1455 /* I should reset the ring buffers here, but I don't yet know
1456 * a simple way to do that.
1457 */
1458
1459#ifdef CONFIG_USE_MDIO
1460 fep->sequence_done = 0;
1461 fep->link = 0;
1462
1463 if (fep->phy) {
1464 mii_do_cmd(dev, fep->phy->ack_int);
1465 mii_do_cmd(dev, fep->phy->config);
1466 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1467 while(!fep->sequence_done)
1468 schedule();
1469
1470 mii_do_cmd(dev, fep->phy->startup);
1471 netif_start_queue(dev);
1472 return 0; /* Success */
1473 }
1474 return -ENODEV; /* No PHY we understand */
1475#else
1476 fep->link = 1;
1477 netif_start_queue(dev);
1478 return 0; /* Success */
1479#endif /* CONFIG_USE_MDIO */
1480
1481}
1482
1483static int
1484fec_enet_close(struct net_device *dev)
1485{
1486 /* Don't know what to do yet.
1487 */
1488 netif_stop_queue(dev);
1489 fec_stop(dev);
1490
1491 return 0;
1492}
1493
1494static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1495{
1496 struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv;
1497
1498 return &fep->stats;
1499}
1500
1501/* Set or clear the multicast filter for this adaptor.
1502 * Skeleton taken from sunlance driver.
1503 * The CPM Ethernet implementation allows Multicast as well as individual
1504 * MAC address filtering. Some of the drivers check to make sure it is
1505 * a group multicast address, and discard those that are not. I guess I
1506 * will do the same for now, but just remove the test if you want
1507 * individual filtering as well (do the upper net layers want or support
1508 * this kind of feature?).
1509 */
1510
1511static void set_multicast_list(struct net_device *dev)
1512{
1513 struct fec_enet_private *fep;
1514 volatile fec_t *ep;
1515
1516 fep = (struct fec_enet_private *)dev->priv;
1517 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
1518
1519 if (dev->flags&IFF_PROMISC) {
1520
1521 /* Log any net taps. */
1522 printk("%s: Promiscuous mode enabled.\n", dev->name);
1523 ep->fec_r_cntrl |= FEC_RCNTRL_PROM;
1524 } else {
1525
1526 ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM;
1527
1528 if (dev->flags & IFF_ALLMULTI) {
1529 /* Catch all multicast addresses, so set the
1530 * filter to all 1's.
1531 */
1532 ep->fec_hash_table_high = 0xffffffff;
1533 ep->fec_hash_table_low = 0xffffffff;
1534 }
1535#if 0
1536 else {
1537 /* Clear filter and add the addresses in the list.
1538 */
1539 ep->sen_gaddr1 = 0;
1540 ep->sen_gaddr2 = 0;
1541 ep->sen_gaddr3 = 0;
1542 ep->sen_gaddr4 = 0;
1543
1544 dmi = dev->mc_list;
1545
1546 for (i=0; i<dev->mc_count; i++) {
1547
1548 /* Only support group multicast for now.
1549 */
1550 if (!(dmi->dmi_addr[0] & 1))
1551 continue;
1552
1553 /* The address in dmi_addr is LSB first,
1554 * and taddr is MSB first. We have to
1555 * copy bytes MSB first from dmi_addr.
1556 */
1557 mcptr = (u_char *)dmi->dmi_addr + 5;
1558 tdptr = (u_char *)&ep->sen_taddrh;
1559 for (j=0; j<6; j++)
1560 *tdptr++ = *mcptr--;
1561
1562 /* Ask CPM to run CRC and set bit in
1563 * filter mask.
1564 */
1565 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG;
1566 /* this delay is necessary here -- Cort */
1567 udelay(10);
1568 while (cpmp->cp_cpcr & CPM_CR_FLG);
1569 }
1570 }
1571#endif
1572 }
1573}
1574
1575/* Initialize the FEC Ethernet on 860T.
1576 */
1577static int __init fec_enet_init(void)
1578{
1579 struct net_device *dev;
1580 struct fec_enet_private *fep;
1581 int i, j, k, err;
1582 unsigned char *eap, *iap, *ba;
Aristeu Sergio Rozanski Filhofc007dd2005-08-07 09:42:33 -07001583 dma_addr_t mem_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584 volatile cbd_t *bdp;
1585 cbd_t *cbd_base;
1586 volatile immap_t *immap;
1587 volatile fec_t *fecp;
1588 bd_t *bd;
1589#ifdef CONFIG_SCC_ENET
1590 unsigned char tmpaddr[6];
1591#endif
1592
1593 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1594
1595 bd = (bd_t *)__res;
1596
1597 dev = alloc_etherdev(sizeof(*fep));
1598 if (!dev)
1599 return -ENOMEM;
1600
1601 fep = dev->priv;
1602
1603 fecp = &(immap->im_cpm.cp_fec);
1604
1605 /* Whack a reset. We should wait for this.
1606 */
1607 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1608 for (i = 0;
1609 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1610 ++i) {
1611 udelay(1);
1612 }
1613 if (i == FEC_RESET_DELAY) {
1614 printk ("FEC Reset timeout!\n");
1615 }
1616
1617 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1618 * this needs some work to get unique addresses.
1619 */
1620 eap = (unsigned char *)my_enet_addr;
1621 iap = bd->bi_enetaddr;
1622
1623#ifdef CONFIG_SCC_ENET
1624 /*
1625 * If a board has Ethernet configured both on a SCC and the
1626 * FEC, it needs (at least) 2 MAC addresses (we know that Sun
1627 * disagrees, but anyway). For the FEC port, we create
1628 * another address by setting one of the address bits above
1629 * something that would have (up to now) been allocated.
1630 */
1631 for (i=0; i<6; i++)
1632 tmpaddr[i] = *iap++;
1633 tmpaddr[3] |= 0x80;
1634 iap = tmpaddr;
1635#endif
1636
1637 for (i=0; i<6; i++) {
1638 dev->dev_addr[i] = *eap++ = *iap++;
1639 }
1640
1641 /* Allocate memory for buffer descriptors.
1642 */
1643 if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1644 printk("FEC init error. Need more space.\n");
1645 printk("FEC initialization failed.\n");
1646 return 1;
1647 }
Aristeu Sergio Rozanski Filhofc007dd2005-08-07 09:42:33 -07001648 cbd_base = (cbd_t *)dma_alloc_coherent(dev->class_dev.dev, PAGE_SIZE,
1649 &mem_addr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650
1651 /* Set receive and transmit descriptor base.
1652 */
1653 fep->rx_bd_base = cbd_base;
1654 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1655
1656 fep->skb_cur = fep->skb_dirty = 0;
1657
1658 /* Initialize the receive buffer descriptors.
1659 */
1660 bdp = fep->rx_bd_base;
1661 k = 0;
1662 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1663
1664 /* Allocate a page.
1665 */
Aristeu Sergio Rozanski Filhofc007dd2005-08-07 09:42:33 -07001666 ba = (unsigned char *)dma_alloc_coherent(dev->class_dev.dev,
1667 PAGE_SIZE,
1668 &mem_addr,
1669 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001670 /* BUG: no check for failure */
1671
1672 /* Initialize the BD for every fragment in the page.
1673 */
1674 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1675 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1676 bdp->cbd_bufaddr = mem_addr;
1677 fep->rx_vaddr[k++] = ba;
1678 mem_addr += FEC_ENET_RX_FRSIZE;
1679 ba += FEC_ENET_RX_FRSIZE;
1680 bdp++;
1681 }
1682 }
1683
1684 /* Set the last buffer to wrap.
1685 */
1686 bdp--;
1687 bdp->cbd_sc |= BD_SC_WRAP;
1688
1689#ifdef CONFIG_FEC_PACKETHOOK
1690 fep->ph_lock = 0;
1691 fep->ph_rxhandler = fep->ph_txhandler = NULL;
1692 fep->ph_proto = 0;
1693 fep->ph_regaddr = NULL;
1694 fep->ph_priv = NULL;
1695#endif
1696
1697 /* Install our interrupt handler.
1698 */
1699 if (request_irq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1700 panic("Could not allocate FEC IRQ!");
1701
1702#ifdef CONFIG_RPXCLASSIC
1703 /* Make Port C, bit 15 an input that causes interrupts.
1704 */
1705 immap->im_ioport.iop_pcpar &= ~0x0001;
1706 immap->im_ioport.iop_pcdir &= ~0x0001;
1707 immap->im_ioport.iop_pcso &= ~0x0001;
1708 immap->im_ioport.iop_pcint |= 0x0001;
1709 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1710
1711 /* Make LEDS reflect Link status.
1712 */
1713 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1714#endif
1715
1716#ifdef PHY_INTERRUPT
1717 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
1718 (0x80000000 >> PHY_INTERRUPT);
1719
1720 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0)
1721 panic("Could not allocate MII IRQ!");
1722#endif
1723
1724 dev->base_addr = (unsigned long)fecp;
1725
1726 /* The FEC Ethernet specific entries in the device structure. */
1727 dev->open = fec_enet_open;
1728 dev->hard_start_xmit = fec_enet_start_xmit;
1729 dev->tx_timeout = fec_timeout;
1730 dev->watchdog_timeo = TX_TIMEOUT;
1731 dev->stop = fec_enet_close;
1732 dev->get_stats = fec_enet_get_stats;
1733 dev->set_multicast_list = set_multicast_list;
1734
1735#ifdef CONFIG_USE_MDIO
1736 for (i=0; i<NMII-1; i++)
1737 mii_cmds[i].mii_next = &mii_cmds[i+1];
1738 mii_free = mii_cmds;
1739#endif /* CONFIG_USE_MDIO */
1740
1741 /* Configure all of port D for MII.
1742 */
1743 immap->im_ioport.iop_pdpar = 0x1fff;
1744
1745 /* Bits moved from Rev. D onward.
1746 */
1747 if ((mfspr(SPRN_IMMR) & 0xffff) < 0x0501)
1748 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1749 else
1750 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1751
1752#ifdef CONFIG_USE_MDIO
1753 /* Set MII speed to 2.5 MHz
1754 */
1755 fecp->fec_mii_speed = fep->phy_speed =
1756 (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1;
1757#else
1758 fecp->fec_mii_speed = 0; /* turn off MDIO */
1759#endif /* CONFIG_USE_MDIO */
1760
1761 err = register_netdev(dev);
1762 if (err) {
1763 free_netdev(dev);
1764 return err;
1765 }
1766
1767 printk ("%s: FEC ENET Version 0.2, FEC irq %d"
1768#ifdef PHY_INTERRUPT
1769 ", MII irq %d"
1770#endif
1771 ", addr ",
1772 dev->name, FEC_INTERRUPT
1773#ifdef PHY_INTERRUPT
1774 , PHY_INTERRUPT
1775#endif
1776 );
1777 for (i=0; i<6; i++)
1778 printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':');
1779
1780#ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */
1781 fec_restart (dev, 1);
1782#else /* always use half duplex mode only */
1783 fec_restart (dev, 0);
1784#endif
1785
1786#ifdef CONFIG_USE_MDIO
1787 /* Queue up command to detect the PHY and initialize the
1788 * remainder of the interface.
1789 */
1790 fep->phy_id_done = 0;
1791 fep->phy_addr = 0;
1792 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1793#endif /* CONFIG_USE_MDIO */
1794
1795 return 0;
1796}
1797module_init(fec_enet_init);
1798
1799/* This function is called to start or restart the FEC during a link
1800 * change. This only happens when switching between half and full
1801 * duplex.
1802 */
1803static void
1804fec_restart(struct net_device *dev, int duplex)
1805{
1806 struct fec_enet_private *fep;
1807 int i;
1808 volatile cbd_t *bdp;
1809 volatile immap_t *immap;
1810 volatile fec_t *fecp;
1811
1812 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1813
1814 fecp = &(immap->im_cpm.cp_fec);
1815
1816 fep = dev->priv;
1817
1818 /* Whack a reset. We should wait for this.
1819 */
1820 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1821 for (i = 0;
1822 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1823 ++i) {
1824 udelay(1);
1825 }
1826 if (i == FEC_RESET_DELAY) {
1827 printk ("FEC Reset timeout!\n");
1828 }
1829
1830 /* Set station address.
1831 */
1832 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1833 fecp->fec_addr_high = my_enet_addr[2];
1834
1835 /* Reset all multicast.
1836 */
1837 fecp->fec_hash_table_high = 0;
1838 fecp->fec_hash_table_low = 0;
1839
1840 /* Set maximum receive buffer size.
1841 */
1842 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1843 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1844
1845 /* Set receive and transmit descriptor base.
1846 */
1847 fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base));
1848 fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base));
1849
1850 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1851 fep->cur_rx = fep->rx_bd_base;
1852
1853 /* Reset SKB transmit buffers.
1854 */
1855 fep->skb_cur = fep->skb_dirty = 0;
1856 for (i=0; i<=TX_RING_MOD_MASK; i++) {
1857 if (fep->tx_skbuff[i] != NULL) {
1858 dev_kfree_skb(fep->tx_skbuff[i]);
1859 fep->tx_skbuff[i] = NULL;
1860 }
1861 }
1862
1863 /* Initialize the receive buffer descriptors.
1864 */
1865 bdp = fep->rx_bd_base;
1866 for (i=0; i<RX_RING_SIZE; i++) {
1867
1868 /* Initialize the BD for every fragment in the page.
1869 */
1870 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1871 bdp++;
1872 }
1873
1874 /* Set the last buffer to wrap.
1875 */
1876 bdp--;
1877 bdp->cbd_sc |= BD_SC_WRAP;
1878
1879 /* ...and the same for transmmit.
1880 */
1881 bdp = fep->tx_bd_base;
1882 for (i=0; i<TX_RING_SIZE; i++) {
1883
1884 /* Initialize the BD for every fragment in the page.
1885 */
1886 bdp->cbd_sc = 0;
1887 bdp->cbd_bufaddr = 0;
1888 bdp++;
1889 }
1890
1891 /* Set the last buffer to wrap.
1892 */
1893 bdp--;
1894 bdp->cbd_sc |= BD_SC_WRAP;
1895
1896 /* Enable MII mode.
1897 */
1898 if (duplex) {
1899 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */
1900 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */
1901 }
1902 else {
1903 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
1904 fecp->fec_x_cntrl = 0;
1905 }
1906 fep->full_duplex = duplex;
1907
1908 /* Enable big endian and don't care about SDMA FC.
1909 */
1910 fecp->fec_fun_code = 0x78000000;
1911
1912#ifdef CONFIG_USE_MDIO
1913 /* Set MII speed.
1914 */
1915 fecp->fec_mii_speed = fep->phy_speed;
1916#endif /* CONFIG_USE_MDIO */
1917
1918 /* Clear any outstanding interrupt.
1919 */
1920 fecp->fec_ievent = 0xffc0;
1921
1922 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1923
1924 /* Enable interrupts we wish to service.
1925 */
1926 fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB |
1927 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII );
1928
1929 /* And last, enable the transmit and receive processing.
1930 */
1931 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
1932 fecp->fec_r_des_active = 0x01000000;
1933}
1934
1935static void
1936fec_stop(struct net_device *dev)
1937{
1938 volatile immap_t *immap;
1939 volatile fec_t *fecp;
1940 struct fec_enet_private *fep;
1941 int i;
1942
1943 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1944
1945 fecp = &(immap->im_cpm.cp_fec);
1946
1947 if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0)
1948 return; /* already down */
1949
1950 fep = dev->priv;
1951
1952
1953 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
1954
1955 for (i = 0;
1956 ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY);
1957 ++i) {
1958 udelay(1);
1959 }
1960 if (i == FEC_RESET_DELAY) {
1961 printk ("FEC timeout on graceful transmit stop\n");
1962 }
1963
1964 /* Clear outstanding MII command interrupts.
1965 */
1966 fecp->fec_ievent = FEC_ENET_MII;
1967
1968 /* Enable MII command finished interrupt
1969 */
1970 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1971 fecp->fec_imask = FEC_ENET_MII;
1972
1973#ifdef CONFIG_USE_MDIO
1974 /* Set MII speed.
1975 */
1976 fecp->fec_mii_speed = fep->phy_speed;
1977#endif /* CONFIG_USE_MDIO */
1978
1979 /* Disable FEC
1980 */
1981 fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN);
1982}