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review.evervolv.com / android_kernel_htc_msm8960 / dc1a94ae1749d14c55f8b54e9d92bd89df82d51a / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: 914168105297b657f952f654b81ddb02531548bb [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]11 * mpi2.h Version: 02.00.13
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]56 * --------------------------------------------------------------------------
57 */
58
59#ifndef MPI2_H
60#define MPI2_H
61
62
63/*****************************************************************************
64*
65* MPI Version Definitions
66*
67*****************************************************************************/
68
69#define MPI2_VERSION_MAJOR (0x02)
70#define MPI2_VERSION_MINOR (0x00)
71#define MPI2_VERSION_MAJOR_MASK (0xFF00)
72#define MPI2_VERSION_MAJOR_SHIFT (8)
73#define MPI2_VERSION_MINOR_MASK (0x00FF)
74#define MPI2_VERSION_MINOR_SHIFT (0)
75#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
76 MPI2_VERSION_MINOR)
77
78#define MPI2_VERSION_02_00 (0x0200)
79
80/* versioning for this MPI header set */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]81#define MPI2_HEADER_VERSION_UNIT (0x0D)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]82#define MPI2_HEADER_VERSION_DEV (0x00)
83#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
84#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
85#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
86#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
87#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
88
89
90/*****************************************************************************
91*
92* IOC State Definitions
93*
94*****************************************************************************/
95
96#define MPI2_IOC_STATE_RESET (0x00000000)
97#define MPI2_IOC_STATE_READY (0x10000000)
98#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
99#define MPI2_IOC_STATE_FAULT (0x40000000)
100
101#define MPI2_IOC_STATE_MASK (0xF0000000)
102#define MPI2_IOC_STATE_SHIFT (28)
103
104/* Fault state range for prodcut specific codes */
105#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
106#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
107
108
109/*****************************************************************************
110*
111* System Interface Register Definitions
112*
113*****************************************************************************/
114
115typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
116{
117 U32 Doorbell; /* 0x00 */
118 U32 WriteSequence; /* 0x04 */
119 U32 HostDiagnostic; /* 0x08 */
120 U32 Reserved1; /* 0x0C */
121 U32 DiagRWData; /* 0x10 */
122 U32 DiagRWAddressLow; /* 0x14 */
123 U32 DiagRWAddressHigh; /* 0x18 */
124 U32 Reserved2[5]; /* 0x1C */
125 U32 HostInterruptStatus; /* 0x30 */
126 U32 HostInterruptMask; /* 0x34 */
127 U32 DCRData; /* 0x38 */
128 U32 DCRAddress; /* 0x3C */
129 U32 Reserved3[2]; /* 0x40 */
130 U32 ReplyFreeHostIndex; /* 0x48 */
131 U32 Reserved4[8]; /* 0x4C */
132 U32 ReplyPostHostIndex; /* 0x6C */
133 U32 Reserved5; /* 0x70 */
134 U32 HCBSize; /* 0x74 */
135 U32 HCBAddressLow; /* 0x78 */
136 U32 HCBAddressHigh; /* 0x7C */
137 U32 Reserved6[16]; /* 0x80 */
138 U32 RequestDescriptorPostLow; /* 0xC0 */
139 U32 RequestDescriptorPostHigh; /* 0xC4 */
140 U32 Reserved7[14]; /* 0xC8 */
141} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
142 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
143
144/*
145 * Defines for working with the Doorbell register.
146 */
147#define MPI2_DOORBELL_OFFSET (0x00000000)
148
149/* IOC --> System values */
150#define MPI2_DOORBELL_USED (0x08000000)
151#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
152#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
153#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
154#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
155
156/* System --> IOC values */
157#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
158#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
159#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
160#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
161
162
163/*
164 * Defines for the WriteSequence register
165 */
166#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
167#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
168#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
169#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
170#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
171#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
172#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
173#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
174#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
175
176/*
177 * Defines for the HostDiagnostic register
178 */
179#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
180
181#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
182#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
183#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
184
185#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
186#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
187#define MPI2_DIAG_HCB_MODE (0x00000100)
188#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
189#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
190#define MPI2_DIAG_RESET_HISTORY (0x00000020)
191#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
192#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
193#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
194
195/*
196 * Offsets for DiagRWData and address
197 */
198#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
199#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
200#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
201
202/*
203 * Defines for the HostInterruptStatus register
204 */
205#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
206#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
207#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
208#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
209#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
210#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
211#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
212
213/*
214 * Defines for the HostInterruptMask register
215 */
216#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
217#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
218#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
219#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
220#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
221#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
222
223/*
224 * Offsets for DCRData and address
225 */
226#define MPI2_DCR_DATA_OFFSET (0x00000038)
227#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
228
229/*
230 * Offset for the Reply Free Queue
231 */
232#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
233
234/*
235 * Offset for the Reply Descriptor Post Queue
236 */
237#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
238
239/*
240 * Defines for the HCBSize and address
241 */
242#define MPI2_HCB_SIZE_OFFSET (0x00000074)
243#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
244#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
245
246#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
247#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
248
249/*
250 * Offsets for the Request Queue
251 */
252#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
253#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
254
255
256/*****************************************************************************
257*
258* Message Descriptors
259*
260*****************************************************************************/
261
262/* Request Descriptors */
263
264/* Default Request Descriptor */
265typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
266{
267 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]268 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]269 U16 SMID; /* 0x02 */
270 U16 LMID; /* 0x04 */
271 U16 DescriptorTypeDependent; /* 0x06 */
272} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
273 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
274 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
275
276/* defines for the RequestFlags field */
277#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
278#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
279#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
280#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
281#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]282#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]283
284#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
285
286
287/* High Priority Request Descriptor */
288typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
289{
290 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]291 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]292 U16 SMID; /* 0x02 */
293 U16 LMID; /* 0x04 */
294 U16 Reserved1; /* 0x06 */
295} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
296 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
297 Mpi2HighPriorityRequestDescriptor_t,
298 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
299
300
301/* SCSI IO Request Descriptor */
302typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
303{
304 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]305 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]306 U16 SMID; /* 0x02 */
307 U16 LMID; /* 0x04 */
308 U16 DevHandle; /* 0x06 */
309} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
310 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
311 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
312
313
314/* SCSI Target Request Descriptor */
315typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
316{
317 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]318 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]319 U16 SMID; /* 0x02 */
320 U16 LMID; /* 0x04 */
321 U16 IoIndex; /* 0x06 */
322} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
323 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
324 Mpi2SCSITargetRequestDescriptor_t,
325 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
326
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]327
328/* RAID Accelerator Request Descriptor */
329typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
330 U8 RequestFlags; /* 0x00 */
331 U8 MSIxIndex; /* 0x01 */
332 U16 SMID; /* 0x02 */
333 U16 LMID; /* 0x04 */
334 U16 Reserved; /* 0x06 */
335} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
336 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
337 Mpi2RAIDAcceleratorRequestDescriptor_t,
338 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
339
340
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]341/* union of Request Descriptors */
342typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
343{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]344 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
345 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
346 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
347 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
348 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
349 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]350} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
351 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
352
353
354/* Reply Descriptors */
355
356/* Default Reply Descriptor */
357typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
358{
359 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]360 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]361 U16 DescriptorTypeDependent1; /* 0x02 */
362 U32 DescriptorTypeDependent2; /* 0x04 */
363} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
364 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
365
366/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]367#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
368#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
369#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
370#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
371#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
372#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
373#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]374
375/* values for marking a reply descriptor as unused */
376#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
377#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
378
379/* Address Reply Descriptor */
380typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
381{
382 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]383 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]384 U16 SMID; /* 0x02 */
385 U32 ReplyFrameAddress; /* 0x04 */
386} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
387 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
388
389#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
390
391
392/* SCSI IO Success Reply Descriptor */
393typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
394{
395 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]396 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]397 U16 SMID; /* 0x02 */
398 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]399 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]400} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
401 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
402 Mpi2SCSIIOSuccessReplyDescriptor_t,
403 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
404
405
406/* TargetAssist Success Reply Descriptor */
407typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
408{
409 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]410 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]411 U16 SMID; /* 0x02 */
412 U8 SequenceNumber; /* 0x04 */
413 U8 Reserved1; /* 0x05 */
414 U16 IoIndex; /* 0x06 */
415} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
416 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
417 Mpi2TargetAssistSuccessReplyDescriptor_t,
418 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
419
420
421/* Target Command Buffer Reply Descriptor */
422typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
423{
424 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]425 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]426 U8 VP_ID; /* 0x02 */
427 U8 Flags; /* 0x03 */
428 U16 InitiatorDevHandle; /* 0x04 */
429 U16 IoIndex; /* 0x06 */
430} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
431 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
432 Mpi2TargetCommandBufferReplyDescriptor_t,
433 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
434
435/* defines for Flags field */
436#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
437
438
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]439/* RAID Accelerator Success Reply Descriptor */
440typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
441 U8 ReplyFlags; /* 0x00 */
442 U8 MSIxIndex; /* 0x01 */
443 U16 SMID; /* 0x02 */
444 U32 Reserved; /* 0x04 */
445} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
446 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
447 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
448 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
449
450
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]451/* union of Reply Descriptors */
452typedef union _MPI2_REPLY_DESCRIPTORS_UNION
453{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]454 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
455 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
456 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
457 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
458 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
459 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
460 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]461} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
462 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
463
464
465
466/*****************************************************************************
467*
468* Message Functions
469* 0x80 -> 0x8F reserved for private message use per product
470*
471*
472*****************************************************************************/
473
474#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
475#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
476#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
477#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
478#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
479#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
480#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
481#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
482#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
483#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
484#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
485#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
486#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
487#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
488#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
489#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
490#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
491#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
492#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
493#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
494#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
495#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
496#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
497#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
498#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]499#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]500
501
502
503/* Doorbell functions */
504#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
505/* #define MPI2_FUNCTION_IO_UNIT_RESET (0x41) */
506#define MPI2_FUNCTION_HANDSHAKE (0x42)
507
508
509/*****************************************************************************
510*
511* IOC Status Values
512*
513*****************************************************************************/
514
515/* mask for IOCStatus status value */
516#define MPI2_IOCSTATUS_MASK (0x7FFF)
517
518/****************************************************************************
519* Common IOCStatus values for all replies
520****************************************************************************/
521
522#define MPI2_IOCSTATUS_SUCCESS (0x0000)
523#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
524#define MPI2_IOCSTATUS_BUSY (0x0002)
525#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
526#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
527#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
528#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
529#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
530#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
531#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
532
533/****************************************************************************
534* Config IOCStatus values
535****************************************************************************/
536
537#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
538#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
539#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
540#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
541#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
542#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
543
544/****************************************************************************
545* SCSI IO Reply
546****************************************************************************/
547
548#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
549#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
550#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
551#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
552#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
553#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
554#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
555#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
556#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
557#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
558#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
559#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
560
561/****************************************************************************
562* For use by SCSI Initiator and SCSI Target end-to-end data protection
563****************************************************************************/
564
565#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
566#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
567#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
568
569/****************************************************************************
570* SCSI Target values
571****************************************************************************/
572
573#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
574#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
575#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
576#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
577#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
578#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
579#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
580#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
581#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
582#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
583
584/****************************************************************************
585* Serial Attached SCSI values
586****************************************************************************/
587
588#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
589#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
590
591/****************************************************************************
592* Diagnostic Buffer Post / Diagnostic Release values
593****************************************************************************/
594
595#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
596
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]597/****************************************************************************
598* RAID Accelerator values
599****************************************************************************/
600
601#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]602
603/****************************************************************************
604* IOCStatus flag to indicate that log info is available
605****************************************************************************/
606
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]607#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]608
609/****************************************************************************
610* IOCLogInfo Types
611****************************************************************************/
612
613#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
614#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
615#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
616#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
617#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
618#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
619#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
620#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
621
622
623/*****************************************************************************
624*
625* Standard Message Structures
626*
627*****************************************************************************/
628
629/****************************************************************************
630* Request Message Header for all request messages
631****************************************************************************/
632
633typedef struct _MPI2_REQUEST_HEADER
634{
635 U16 FunctionDependent1; /* 0x00 */
636 U8 ChainOffset; /* 0x02 */
637 U8 Function; /* 0x03 */
638 U16 FunctionDependent2; /* 0x04 */
639 U8 FunctionDependent3; /* 0x06 */
640 U8 MsgFlags; /* 0x07 */
641 U8 VP_ID; /* 0x08 */
642 U8 VF_ID; /* 0x09 */
643 U16 Reserved1; /* 0x0A */
644} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
645 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
646
647
648/****************************************************************************
649* Default Reply
650****************************************************************************/
651
652typedef struct _MPI2_DEFAULT_REPLY
653{
654 U16 FunctionDependent1; /* 0x00 */
655 U8 MsgLength; /* 0x02 */
656 U8 Function; /* 0x03 */
657 U16 FunctionDependent2; /* 0x04 */
658 U8 FunctionDependent3; /* 0x06 */
659 U8 MsgFlags; /* 0x07 */
660 U8 VP_ID; /* 0x08 */
661 U8 VF_ID; /* 0x09 */
662 U16 Reserved1; /* 0x0A */
663 U16 FunctionDependent5; /* 0x0C */
664 U16 IOCStatus; /* 0x0E */
665 U32 IOCLogInfo; /* 0x10 */
666} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
667 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
668
669
670/* common version structure/union used in messages and configuration pages */
671
672typedef struct _MPI2_VERSION_STRUCT
673{
674 U8 Dev; /* 0x00 */
675 U8 Unit; /* 0x01 */
676 U8 Minor; /* 0x02 */
677 U8 Major; /* 0x03 */
678} MPI2_VERSION_STRUCT;
679
680typedef union _MPI2_VERSION_UNION
681{
682 MPI2_VERSION_STRUCT Struct;
683 U32 Word;
684} MPI2_VERSION_UNION;
685
686
687/* LUN field defines, common to many structures */
688#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
689#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
690#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
691#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
692#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
693#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
694
695
696/*****************************************************************************
697*
698* Fusion-MPT MPI Scatter Gather Elements
699*
700*****************************************************************************/
701
702/****************************************************************************
703* MPI Simple Element structures
704****************************************************************************/
705
706typedef struct _MPI2_SGE_SIMPLE32
707{
708 U32 FlagsLength;
709 U32 Address;
710} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
711 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
712
713typedef struct _MPI2_SGE_SIMPLE64
714{
715 U32 FlagsLength;
716 U64 Address;
717} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
718 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
719
720typedef struct _MPI2_SGE_SIMPLE_UNION
721{
722 U32 FlagsLength;
723 union
724 {
725 U32 Address32;
726 U64 Address64;
727 } u;
728} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
729 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
730
731
732/****************************************************************************
733* MPI Chain Element structures
734****************************************************************************/
735
736typedef struct _MPI2_SGE_CHAIN32
737{
738 U16 Length;
739 U8 NextChainOffset;
740 U8 Flags;
741 U32 Address;
742} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
743 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
744
745typedef struct _MPI2_SGE_CHAIN64
746{
747 U16 Length;
748 U8 NextChainOffset;
749 U8 Flags;
750 U64 Address;
751} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
752 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
753
754typedef struct _MPI2_SGE_CHAIN_UNION
755{
756 U16 Length;
757 U8 NextChainOffset;
758 U8 Flags;
759 union
760 {
761 U32 Address32;
762 U64 Address64;
763 } u;
764} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
765 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
766
767
768/****************************************************************************
769* MPI Transaction Context Element structures
770****************************************************************************/
771
772typedef struct _MPI2_SGE_TRANSACTION32
773{
774 U8 Reserved;
775 U8 ContextSize;
776 U8 DetailsLength;
777 U8 Flags;
778 U32 TransactionContext[1];
779 U32 TransactionDetails[1];
780} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
781 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
782
783typedef struct _MPI2_SGE_TRANSACTION64
784{
785 U8 Reserved;
786 U8 ContextSize;
787 U8 DetailsLength;
788 U8 Flags;
789 U32 TransactionContext[2];
790 U32 TransactionDetails[1];
791} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
792 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
793
794typedef struct _MPI2_SGE_TRANSACTION96
795{
796 U8 Reserved;
797 U8 ContextSize;
798 U8 DetailsLength;
799 U8 Flags;
800 U32 TransactionContext[3];
801 U32 TransactionDetails[1];
802} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
803 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
804
805typedef struct _MPI2_SGE_TRANSACTION128
806{
807 U8 Reserved;
808 U8 ContextSize;
809 U8 DetailsLength;
810 U8 Flags;
811 U32 TransactionContext[4];
812 U32 TransactionDetails[1];
813} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
814 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
815
816typedef struct _MPI2_SGE_TRANSACTION_UNION
817{
818 U8 Reserved;
819 U8 ContextSize;
820 U8 DetailsLength;
821 U8 Flags;
822 union
823 {
824 U32 TransactionContext32[1];
825 U32 TransactionContext64[2];
826 U32 TransactionContext96[3];
827 U32 TransactionContext128[4];
828 } u;
829 U32 TransactionDetails[1];
830} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
831 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
832
833
834/****************************************************************************
835* MPI SGE union for IO SGL's
836****************************************************************************/
837
838typedef struct _MPI2_MPI_SGE_IO_UNION
839{
840 union
841 {
842 MPI2_SGE_SIMPLE_UNION Simple;
843 MPI2_SGE_CHAIN_UNION Chain;
844 } u;
845} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
846 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
847
848
849/****************************************************************************
850* MPI SGE union for SGL's with Simple and Transaction elements
851****************************************************************************/
852
853typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
854{
855 union
856 {
857 MPI2_SGE_SIMPLE_UNION Simple;
858 MPI2_SGE_TRANSACTION_UNION Transaction;
859 } u;
860} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
861 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
862
863
864/****************************************************************************
865* All MPI SGE types union
866****************************************************************************/
867
868typedef struct _MPI2_MPI_SGE_UNION
869{
870 union
871 {
872 MPI2_SGE_SIMPLE_UNION Simple;
873 MPI2_SGE_CHAIN_UNION Chain;
874 MPI2_SGE_TRANSACTION_UNION Transaction;
875 } u;
876} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
877 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
878
879
880/****************************************************************************
881* MPI SGE field definition and masks
882****************************************************************************/
883
884/* Flags field bit definitions */
885
886#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
887#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
888#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
889#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
890#define MPI2_SGE_FLAGS_DIRECTION (0x04)
891#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
892#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
893
894#define MPI2_SGE_FLAGS_SHIFT (24)
895
896#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
897#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
898
899/* Element Type */
900
901#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
902#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
903#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
904#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
905
906/* Address location */
907
908#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
909
910/* Direction */
911
912#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
913#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
914
915/* Address Size */
916
917#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
918#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
919
920/* Context Size */
921
922#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
923#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
924#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
925#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
926
927#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
928#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
929
930/****************************************************************************
931* MPI SGE operation Macros
932****************************************************************************/
933
934/* SIMPLE FlagsLength manipulations... */
935#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
936#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
937#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
938#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
939
940#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
941
942#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
943#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
944#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
945
946/* CAUTION - The following are READ-MODIFY-WRITE! */
947#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
948#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
949
950#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
951
952
953/*****************************************************************************
954*
955* Fusion-MPT IEEE Scatter Gather Elements
956*
957*****************************************************************************/
958
959/****************************************************************************
960* IEEE Simple Element structures
961****************************************************************************/
962
963typedef struct _MPI2_IEEE_SGE_SIMPLE32
964{
965 U32 Address;
966 U32 FlagsLength;
967} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
968 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
969
970typedef struct _MPI2_IEEE_SGE_SIMPLE64
971{
972 U64 Address;
973 U32 Length;
974 U16 Reserved1;
975 U8 Reserved2;
976 U8 Flags;
977} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
978 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
979
980typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
981{
982 MPI2_IEEE_SGE_SIMPLE32 Simple32;
983 MPI2_IEEE_SGE_SIMPLE64 Simple64;
984} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
985 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
986
987
988/****************************************************************************
989* IEEE Chain Element structures
990****************************************************************************/
991
992typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
993
994typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
995
996typedef union _MPI2_IEEE_SGE_CHAIN_UNION
997{
998 MPI2_IEEE_SGE_CHAIN32 Chain32;
999 MPI2_IEEE_SGE_CHAIN64 Chain64;
1000} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1001 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1002
1003
1004/****************************************************************************
1005* All IEEE SGE types union
1006****************************************************************************/
1007
1008typedef struct _MPI2_IEEE_SGE_UNION
1009{
1010 union
1011 {
1012 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1013 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1014 } u;
1015} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1016 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1017
1018
1019/****************************************************************************
1020* IEEE SGE field definitions and masks
1021****************************************************************************/
1022
1023/* Flags field bit definitions */
1024
1025#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1026
1027#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1028
1029#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1030
1031/* Element Type */
1032
1033#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1034#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1035
1036/* Data Location Address Space */
1037
1038#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1039#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1040#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1041#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1042#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1043
1044
1045/****************************************************************************
1046* IEEE SGE operation Macros
1047****************************************************************************/
1048
1049/* SIMPLE FlagsLength manipulations... */
1050#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1051#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1052#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1053
1054#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1055
1056#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1057#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1058#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1059
1060/* CAUTION - The following are READ-MODIFY-WRITE! */
1061#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1062#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1063
1064
1065
1066
1067/*****************************************************************************
1068*
1069* Fusion-MPT MPI/IEEE Scatter Gather Unions
1070*
1071*****************************************************************************/
1072
1073typedef union _MPI2_SIMPLE_SGE_UNION
1074{
1075 MPI2_SGE_SIMPLE_UNION MpiSimple;
1076 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1077} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1078 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1079
1080
1081typedef union _MPI2_SGE_IO_UNION
1082{
1083 MPI2_SGE_SIMPLE_UNION MpiSimple;
1084 MPI2_SGE_CHAIN_UNION MpiChain;
1085 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1086 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1087} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1088 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1089
1090
1091/****************************************************************************
1092*
1093* Values for SGLFlags field, used in many request messages with an SGL
1094*
1095****************************************************************************/
1096
1097/* values for MPI SGL Data Location Address Space subfield */
1098#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1099#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1100#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1101#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1102#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1103/* values for SGL Type subfield */
1104#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1105#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1106#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1107#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1108
1109
1110#endif
1111