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review.evervolv.com / android_kernel_htc_msm8960 / dee805532a30183c4462305b4614e58bd83a7bc1 / . / arch / powerpc / boot / dts / mpc8572ds.dts
blob: cb06325f0b7955dd2b79888ca9810340d141cdda [file] [log] [blame]
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]1/*
2 * MPC8572 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]45 next-level-cache = <&L2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]46 };
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]47
48 PowerPC,8572@1 {
49 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]58 next-level-cache = <&L2>;
Kumar Gala7e258672008-02-05 23:58:30 -0600[diff] [blame]59 };
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]60 };
61
62 memory {
63 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]64 reg = <0x0 0x0>; // Filled by U-Boot
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]65 };
66
67 soc8572@ffe00000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 device_type = "soc";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]71 ranges = <0x0 0xffe00000 0x100000>;
72 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]73 bus-frequency = <0>; // Filled out by uboot.
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]77 reg = <0x2000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]78 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]79 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]80 };
81
82 memory-controller@6000 {
83 compatible = "fsl,mpc8572-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]84 reg = <0x6000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]85 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]86 interrupts = <18 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]87 };
88
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]89 L2: l2-cache-controller@20000 {
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]90 compatible = "fsl,mpc8572-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]91 reg = <0x20000 0x1000>;
92 cache-line-size = <32>; // 32 bytes
93 cache-size = <0x80000>; // L2, 512K
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]94 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]95 interrupts = <16 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]96 };
97
98 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]99 #address-cells = <1>;
100 #size-cells = <0>;
101 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]102 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]103 reg = <0x3000 0x100>;
104 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]105 interrupt-parent = <&mpic>;
106 dfsrr;
107 };
108
109 i2c@3100 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]110 #address-cells = <1>;
111 #size-cells = <0>;
112 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]113 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]114 reg = <0x3100 0x100>;
115 interrupts = <43 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]116 interrupt-parent = <&mpic>;
117 dfsrr;
118 };
119
Kumar Galadee80552008-06-27 13:45:19 -0500[diff] [blame^]120 dma@c300 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
124 reg = <0xc300 0x4>;
125 ranges = <0x0 0xc100 0x200>;
126 cell-index = <1>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8572-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x0 0x80>;
131 cell-index = <0>;
132 interrupt-parent = <&mpic>;
133 interrupts = <76 2>;
134 };
135 dma-channel@80 {
136 compatible = "fsl,mpc8572-dma-channel",
137 "fsl,eloplus-dma-channel";
138 reg = <0x80 0x80>;
139 cell-index = <1>;
140 interrupt-parent = <&mpic>;
141 interrupts = <77 2>;
142 };
143 dma-channel@100 {
144 compatible = "fsl,mpc8572-dma-channel",
145 "fsl,eloplus-dma-channel";
146 reg = <0x100 0x80>;
147 cell-index = <2>;
148 interrupt-parent = <&mpic>;
149 interrupts = <78 2>;
150 };
151 dma-channel@180 {
152 compatible = "fsl,mpc8572-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x180 0x80>;
155 cell-index = <3>;
156 interrupt-parent = <&mpic>;
157 interrupts = <79 2>;
158 };
159 };
160
161 dma@21300 {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
165 reg = <0x21300 0x4>;
166 ranges = <0x0 0x21100 0x200>;
167 cell-index = <0>;
168 dma-channel@0 {
169 compatible = "fsl,mpc8572-dma-channel",
170 "fsl,eloplus-dma-channel";
171 reg = <0x0 0x80>;
172 cell-index = <0>;
173 interrupt-parent = <&mpic>;
174 interrupts = <20 2>;
175 };
176 dma-channel@80 {
177 compatible = "fsl,mpc8572-dma-channel",
178 "fsl,eloplus-dma-channel";
179 reg = <0x80 0x80>;
180 cell-index = <1>;
181 interrupt-parent = <&mpic>;
182 interrupts = <21 2>;
183 };
184 dma-channel@100 {
185 compatible = "fsl,mpc8572-dma-channel",
186 "fsl,eloplus-dma-channel";
187 reg = <0x100 0x80>;
188 cell-index = <2>;
189 interrupt-parent = <&mpic>;
190 interrupts = <22 2>;
191 };
192 dma-channel@180 {
193 compatible = "fsl,mpc8572-dma-channel",
194 "fsl,eloplus-dma-channel";
195 reg = <0x180 0x80>;
196 cell-index = <3>;
197 interrupt-parent = <&mpic>;
198 interrupts = <23 2>;
199 };
200 };
201
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]202 mdio@24520 {
203 #address-cells = <1>;
204 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]205 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]206 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]207
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]208 phy0: ethernet-phy@0 {
209 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]210 interrupts = <10 1>;
211 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]212 };
213 phy1: ethernet-phy@1 {
214 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]215 interrupts = <10 1>;
216 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]217 };
218 phy2: ethernet-phy@2 {
219 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]220 interrupts = <10 1>;
221 reg = <0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]222 };
223 phy3: ethernet-phy@3 {
224 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]225 interrupts = <10 1>;
226 reg = <0x3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]227 };
228 };
229
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]230 enet0: ethernet@24000 {
231 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]232 device_type = "network";
233 model = "eTSEC";
234 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]235 reg = <0x24000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]236 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]237 interrupts = <29 2 30 2 34 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]238 interrupt-parent = <&mpic>;
239 phy-handle = <&phy0>;
240 phy-connection-type = "rgmii-id";
241 };
242
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]243 enet1: ethernet@25000 {
244 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]245 device_type = "network";
246 model = "eTSEC";
247 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]248 reg = <0x25000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]249 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]250 interrupts = <35 2 36 2 40 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]251 interrupt-parent = <&mpic>;
252 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id";
254 };
255
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]256 enet2: ethernet@26000 {
257 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]258 device_type = "network";
259 model = "eTSEC";
260 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]261 reg = <0x26000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]262 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]263 interrupts = <31 2 32 2 33 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]264 interrupt-parent = <&mpic>;
265 phy-handle = <&phy2>;
266 phy-connection-type = "rgmii-id";
267 };
268
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]269 enet3: ethernet@27000 {
270 cell-index = <3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]271 device_type = "network";
272 model = "eTSEC";
273 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]274 reg = <0x27000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]275 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]276 interrupts = <37 2 38 2 39 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]277 interrupt-parent = <&mpic>;
278 phy-handle = <&phy3>;
279 phy-connection-type = "rgmii-id";
280 };
281
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]282 serial0: serial@4500 {
283 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]284 device_type = "serial";
285 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]286 reg = <0x4500 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]287 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]288 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]289 interrupt-parent = <&mpic>;
290 };
291
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]292 serial1: serial@4600 {
293 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]294 device_type = "serial";
295 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]296 reg = <0x4600 0x100>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]297 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]298 interrupts = <42 2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]299 interrupt-parent = <&mpic>;
300 };
301
302 global-utilities@e0000 { //global utilities block
303 compatible = "fsl,mpc8572-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]304 reg = <0xe0000 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]305 fsl,has-rstcr;
306 };
307
Jason Jin741edc42008-05-23 16:32:48 +0800[diff] [blame]308 msi@41600 {
309 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
310 reg = <0x41600 0x80>;
311 msi-available-ranges = <0 0x100>;
312 interrupts = <
313 0xe0 0
314 0xe1 0
315 0xe2 0
316 0xe3 0
317 0xe4 0
318 0xe5 0
319 0xe6 0
320 0xe7 0>;
321 interrupt-parent = <&mpic>;
322 };
323
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]324 mpic: pic@40000 {
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]325 interrupt-controller;
326 #address-cells = <0>;
327 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]328 reg = <0x40000 0x40000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]329 compatible = "chrp,open-pic";
330 device_type = "open-pic";
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]331 };
332 };
333
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]334 pci0: pcie@ffe08000 {
335 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]336 compatible = "fsl,mpc8548-pcie";
337 device_type = "pci";
338 #interrupt-cells = <1>;
339 #size-cells = <2>;
340 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]341 reg = <0xffe08000 0x1000>;
342 bus-range = <0 255>;
343 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
344 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
345 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]346 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]347 interrupts = <24 2>;
348 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]349 interrupt-map = <
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]350 /* IDSEL 0x11 func 0 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]351 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
352 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
353 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
354 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]355
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]356 /* IDSEL 0x11 func 1 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]357 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
358 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
359 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
360 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]361
362 /* IDSEL 0x11 func 2 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]363 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
364 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
365 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
366 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]367
368 /* IDSEL 0x11 func 3 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]369 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
370 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
371 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
372 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]373
374 /* IDSEL 0x11 func 4 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]375 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
376 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
377 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
378 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]379
380 /* IDSEL 0x11 func 5 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]381 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
382 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
383 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
384 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]385
386 /* IDSEL 0x11 func 6 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]387 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
388 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
389 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
390 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]391
392 /* IDSEL 0x11 func 7 - PCI slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]393 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
394 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
395 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
396 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]397
398 /* IDSEL 0x12 func 0 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]399 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
400 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
401 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
402 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]403
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]404 /* IDSEL 0x12 func 1 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]405 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
406 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
407 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
408 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]409
410 /* IDSEL 0x12 func 2 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]411 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
412 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
413 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
414 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]415
416 /* IDSEL 0x12 func 3 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]417 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
418 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
419 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
420 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]421
422 /* IDSEL 0x12 func 4 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]423 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
424 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
425 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
426 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]427
428 /* IDSEL 0x12 func 5 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]429 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
430 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
431 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
432 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]433
434 /* IDSEL 0x12 func 6 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]435 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
436 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
437 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
438 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]439
440 /* IDSEL 0x12 func 7 - PCI slot 2 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]441 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
442 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
443 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
444 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]445
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]446 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]447 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
448 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
449 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
450 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]451
452 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]453 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]454
455 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]456 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
457 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]458
459 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]460 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
461 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]462
463 >;
464
465 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]466 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]467 #size-cells = <2>;
468 #address-cells = <3>;
469 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]470 ranges = <0x2000000 0x0 0x80000000
471 0x2000000 0x0 0x80000000
472 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]473
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]474 0x1000000 0x0 0x0
475 0x1000000 0x0 0x0
476 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]477 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]478 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]479 #size-cells = <2>;
480 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]481 ranges = <0x2000000 0x0 0x80000000
482 0x2000000 0x0 0x80000000
483 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]484
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]485 0x1000000 0x0 0x0
486 0x1000000 0x0 0x0
487 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]488 isa@1e {
489 device_type = "isa";
490 #interrupt-cells = <2>;
491 #size-cells = <1>;
492 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]493 reg = <0xf000 0x0 0x0 0x0 0x0>;
494 ranges = <0x1 0x0 0x1000000 0x0 0x0
495 0x1000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]496 interrupt-parent = <&i8259>;
497
498 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]499 reg = <0x1 0x20 0x2
500 0x1 0xa0 0x2
501 0x1 0x4d0 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]502 interrupt-controller;
503 device_type = "interrupt-controller";
504 #address-cells = <0>;
505 #interrupt-cells = <2>;
506 compatible = "chrp,iic";
507 interrupts = <9 2>;
508 interrupt-parent = <&mpic>;
509 };
510
511 i8042@60 {
512 #size-cells = <0>;
513 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]514 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
515 interrupts = <1 3 12 3>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]516 interrupt-parent =
517 <&i8259>;
518
519 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]520 reg = <0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]521 compatible = "pnpPNP,303";
522 };
523
524 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]525 reg = <0x1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]526 compatible = "pnpPNP,f03";
527 };
528 };
529
530 rtc@70 {
531 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]532 reg = <0x1 0x70 0x2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]533 };
534
535 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]536 reg = <0x1 0x400 0x80>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]537 };
538 };
539 };
540 };
541
542 };
543
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]544 pci1: pcie@ffe09000 {
545 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]546 compatible = "fsl,mpc8548-pcie";
547 device_type = "pci";
548 #interrupt-cells = <1>;
549 #size-cells = <2>;
550 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]551 reg = <0xffe09000 0x1000>;
552 bus-range = <0 255>;
553 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
554 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
555 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]556 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]557 interrupts = <26 2>;
558 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]559 interrupt-map = <
560 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]561 0000 0x0 0x0 0x1 &mpic 0x4 0x1
562 0000 0x0 0x0 0x2 &mpic 0x5 0x1
563 0000 0x0 0x0 0x3 &mpic 0x6 0x1
564 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]565 >;
566 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]567 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]568 #size-cells = <2>;
569 #address-cells = <3>;
570 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]571 ranges = <0x2000000 0x0 0xa0000000
572 0x2000000 0x0 0xa0000000
573 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]574
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]575 0x1000000 0x0 0x0
576 0x1000000 0x0 0x0
577 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]578 };
579 };
580
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]581 pci2: pcie@ffe0a000 {
582 cell-index = <2>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]583 compatible = "fsl,mpc8548-pcie";
584 device_type = "pci";
585 #interrupt-cells = <1>;
586 #size-cells = <2>;
587 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]588 reg = <0xffe0a000 0x1000>;
589 bus-range = <0 255>;
590 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
591 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
592 clock-frequency = <33333333>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]593 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]594 interrupts = <27 2>;
595 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]596 interrupt-map = <
597 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]598 0000 0x0 0x0 0x1 &mpic 0x0 0x1
599 0000 0x0 0x0 0x2 &mpic 0x1 0x1
600 0000 0x0 0x0 0x3 &mpic 0x2 0x1
601 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]602 >;
603 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]604 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]605 #size-cells = <2>;
606 #address-cells = <3>;
607 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]608 ranges = <0x2000000 0x0 0xc0000000
609 0x2000000 0x0 0xc0000000
610 0x0 0x20000000
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]611
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]612 0x1000000 0x0 0x0
613 0x1000000 0x0 0x0
614 0x0 0x100000>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]615 };
616 };
617};