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review.evervolv.com / android_kernel_htc_msm8960 / e01bb5a4944eea27e87ca00a869105185c13664d / . / drivers / video / msm / mdp4_util.c
blob: b156d5264288cf4d87d7c7f88858008d405aedcd [file] [log] [blame]
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]1/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/debugfs.h>
25#include <linux/semaphore.h>
26#include <linux/uaccess.h>
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]27#include <linux/msm_mdp.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]28#include <asm/system.h>
29#include <asm/mach-types.h>
30#include <mach/hardware.h>
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]31#include <mach/iommu_domains.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]32#include "mdp.h"
33#include "msm_fb.h"
34#include "mdp4.h"
35
36struct mdp4_statistic mdp4_stat;
37
38unsigned is_mdp4_hw_reset(void)
39{
40 unsigned hw_reset = 0;
41
42 /* Only revisions > v2.1 may be reset or powered off/on at runtime */
43 if (mdp_hw_revision > MDP4_REVISION_V2_1) {
44 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
45 hw_reset = !inpdw(MDP_BASE + 0x003c);
46 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
47 }
48
49 return hw_reset;
50}
51
52void mdp4_sw_reset(ulong bits)
53{
54 /* MDP cmd block enable */
55 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
56
57 bits &= 0x1f; /* 5 bits */
58 outpdw(MDP_BASE + 0x001c, bits); /* MDP_SW_RESET */
59
60 while (inpdw(MDP_BASE + 0x001c) & bits) /* self clear when complete */
61 ;
62 /* MDP cmd block disable */
63 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
64
65 MSM_FB_DEBUG("mdp4_sw_reset: 0x%x\n", (int)bits);
66}
67
68void mdp4_overlay_cfg(int overlayer, int blt_mode, int refresh, int direct_out)
69{
70 ulong bits = 0;
71
72 if (blt_mode)
73 bits |= (1 << 3);
74 refresh &= 0x03; /* 2 bites */
75 bits |= (refresh << 1);
76 direct_out &= 0x01;
77 bits |= direct_out;
78 /* MDP cmd block enable */
79 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
80
81
82 if (overlayer == MDP4_MIXER0)
83 outpdw(MDP_BASE + 0x10004, bits); /* MDP_OVERLAY0_CFG */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]84 else if (overlayer == MDP4_MIXER1)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]85 outpdw(MDP_BASE + 0x18004, bits); /* MDP_OVERLAY1_CFG */
86
87 MSM_FB_DEBUG("mdp4_overlay_cfg: 0x%x\n",
88 (int)inpdw(MDP_BASE + 0x10004));
89 /* MDP cmd block disable */
90 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
91}
92
93void mdp4_display_intf_sel(int output, ulong intf)
94{
95 ulong bits, mask, data;
96 /* MDP cmd block enable */
97 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
98
99 bits = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
100
101 if (intf == DSI_VIDEO_INTF) {
102 data = 0x40; /* bit 6 */
103 intf = MDDI_LCDC_INTF;
104 if (output == SECONDARY_INTF_SEL) {
105 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
106 intf=%d\n", __func__, output, (int)intf);
107 }
108 } else if (intf == DSI_CMD_INTF) {
109 data = 0x80; /* bit 7 */
110 intf = MDDI_INTF;
111 if (output == EXTERNAL_INTF_SEL) {
112 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
113 intf=%d\n", __func__, output, (int)intf);
114 }
115 } else
116 data = 0;
117
118 mask = 0x03; /* 2 bits */
119 intf &= 0x03; /* 2 bits */
120
121 switch (output) {
122 case EXTERNAL_INTF_SEL:
123 intf <<= 4;
124 mask <<= 4;
125 break;
126 case SECONDARY_INTF_SEL:
127 intf &= 0x02; /* only MDDI and EBI2 support */
128 intf <<= 2;
129 mask <<= 2;
130 break;
131 default:
132 break;
133 }
134
135 intf |= data;
136 mask |= data;
137
138 bits &= ~mask;
139 bits |= intf;
140
141 outpdw(MDP_BASE + 0x0038, bits); /* MDP_DISP_INTF_SEL */
142 /* MDP cmd block disable */
143 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
144
145 MSM_FB_DEBUG("mdp4_display_intf_sel: 0x%x\n", (int)inpdw(MDP_BASE + 0x0038));
146}
147
148unsigned long mdp4_display_status(void)
149{
150 ulong status;
151 /* MDP cmd block enable */
152 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
153
154 status = inpdw(MDP_BASE + 0x0018) & 0x3ff; /* MDP_DISPLAY_STATUS */
155
156 /* MDP cmd block disable */
157 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
158 return status;
159}
160
161void mdp4_ebi2_lcd_setup(int lcd, ulong base, int ystride)
162{
163 /* always use memory map */
164 ystride &= 0x01fff; /* 13 bits */
165 /* MDP cmd block enable */
166 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
167
168 if (lcd == EBI2_LCD0) {
169 outpdw(MDP_BASE + 0x0060, base);/* MDP_EBI2_LCD0 */
170 outpdw(MDP_BASE + 0x0068, ystride);/* MDP_EBI2_LCD0_YSTRIDE */
171 } else {
172 outpdw(MDP_BASE + 0x0064, base);/* MDP_EBI2_LCD1 */
173 outpdw(MDP_BASE + 0x006c, ystride);/* MDP_EBI2_LCD1_YSTRIDE */
174 }
175 /* MDP cmd block disable */
176 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
177}
178
179void mdp4_mddi_setup(int mddi, unsigned long id)
180{
181 ulong bits;
182
183 if (mddi == MDDI_EXTERNAL_SET)
184 bits = 0x02;
185 else if (mddi == MDDI_SECONDARY_SET)
186 bits = 0x01;
187 else
188 bits = 0; /* PRIMARY_SET */
189
190 id <<= 16;
191
192 bits |= id;
193 /* MDP cmd block enable */
194 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
195
196 outpdw(MDP_BASE + 0x0090, bits); /* MDP_MDDI_PARAM_WR_SEL */
197 /* MDP cmd block disable */
198 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
199}
200
201int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req)
202{
203
204 /* not implemented yet */
205 return -1;
206}
207
208void mdp4_fetch_cfg(uint32 core_clk)
209{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]210 uint32 dmap_data, vg_data;
211 char *base;
212 int i;
213 /* MDP cmd block enable */
214 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
215
Adrian Salido-Moreno3436dae2011-08-08 12:13:07 -0700[diff] [blame]216 if (mdp_rev >= MDP_REV_41 || core_clk >= 90000000) { /* 90 Mhz */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]217 dmap_data = 0x47; /* 16 bytes-burst x 8 req */
218 vg_data = 0x47; /* 16 bytes-burs x 8 req */
219 } else {
220 dmap_data = 0x27; /* 8 bytes-burst x 8 req */
221 vg_data = 0x43; /* 16 bytes-burst x 4 req */
222 }
223
224 MSM_FB_DEBUG("mdp4_fetch_cfg: dmap=%x vg=%x\n",
225 dmap_data, vg_data);
226
227 /* dma_p fetch config */
228 outpdw(MDP_BASE + 0x91004, dmap_data);
229 /* dma_e fetch config */
230 outpdw(MDP_BASE + 0xB1004, dmap_data);
231
232 /*
233 * set up two vg pipes and two rgb pipes
234 */
235 base = MDP_BASE + MDP4_VIDEO_BASE;
236 for (i = 0; i < 4; i++) {
237 outpdw(base + 0x1004, vg_data);
238 base += MDP4_VIDEO_OFF;
239 }
240 /* MDP cmd block disable */
241 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
242}
243
244void mdp4_hw_init(void)
245{
246 ulong bits;
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]247 uint32 clk_rate;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]248
249 /* MDP cmd block enable */
250 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
251
Nagamalleswararao Ganji074ee022011-09-02 12:06:37 -0700[diff] [blame]252 mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
253
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]254#ifdef MDP4_ERROR
255 /*
256 * Issue software reset on DMA_P will casue DMA_P dma engine stall
257 * on LCDC mode. However DMA_P does not stall at MDDI mode.
258 * This need further investigation.
259 */
260 mdp4_sw_reset(0x17);
261#endif
262
kuogee hsieh4b910f22011-11-15 09:43:04 -0800[diff] [blame]263 if (mdp_rev > MDP_REV_41) {
264 /* mdp chip select controller */
265 outpdw(MDP_BASE + 0x00c0, CS_CONTROLLER_0);
266 outpdw(MDP_BASE + 0x00c4, CS_CONTROLLER_1);
267 }
268
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]269 mdp4_clear_lcdc();
270
271 mdp4_mixer_blend_init(0);
272 mdp4_mixer_blend_init(1);
273 mdp4_vg_qseed_init(0);
274 mdp4_vg_qseed_init(1);
275
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]276 mdp4_vg_csc_setup(0);
277 mdp4_vg_csc_setup(1);
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]278 mdp4_mixer_csc_setup(1);
279 mdp4_mixer_csc_setup(2);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]280 mdp4_dmap_csc_setup();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]281
Ravishangar Kalyaname7833e22011-07-22 16:20:19 -0700[diff] [blame]282 if (mdp_rev <= MDP_REV_41) {
283 mdp4_mixer_gc_lut_setup(0);
284 mdp4_mixer_gc_lut_setup(1);
285 }
286
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]287 mdp4_vg_igc_lut_setup(0);
288 mdp4_vg_igc_lut_setup(1);
289
290 mdp4_rgb_igc_lut_setup(0);
291 mdp4_rgb_igc_lut_setup(1);
292
293 outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
294
295 /* system interrupts */
296
297 bits = mdp_intr_mask;
298 outpdw(MDP_BASE + 0x0050, bits);/* enable specififed interrupts */
299
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]300 /* For the max read pending cmd config below, if the MDP clock */
301 /* is less than the AXI clock, then we must use 3 pending */
302 /* pending requests. Otherwise, we should use 8 pending requests. */
303 /* In the future we should do this detection automatically. */
304
305 /* max read pending cmd config */
306 outpdw(MDP_BASE + 0x004c, 0x02222); /* 3 pending requests */
307
308#ifndef CONFIG_FB_MSM_OVERLAY
309 /* both REFRESH_MODE and DIRECT_OUT are ignored at BLT mode */
310 mdp4_overlay_cfg(MDP4_MIXER0, OVERLAY_MODE_BLT, 0, 0);
311 mdp4_overlay_cfg(MDP4_MIXER1, OVERLAY_MODE_BLT, 0, 0);
312#endif
313
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]314 clk_rate = mdp_get_core_clk();
315 mdp4_fetch_cfg(clk_rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]316
317 /* Mark hardware as initialized. Only revisions > v2.1 have a register
318 * for tracking core reset status. */
319 if (mdp_hw_revision > MDP4_REVISION_V2_1)
320 outpdw(MDP_BASE + 0x003c, 1);
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]321
322 /* MDP cmd block disable */
323 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]324}
325
326
327void mdp4_clear_lcdc(void)
328{
329 uint32 bits;
330
331 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
332
333 bits = inpdw(MDP_BASE + 0xc0000);
334 if (bits & 0x01) { /* enabled already */
335 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
336 return;
337 }
338
339 outpdw(MDP_BASE + 0xc0004, 0); /* vsync ctrl out */
340 outpdw(MDP_BASE + 0xc0008, 0); /* vsync period */
341 outpdw(MDP_BASE + 0xc000c, 0); /* vsync pusle width */
342 outpdw(MDP_BASE + 0xc0010, 0); /* lcdc display HCTL */
343 outpdw(MDP_BASE + 0xc0014, 0); /* lcdc display v start */
344 outpdw(MDP_BASE + 0xc0018, 0); /* lcdc display v end */
345 outpdw(MDP_BASE + 0xc001c, 0); /* lcdc active hctl */
346 outpdw(MDP_BASE + 0xc0020, 0); /* lcdc active v start */
347 outpdw(MDP_BASE + 0xc0024, 0); /* lcdc active v end */
348 outpdw(MDP_BASE + 0xc0028, 0); /* lcdc board color */
349 outpdw(MDP_BASE + 0xc002c, 0); /* lcdc underflow ctrl */
350 outpdw(MDP_BASE + 0xc0030, 0); /* lcdc hsync skew */
351 outpdw(MDP_BASE + 0xc0034, 0); /* lcdc test ctl */
352 outpdw(MDP_BASE + 0xc0038, 0); /* lcdc ctl polarity */
353
354 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
355}
356
357irqreturn_t mdp4_isr(int irq, void *ptr)
358{
359 uint32 isr, mask, panel;
360 struct mdp_dma_data *dma;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]361 struct mdp_hist_mgmt *mgmt = NULL;
362 char *base_addr;
363 int i, ret;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]364
365 mdp_is_in_isr = TRUE;
366
367 /* complete all the reads before reading the interrupt
368 * status register - eliminate effects of speculative
369 * reads by the cpu
370 */
371 rmb();
372 isr = inpdw(MDP_INTR_STATUS);
373 if (isr == 0)
374 goto out;
375
376 mdp4_stat.intr_tot++;
377 mask = inpdw(MDP_INTR_ENABLE);
378 outpdw(MDP_INTR_CLEAR, isr);
379
380 if (isr & INTR_PRIMARY_INTF_UDERRUN) {
381 mdp4_stat.intr_underrun_p++;
382 /* When underun occurs mdp clear the histogram registers
383 that are set before in hw_init so restore them back so
384 that histogram works.*/
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]385 for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
386 mgmt = mdp_hist_mgmt_array[i];
387 if (!mgmt)
388 continue;
389 base_addr = MDP_BASE + mgmt->base;
390 MDP_OUTP(base_addr + 0x010, 1);
391 outpdw(base_addr + 0x01c, INTR_HIST_DONE |
392 INTR_HIST_RESET_SEQ_DONE);
393 mgmt->mdp_is_hist_valid = FALSE;
394 __mdp_histogram_reset(mgmt);
395 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]396 }
397
398 if (isr & INTR_EXTERNAL_INTF_UDERRUN)
399 mdp4_stat.intr_underrun_e++;
400
401 isr &= mask;
402
403 if (isr == 0)
404 goto out;
405
406 panel = mdp4_overlay_panel_list();
407 if (isr & INTR_PRIMARY_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]408 mdp4_stat.intr_vsync_p++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]409 dma = &dma2_data;
410 spin_lock(&mdp_spin_lock);
411 mdp_intr_mask &= ~INTR_PRIMARY_VSYNC;
412 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
413 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]414 if (panel & MDP4_PANEL_LCDC)
415 mdp4_primary_vsync_lcdc();
416#ifdef CONFIG_FB_MSM_MIPI_DSI
417 else if (panel & MDP4_PANEL_DSI_VIDEO)
418 mdp4_primary_vsync_dsi_video();
419#endif
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]420 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]421 }
422#ifdef CONFIG_FB_MSM_DTV
423 if (isr & INTR_EXTERNAL_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]424 mdp4_stat.intr_vsync_e++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]425 dma = &dma_e_data;
426 spin_lock(&mdp_spin_lock);
427 mdp_intr_mask &= ~INTR_EXTERNAL_VSYNC;
428 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
429 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]430 if (panel & MDP4_PANEL_DTV)
431 mdp4_external_vsync_dtv();
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]432 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]433 }
434#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]435
436#ifdef CONFIG_FB_MSM_OVERLAY
437 if (isr & INTR_OVERLAY0_DONE) {
438 mdp4_stat.intr_overlay0++;
439 dma = &dma2_data;
440 if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
441 /* disable LCDC interrupt */
442 spin_lock(&mdp_spin_lock);
443 mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
444 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
445 dma->waiting = FALSE;
446 spin_unlock(&mdp_spin_lock);
447 if (panel & MDP4_PANEL_LCDC)
448 mdp4_overlay0_done_lcdc(dma);
449#ifdef CONFIG_FB_MSM_MIPI_DSI
450 else if (panel & MDP4_PANEL_DSI_VIDEO)
451 mdp4_overlay0_done_dsi_video(dma);
452#endif
453 } else { /* MDDI, DSI_CMD */
454#ifdef CONFIG_FB_MSM_MIPI_DSI
455 if (panel & MDP4_PANEL_DSI_CMD)
456 mdp4_overlay0_done_dsi_cmd(dma);
457#else
458 if (panel & MDP4_PANEL_MDDI)
459 mdp4_overlay0_done_mddi(dma);
460#endif
461 }
462 mdp_hw_cursor_done();
463 }
464 if (isr & INTR_OVERLAY1_DONE) {
465 mdp4_stat.intr_overlay1++;
466 /* disable DTV interrupt */
467 dma = &dma_e_data;
468 spin_lock(&mdp_spin_lock);
469 mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
470 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
471 dma->waiting = FALSE;
472 spin_unlock(&mdp_spin_lock);
473#if defined(CONFIG_FB_MSM_DTV)
474 if (panel & MDP4_PANEL_DTV)
475 mdp4_overlay1_done_dtv();
476#endif
477#if defined(CONFIG_FB_MSM_TVOUT)
478 if (panel & MDP4_PANEL_ATV)
479 mdp4_overlay1_done_atv();
480#endif
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]481 }
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]482#if defined(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL)
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]483 if (isr & INTR_OVERLAY2_DONE) {
484 mdp4_stat.intr_overlay2++;
485 /* disable DTV interrupt */
486 dma = &dma_wb_data;
487 spin_lock(&mdp_spin_lock);
488 mdp_intr_mask &= ~INTR_OVERLAY2_DONE;
489 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
490 dma->waiting = FALSE;
491 spin_unlock(&mdp_spin_lock);
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]492 if (panel & MDP4_PANEL_WRITEBACK)
493 mdp4_overlay1_done_writeback(dma);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]494 }
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]495#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]496#endif /* OVERLAY */
497
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]498 if (isr & INTR_DMA_P_DONE) {
499 mdp4_stat.intr_dma_p++;
500 dma = &dma2_data;
501 if (panel & MDP4_PANEL_LCDC) {
502 /* disable LCDC interrupt */
503 spin_lock(&mdp_spin_lock);
504 mdp_intr_mask &= ~INTR_DMA_P_DONE;
505 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
506 dma->waiting = FALSE;
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]507 mdp4_dma_p_done_lcdc();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]508 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]509 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]510#ifdef CONFIG_FB_MSM_OVERLAY
511#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]512 else if (panel & MDP4_PANEL_DSI_VIDEO) {
513 /* disable LCDC interrupt */
514 spin_lock(&mdp_spin_lock);
515 mdp_intr_mask &= ~INTR_DMA_P_DONE;
516 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
517 dma->waiting = FALSE;
Kuogee Hsieh5ff2cb62012-04-11 10:43:07 -0700[diff] [blame]518 mdp4_dma_p_done_dsi_video(dma);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]519 spin_unlock(&mdp_spin_lock);
520 } else if (panel & MDP4_PANEL_DSI_CMD) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]521 mdp4_dma_p_done_dsi(dma);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]522 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]523#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]524 else { /* MDDI */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]525 mdp4_dma_p_done_mddi();
526 mdp_pipe_ctrl(MDP_DMA2_BLOCK,
527 MDP_BLOCK_POWER_OFF, TRUE);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]528 complete(&dma->comp);
529 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]530#endif
531#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]532 else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]533 spin_lock(&mdp_spin_lock);
534 dma->busy = FALSE;
535 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]536 complete(&dma->comp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]537 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]538#endif
539 }
540 if (isr & INTR_DMA_S_DONE) {
541 mdp4_stat.intr_dma_s++;
542#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDDI)
543 dma = &dma2_data;
544#else
545 dma = &dma_s_data;
546#endif
547
548 dma->busy = FALSE;
549 mdp_pipe_ctrl(MDP_DMA_S_BLOCK,
550 MDP_BLOCK_POWER_OFF, TRUE);
551 complete(&dma->comp);
552 }
553 if (isr & INTR_DMA_E_DONE) {
554 mdp4_stat.intr_dma_e++;
555 dma = &dma_e_data;
556 spin_lock(&mdp_spin_lock);
557 mdp_intr_mask &= ~INTR_DMA_E_DONE;
558 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
559 dma->busy = FALSE;
Huaibin Yang0da46922011-11-29 15:08:04 -0800[diff] [blame]560 mdp4_dma_e_done_dtv();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]561 if (dma->waiting) {
562 dma->waiting = FALSE;
563 complete(&dma->comp);
564 }
565 spin_unlock(&mdp_spin_lock);
566 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]567 if (isr & INTR_DMA_P_HISTOGRAM) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]568 mdp4_stat.intr_histogram++;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]569 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_P, &mgmt);
570 if (!ret)
571 mdp_histogram_handle_isr(mgmt);
572 }
573 if (isr & INTR_DMA_S_HISTOGRAM) {
574 mdp4_stat.intr_histogram++;
575 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_S, &mgmt);
576 if (!ret)
577 mdp_histogram_handle_isr(mgmt);
578 }
579 if (isr & INTR_VG1_HISTOGRAM) {
580 mdp4_stat.intr_histogram++;
581 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_1, &mgmt);
582 if (!ret)
583 mdp_histogram_handle_isr(mgmt);
584 }
585 if (isr & INTR_VG2_HISTOGRAM) {
586 mdp4_stat.intr_histogram++;
587 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_2, &mgmt);
588 if (!ret)
589 mdp_histogram_handle_isr(mgmt);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]590 }
591
592out:
593 mdp_is_in_isr = FALSE;
594
595 return IRQ_HANDLED;
596}
597
598
599/*
600 * QSEED tables
601 */
602
603static uint32 vg_qseed_table0[] = {
604 0x5556aaff, 0x00000000, 0x00000000, 0x00000000
605};
606
607static uint32 vg_qseed_table1[] = {
Carl Vanderlipd89c0e72012-03-28 10:17:20 -0700[diff] [blame]608 0x00000000, 0x20000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]609};
610
611static uint32 vg_qseed_table2[] = {
612 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
613 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
614 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
615 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
616 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
617 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
618 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
619 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
620 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
621 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
622 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
623 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
624 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
625 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
626 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
627 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
628
629 0x02000000, 0x00000000, 0x02000000, 0x00000000,
630 0x02000000, 0x00000000, 0x02000000, 0x00000000,
631 0x02000000, 0x00000000, 0x02000000, 0x00000000,
632 0x02000000, 0x00000000, 0x02000000, 0x00000000,
633 0x02000000, 0x00000000, 0x02000000, 0x00000000,
634 0x02000000, 0x00000000, 0x02000000, 0x00000000,
635 0x02000000, 0x00000000, 0x02000000, 0x00000000,
636 0x02000000, 0x00000000, 0x02000000, 0x00000000,
637 0x02000000, 0x00000000, 0x02000000, 0x00000000,
638 0x02000000, 0x00000000, 0x02000000, 0x00000000,
639 0x02000000, 0x00000000, 0x02000000, 0x00000000,
640 0x02000000, 0x00000000, 0x02000000, 0x00000000,
641 0x02000000, 0x00000000, 0x02000000, 0x00000000,
642 0x02000000, 0x00000000, 0x02000000, 0x00000000,
643 0x02000000, 0x00000000, 0x02000000, 0x00000000,
644 0x02000000, 0x00000000, 0x02000000, 0x00000000,
645
646 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
647 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
648 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
649 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
650 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
651 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
652 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
653 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
654 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
655 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
656 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
657 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
658 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
659 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
660 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
661 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
662
663 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
664 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
665 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
666 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
667 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
668 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
669 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
670 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
671 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
672 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
673 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
674 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
675 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
676 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
677 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
678 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
679
680 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
681 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
682 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
683 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
684 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
685 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
686 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
687 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
688 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
689 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
690 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
691 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
692 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
693 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
694 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
695 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
696
697 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
698 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
699 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
700 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
701 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
702 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
703 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
704 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
705 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
706 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
707 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
708 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
709 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
710 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
711 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
712 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
713
714 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
715 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
716 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
717 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
718 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
719 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
720 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
721 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
722 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
723 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
724 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
725 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
726 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
727 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
728 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
729 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
730
731 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
732 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
733 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
734 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
735 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
736 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
737 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
738 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
739 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
740 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
741 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
742 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
743 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
744 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
745 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
746 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
747
748 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
749 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
750 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
751 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
752 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
753 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
754 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
755 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
756 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
757 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
758 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
759 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
760 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
761 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
762 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
763 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
764
765 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
766 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
767 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
768 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
769 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
770 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
771 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
772 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
773 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
774 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
775 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
776 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
777 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
778 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
779 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
780 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
781
782 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
783 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
784 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
785 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
786 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
787 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
788 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
789 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
790 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
791 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
792 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
793 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
794 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
795 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
796 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
797 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
798
799 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
800 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
801 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
802 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
803 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
804 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
805 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
806 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
807 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
808 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
809 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
810 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
811 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
812 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
813 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
814 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
815
816 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
817 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
818 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
819 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
820 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
821 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
822 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
823 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
824 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
825 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
826 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
827 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
828 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
829 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
830 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
831 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
832
833 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
834 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
835 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
836 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
837 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
838 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
839 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
840 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
841 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
842 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
843 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
844 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
845 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
846 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
847 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
848 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
849
850 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
851 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
852 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
853 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
854 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
855 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
856 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
857 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
858 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
859 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
860 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
861 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
862 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
863 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
864 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
865 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
866
867 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
868 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
869 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
870 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
871 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
872 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
873 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
874 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
875 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
876 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
877 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
878 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
879 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
880 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
881 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
882 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e,
883
884 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
885 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
886 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
887 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
888 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
889 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
890 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
891 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
892 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
893 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
894 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
895 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
896 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
897 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
898 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
899 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
900
901 0x02000000, 0x00000000, 0x02000000, 0x00000000,
902 0x02000000, 0x00000000, 0x02000000, 0x00000000,
903 0x02000000, 0x00000000, 0x02000000, 0x00000000,
904 0x02000000, 0x00000000, 0x02000000, 0x00000000,
905 0x02000000, 0x00000000, 0x02000000, 0x00000000,
906 0x02000000, 0x00000000, 0x02000000, 0x00000000,
907 0x02000000, 0x00000000, 0x02000000, 0x00000000,
908 0x02000000, 0x00000000, 0x02000000, 0x00000000,
909 0x02000000, 0x00000000, 0x02000000, 0x00000000,
910 0x02000000, 0x00000000, 0x02000000, 0x00000000,
911 0x02000000, 0x00000000, 0x02000000, 0x00000000,
912 0x02000000, 0x00000000, 0x02000000, 0x00000000,
913 0x02000000, 0x00000000, 0x02000000, 0x00000000,
914 0x02000000, 0x00000000, 0x02000000, 0x00000000,
915 0x02000000, 0x00000000, 0x02000000, 0x00000000,
916 0x02000000, 0x00000000, 0x02000000, 0x00000000,
917
918 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
919 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
920 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
921 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
922 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
923 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
924 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
925 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
926 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
927 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
928 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
929 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
930 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
931 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
932 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
933 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
934
935 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
936 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
937 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
938 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
939 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
940 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
941 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
942 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
943 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
944 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
945 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
946 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
947 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
948 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
949 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
950 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
951
952 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
953 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
954 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
955 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
956 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
957 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
958 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
959 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
960 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
961 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
962 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
963 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
964 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
965 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
966 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
967 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
968
969 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
970 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
971 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
972 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
973 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
974 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
975 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
976 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
977 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
978 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
979 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
980 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
981 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
982 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
983 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
984 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
985
986 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
987 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
988 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
989 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
990 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
991 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
992 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
993 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
994 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
995 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
996 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
997 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
998 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
999 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
1000 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
1001 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
1002
1003 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
1004 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
1005 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
1006 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
1007 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
1008 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
1009 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
1010 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
1011 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
1012 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
1013 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
1014 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
1015 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
1016 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
1017 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
1018 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
1019
1020 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
1021 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
1022 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
1023 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
1024 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
1025 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
1026 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
1027 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
1028 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
1029 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
1030 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
1031 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
1032 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
1033 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
1034 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
1035 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
1036
1037 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
1038 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
1039 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
1040 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
1041 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
1042 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
1043 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
1044 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
1045 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
1046 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
1047 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
1048 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
1049 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
1050 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
1051 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
1052 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
1053
1054 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
1055 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
1056 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
1057 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
1058 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
1059 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
1060 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
1061 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
1062 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
1063 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
1064 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
1065 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
1066 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
1067 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
1068 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
1069 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
1070
1071 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
1072 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
1073 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
1074 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
1075 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
1076 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
1077 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
1078 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
1079 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
1080 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
1081 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
1082 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
1083 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
1084 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
1085 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
1086 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
1087
1088 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
1089 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
1090 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
1091 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
1092 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
1093 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
1094 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
1095 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
1096 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
1097 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
1098 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
1099 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
1100 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
1101 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
1102 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
1103 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
1104
1105 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
1106 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
1107 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
1108 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
1109 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
1110 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
1111 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
1112 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
1113 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
1114 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
1115 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
1116 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
1117 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
1118 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
1119 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
1120 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
1121
1122 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
1123 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
1124 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
1125 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
1126 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
1127 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
1128 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
1129 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
1130 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
1131 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
1132 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
1133 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
1134 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
1135 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
1136 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
1137 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
1138
1139 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
1140 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
1141 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
1142 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
1143 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
1144 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
1145 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
1146 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
1147 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
1148 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
1149 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
1150 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
1151 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
1152 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
1153 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
1154 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e
1155};
1156
1157
1158#define MDP4_QSEED_TABLE0_OFF 0x8100
1159#define MDP4_QSEED_TABLE1_OFF 0x8200
1160#define MDP4_QSEED_TABLE2_OFF 0x9000
1161
1162void mdp4_vg_qseed_init(int vp_num)
1163{
1164 uint32 *off;
1165 int i, voff;
1166
1167 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1168
1169 voff = MDP4_VIDEO_OFF * vp_num;
1170 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1171 MDP4_QSEED_TABLE0_OFF);
1172 for (i = 0; i < (sizeof(vg_qseed_table0) / sizeof(uint32)); i++) {
1173 outpdw(off, vg_qseed_table0[i]);
1174 off++;
1175 /* This code is added to workaround the 1K Boundary AXI
1176 Interleave operations from Scorpion that can potentially
1177 corrupt the QSEED table. The idea is to complete the prevous
1178 to the buffer before making the next write when address is
1179 1KB aligned to ensure the write has been committed prior to
1180 next instruction write that can go out from the secondary AXI
1181 port.This happens also because of the expected write sequence
1182 from QSEED table, where LSP has to be written first then the
1183 MSP to trigger both to write out to SRAM, if this has not been
1184 the expectation, then corruption wouldn't have happened.*/
1185
1186 if (!((uint32)off & 0x3FF))
1187 wmb();
1188 }
1189
1190 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1191 MDP4_QSEED_TABLE1_OFF);
1192 for (i = 0; i < (sizeof(vg_qseed_table1) / sizeof(uint32)); i++) {
1193 outpdw(off, vg_qseed_table1[i]);
1194 off++;
1195 if (!((uint32)off & 0x3FF))
1196 wmb();
1197 }
1198
1199 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1200 MDP4_QSEED_TABLE2_OFF);
1201 for (i = 0; i < (sizeof(vg_qseed_table2) / sizeof(uint32)); i++) {
1202 outpdw(off, vg_qseed_table2[i]);
1203 off++;
1204 if (!((uint32)off & 0x3FF))
1205 wmb();
1206 }
1207
1208 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1209
1210}
1211
1212void mdp4_mixer_blend_init(mixer_num)
1213{
1214 unsigned char *overlay_base;
1215 int off;
1216
1217 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1218 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1219 else
1220 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1221
1222 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1223
1224 /* stage 0 to stage 2 */
1225 off = 0;
1226 outpdw(overlay_base + off + 0x104, 0x010);
1227 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1228 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1229
1230 off += 0x20;
1231 outpdw(overlay_base + off + 0x104, 0x010);
1232 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1233 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1234
1235 off += 0x20;
1236 outpdw(overlay_base + off + 0x104, 0x010);
1237 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1238 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1239
1240 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1241}
1242
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1243struct mdp_csc_cfg mdp_csc_convert[4] = {
1244 { /*RGB2RGB*/
1245 0,
1246 {
1247 0x0200, 0x0000, 0x0000,
1248 0x0000, 0x0200, 0x0000,
1249 0x0000, 0x0000, 0x0200,
1250 },
1251 { 0x0, 0x0, 0x0, },
1252 { 0x0, 0x0, 0x0, },
1253 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1254 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1255 },
1256 { /*YUV2RGB*/
1257 0,
1258 {
1259 0x0254, 0x0000, 0x0331,
1260 0x0254, 0xff37, 0xfe60,
1261 0x0254, 0x0409, 0x0000,
1262 },
1263 { 0xfff0, 0xff80, 0xff80, },
1264 { 0x0, 0x0, 0x0, },
1265 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1266 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1267 },
1268 { /*RGB2YUV*/
1269 0,
1270 {
1271 0x0083, 0x0102, 0x0032,
1272 0x1fb5, 0x1f6c, 0x00e1,
1273 0x00e1, 0x1f45, 0x1fdc
1274 },
1275 { 0x0, 0x0, 0x0, },
1276 { 0x0010, 0x0080, 0x0080, },
1277 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1278 { 0x0010, 0x00eb, 0x0010, 0x00f0, 0x0010, 0x00f0, },
1279 },
1280 { /*YUV2YUV ???*/
1281 0,
1282 {
1283 0x0200, 0x0000, 0x0000,
1284 0x0000, 0x0200, 0x0000,
1285 0x0000, 0x0000, 0x0200,
1286 },
1287 { 0x0, 0x0, 0x0, },
1288 { 0x0, 0x0, 0x0, },
1289 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1290 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1291 },
1292};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1293
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1294struct mdp_csc_cfg csc_matrix[3] = {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1295 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1296 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1297 {
1298 0x0254, 0x0000, 0x0331,
1299 0x0254, 0xff37, 0xfe60,
1300 0x0254, 0x0409, 0x0000,
1301 },
1302 {
1303 0xfff0, 0xff80, 0xff80,
1304 },
1305 {
1306 0, 0, 0,
1307 },
1308 {
1309 0, 0xff, 0, 0xff, 0, 0xff,
1310 },
1311 {
1312 0, 0xff, 0, 0xff, 0, 0xff,
1313 },
1314 },
1315 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1316 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1317 {
1318 0x0254, 0x0000, 0x0331,
1319 0x0254, 0xff37, 0xfe60,
1320 0x0254, 0x0409, 0x0000,
1321 },
1322 {
1323 0xfff0, 0xff80, 0xff80,
1324 },
1325 {
1326 0, 0, 0,
1327 },
1328 {
1329 0, 0xff, 0, 0xff, 0, 0xff,
1330 },
1331 {
1332 0, 0xff, 0, 0xff, 0, 0xff,
1333 },
1334 },
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1335 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1336 (0),
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1337 {
1338 0x0200, 0x0000, 0x0000,
1339 0x0000, 0x0200, 0x0000,
1340 0x0000, 0x0000, 0x0200,
1341 },
1342 {
1343 0x0, 0x0, 0x0,
1344 },
1345 {
1346 0, 0, 0,
1347 },
1348 {
1349 0, 0xff, 0, 0xff, 0, 0xff,
1350 },
1351 {
1352 0, 0xff, 0, 0xff, 0, 0xff,
1353 },
1354 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1355};
1356
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1357
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1358
1359#define MDP4_CSC_MV_OFF 0x4400
1360#define MDP4_CSC_PRE_BV_OFF 0x4500
1361#define MDP4_CSC_POST_BV_OFF 0x4580
1362#define MDP4_CSC_PRE_LV_OFF 0x4600
1363#define MDP4_CSC_POST_LV_OFF 0x4680
1364
1365void mdp4_vg_csc_mv_setup(int vp_num)
1366{
1367 uint32 *off;
1368 int i, voff;
1369
1370 voff = MDP4_VIDEO_OFF * vp_num;
1371 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1372 MDP4_CSC_MV_OFF);
1373
1374 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1375 for (i = 0; i < 9; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1376 outpdw(off, csc_matrix[vp_num].csc_mv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1377 off++;
1378 }
1379 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1380}
1381
1382void mdp4_vg_csc_pre_bv_setup(int vp_num)
1383{
1384 uint32 *off;
1385 int i, voff;
1386
1387 voff = MDP4_VIDEO_OFF * vp_num;
1388 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1389 MDP4_CSC_PRE_BV_OFF);
1390
1391 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1392 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1393 outpdw(off, csc_matrix[vp_num].csc_pre_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1394 off++;
1395 }
1396 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1397}
1398
1399void mdp4_vg_csc_post_bv_setup(int vp_num)
1400{
1401 uint32 *off;
1402 int i, voff;
1403
1404 voff = MDP4_VIDEO_OFF * vp_num;
1405 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1406 MDP4_CSC_POST_BV_OFF);
1407
1408 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1409 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1410 outpdw(off, csc_matrix[vp_num].csc_post_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1411 off++;
1412 }
1413 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1414}
1415
1416void mdp4_vg_csc_pre_lv_setup(int vp_num)
1417{
1418 uint32 *off;
1419 int i, voff;
1420
1421 voff = MDP4_VIDEO_OFF * vp_num;
1422 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1423 MDP4_CSC_PRE_LV_OFF);
1424
1425 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1426 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1427 outpdw(off, csc_matrix[vp_num].csc_pre_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1428 off++;
1429 }
1430 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1431}
1432
1433void mdp4_vg_csc_post_lv_setup(int vp_num)
1434{
1435 uint32 *off;
1436 int i, voff;
1437
1438 voff = MDP4_VIDEO_OFF * vp_num;
1439 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1440 MDP4_CSC_POST_LV_OFF);
1441
1442 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1443 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1444 outpdw(off, csc_matrix[vp_num].csc_post_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1445 off++;
1446 }
1447 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1448}
1449
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1450void mdp4_vg_csc_convert_setup(int vp_num)
1451{
1452 struct mdp_csc_cfg_data cfg;
1453
1454 switch (vp_num) {
1455 case 0:
1456 cfg.block = MDP_BLOCK_VG_1;
1457 break;
1458 case 1:
1459 cfg.block = MDP_BLOCK_VG_2;
1460 break;
1461 default:
1462 pr_err("%s - invalid vp_num = %d", __func__, vp_num);
1463 return;
1464 }
1465 cfg.csc_data = csc_matrix[vp_num];
1466 mdp4_csc_enable(&cfg);
1467}
1468
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1469void mdp4_vg_csc_setup(int vp_num)
1470{
1471 /* yuv2rgb */
1472 mdp4_vg_csc_mv_setup(vp_num);
1473 mdp4_vg_csc_pre_bv_setup(vp_num);
1474 mdp4_vg_csc_post_bv_setup(vp_num);
1475 mdp4_vg_csc_pre_lv_setup(vp_num);
1476 mdp4_vg_csc_post_lv_setup(vp_num);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1477 mdp4_vg_csc_convert_setup(vp_num);
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1478}
1479void mdp4_vg_csc_update(struct mdp_csc *p)
1480{
1481 struct mdp4_overlay_pipe *pipe;
1482 int vp_num;
1483
1484 pipe = mdp4_overlay_ndx2pipe(p->id);
1485 if (pipe == NULL) {
1486 pr_err("%s: p->id = %d Error\n", __func__, p->id);
1487 return;
1488 }
1489
1490 vp_num = pipe->pipe_num - OVERLAY_PIPE_VG1;
1491
1492 if (vp_num == 0 || vp_num == 1) {
1493 memcpy(csc_matrix[vp_num].csc_mv, p->csc_mv, sizeof(p->csc_mv));
1494 memcpy(csc_matrix[vp_num].csc_pre_bv, p->csc_pre_bv,
1495 sizeof(p->csc_pre_bv));
1496 memcpy(csc_matrix[vp_num].csc_post_bv, p->csc_post_bv,
1497 sizeof(p->csc_post_bv));
1498 memcpy(csc_matrix[vp_num].csc_pre_lv, p->csc_pre_lv,
1499 sizeof(p->csc_pre_lv));
1500 memcpy(csc_matrix[vp_num].csc_post_lv, p->csc_post_lv,
1501 sizeof(p->csc_post_lv));
1502 mdp4_vg_csc_setup(vp_num);
1503 }
1504}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1505static uint32 csc_rgb2yuv_matrix_tab[9] = {
1506 0x0083, 0x0102, 0x0032,
1507 0x1fb5, 0x1f6c, 0x00e1,
1508 0x00e1, 0x1f45, 0x1fdc
1509};
1510
1511static uint32 csc_rgb2yuv_pre_bv_tab[3] = {0, 0, 0};
1512
1513static uint32 csc_rgb2yuv_post_bv_tab[3] = {0x0010, 0x0080, 0x0080};
1514
1515static uint32 csc_rgb2yuv_pre_lv_tab[6] = {
1516 0x00, 0xff, 0x00,
1517 0xff, 0x00, 0xff
1518};
1519
1520static uint32 csc_rgb2yuv_post_lv_tab[6] = {
1521 0x0010, 0x00eb, 0x0010,
1522 0x00f0, 0x0010, 0x00f0
1523};
1524
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1525void mdp4_mixer_csc_mv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1526{
1527 uint32 *off;
1528 int i;
1529
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1530 if (mixer == MDP4_MIXER1)
1531 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2400);
1532 else
1533 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2400);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1534
1535 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1536 for (i = 0; i < 9; i++) {
1537 outpdw(off, csc_rgb2yuv_matrix_tab[i]);
1538 off++;
1539 }
1540 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1541}
1542
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1543void mdp4_mixer_csc_pre_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1544{
1545 uint32 *off;
1546 int i;
1547
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1548 if (mixer == MDP4_MIXER1)
1549 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2500);
1550 else
1551 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2500);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1552
1553 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1554 for (i = 0; i < 3; i++) {
1555 outpdw(off, csc_rgb2yuv_pre_bv_tab[i]);
1556 off++;
1557 }
1558 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1559}
1560
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1561void mdp4_mixer_csc_post_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1562{
1563 uint32 *off;
1564 int i;
1565
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1566 if (mixer == MDP4_MIXER1)
1567 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2580);
1568 else
1569 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2580);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1570
1571 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1572 for (i = 0; i < 3; i++) {
1573 outpdw(off, csc_rgb2yuv_post_bv_tab[i]);
1574 off++;
1575 }
1576 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1577}
1578
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1579void mdp4_mixer_csc_pre_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1580{
1581 uint32 *off;
1582 int i;
1583
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1584 if (mixer == MDP4_MIXER1)
1585 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2600);
1586 else
1587 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2600);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1588
1589 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1590 for (i = 0; i < 6; i++) {
1591 outpdw(off, csc_rgb2yuv_pre_lv_tab[i]);
1592 off++;
1593 }
1594 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1595}
1596
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1597void mdp4_mixer_csc_post_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1598{
1599 uint32 *off;
1600 int i;
1601
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1602 if (mixer == MDP4_MIXER1)
1603 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2680);
1604 else
1605 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2680);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1606
1607 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1608 for (i = 0; i < 6; i++) {
1609 outpdw(off, csc_rgb2yuv_post_lv_tab[i]);
1610 off++;
1611 }
1612 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1613}
1614
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1615void mdp4_mixer_csc_setup(uint32 mixer)
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1616{
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1617 if (mixer >= MDP4_MIXER1) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1618 /* rgb2yuv */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1619 mdp4_mixer_csc_mv_setup(mixer);
1620 mdp4_mixer_csc_pre_bv_setup(mixer);
1621 mdp4_mixer_csc_post_bv_setup(mixer);
1622 mdp4_mixer_csc_pre_lv_setup(mixer);
1623 mdp4_mixer_csc_post_lv_setup(mixer);
1624 }
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1625}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1626
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1627#define DMA_P_BASE 0x90000
1628void mdp4_dmap_csc_mv_setup(void)
1629{
1630 uint32 *off;
1631 int i;
1632
1633 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3400);
1634
1635 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1636 for (i = 0; i < 9; i++) {
1637 outpdw(off, csc_matrix[2].csc_mv[i]);
1638 off++;
1639 }
1640 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1641}
1642
1643void mdp4_dmap_csc_pre_bv_setup(void)
1644{
1645 uint32 *off;
1646 int i;
1647
1648 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3500);
1649
1650 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1651 for (i = 0; i < 3; i++) {
1652 outpdw(off, csc_matrix[2].csc_pre_bv[i]);
1653 off++;
1654 }
1655 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1656}
1657
1658void mdp4_dmap_csc_post_bv_setup(void)
1659{
1660 uint32 *off;
1661 int i;
1662
1663 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3580);
1664
1665 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1666 for (i = 0; i < 3; i++) {
1667 outpdw(off, csc_matrix[2].csc_post_bv[i]);
1668 off++;
1669 }
1670 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1671}
1672
1673void mdp4_dmap_csc_pre_lv_setup(void)
1674{
1675 uint32 *off;
1676 int i;
1677
1678 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3600);
1679
1680 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1681 for (i = 0; i < 6; i++) {
1682 outpdw(off, csc_matrix[2].csc_pre_lv[i]);
1683 off++;
1684 }
1685 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1686}
1687
1688void mdp4_dmap_csc_post_lv_setup(void)
1689{
1690 uint32 *off;
1691 int i;
1692
1693 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3680);
1694
1695 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1696 for (i = 0; i < 6; i++) {
1697 outpdw(off, csc_matrix[2].csc_post_lv[i]);
1698 off++;
1699 }
1700 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1701}
1702
1703void mdp4_dmap_csc_setup(void)
1704{
1705 mdp4_dmap_csc_mv_setup();
1706 mdp4_dmap_csc_pre_bv_setup();
1707 mdp4_dmap_csc_post_bv_setup();
1708 mdp4_dmap_csc_pre_lv_setup();
1709 mdp4_dmap_csc_post_lv_setup();
1710}
1711
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1712char gc_lut[] = {
1713 0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
1714 0x6, 0x7, 0x8, 0x9, 0xA, 0xA, 0xB, 0xC,
1715 0xD, 0xD, 0xE, 0xF, 0xF, 0x10, 0x10, 0x11,
1716 0x12, 0x12, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15,
1717 0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x19,
1718 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C,
1719 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F,
1720 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21,
1721 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24,
1722 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x26, 0x26,
1723 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x28,
1724 0x28, 0x29, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A,
1725 0x2A, 0x2B, 0x2B, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C,
1726 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E,
1727 0x2E, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x2F, 0x30,
1728 0x30, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31,
1729 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33,
1730 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x34, 0x34,
1731 0x35, 0x35, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36,
1732 0x36, 0x36, 0x37, 0x37, 0x37, 0x37, 0x37, 0x37,
1733 0x38, 0x38, 0x38, 0x38, 0x38, 0x39, 0x39, 0x39,
1734 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A,
1735 0x3A, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3C,
1736 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D,
1737 0x3D, 0x3D, 0x3D, 0x3E, 0x3E, 0x3E, 0x3E, 0x3E,
1738 0x3E, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x40,
1739 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41,
1740 0x41, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, 0x42,
1741 0x42, 0x42, 0x42, 0x43, 0x43, 0x43, 0x43, 0x43,
1742 0x43, 0x43, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
1743 0x44, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45,
1744 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x47,
1745 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x48, 0x48,
1746 0x48, 0x48, 0x48, 0x48, 0x48, 0x48, 0x49, 0x49,
1747 0x49, 0x49, 0x49, 0x49, 0x49, 0x4A, 0x4A, 0x4A,
1748 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 0x4B,
1749 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4C, 0x4C, 0x4C,
1750 0x4C, 0x4C, 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4D,
1751 0x4D, 0x4D, 0x4D, 0x4D, 0x4E, 0x4E, 0x4E, 0x4E,
1752 0x4E, 0x4E, 0x4E, 0x4E, 0x4E, 0x4F, 0x4F, 0x4F,
1753 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x50, 0x50, 0x50,
1754 0x50, 0x50, 0x50, 0x50, 0x50, 0x51, 0x51, 0x51,
1755 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
1756 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x53, 0x53,
1757 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x54,
1758 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54,
1759 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
1760 0x55, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56,
1761 0x56, 0x56, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57,
1762 0x57, 0x57, 0x57, 0x58, 0x58, 0x58, 0x58, 0x58,
1763 0x58, 0x58, 0x58, 0x58, 0x58, 0x59, 0x59, 0x59,
1764 0x59, 0x59, 0x59, 0x59, 0x59, 0x59, 0x5A, 0x5A,
1765 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
1766 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B,
1767 0x5B, 0x5B, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C,
1768 0x5C, 0x5C, 0x5C, 0x5C, 0x5D, 0x5D, 0x5D, 0x5D,
1769 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5E, 0x5E,
1770 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E,
1771 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F,
1772 0x5F, 0x5F, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60,
1773 0x60, 0x60, 0x60, 0x60, 0x60, 0x61, 0x61, 0x61,
1774 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x62,
1775 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62,
1776 0x62, 0x62, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
1777 0x63, 0x63, 0x63, 0x63, 0x63, 0x64, 0x64, 0x64,
1778 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
1779 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65,
1780 0x65, 0x65, 0x65, 0x66, 0x66, 0x66, 0x66, 0x66,
1781 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x67, 0x67,
1782 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67,
1783 0x67, 0x67, 0x68, 0x68, 0x68, 0x68, 0x68, 0x68,
1784 0x68, 0x68, 0x68, 0x68, 0x68, 0x69, 0x69, 0x69,
1785 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
1786 0x69, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A,
1787 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6B, 0x6B, 0x6B,
1788 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B,
1789 0x6B, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C,
1790 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D,
1791 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
1792 0x6D, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E,
1793 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6F, 0x6F, 0x6F,
1794 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F,
1795 0x6F, 0x6F, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
1796 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x71, 0x71,
1797 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
1798 0x71, 0x71, 0x71, 0x72, 0x72, 0x72, 0x72, 0x72,
1799 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72,
1800 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73,
1801 0x73, 0x73, 0x73, 0x73, 0x73, 0x74, 0x74, 0x74,
1802 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74,
1803 0x74, 0x74, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1804 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1805 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76,
1806 0x76, 0x76, 0x76, 0x76, 0x76, 0x77, 0x77, 0x77,
1807 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,
1808 0x77, 0x77, 0x77, 0x78, 0x78, 0x78, 0x78, 0x78,
1809 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
1810 0x78, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79,
1811 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x7A, 0x7A,
1812 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A,
1813 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7B, 0x7B, 0x7B,
1814 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B,
1815 0x7B, 0x7B, 0x7B, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1816 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1817 0x7C, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1818 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1819 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E,
1820 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7F, 0x7F,
1821 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F,
1822 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x80, 0x80, 0x80,
1823 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1824 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
1825 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
1826 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82,
1827 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82,
1828 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1829 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1830 0x83, 0x83, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1831 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1832 0x84, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1833 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1834 0x85, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1835 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1836 0x86, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1837 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1838 0x87, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1839 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1840 0x88, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1841 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1842 0x89, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1843 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1844 0x8A, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1845 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1846 0x8B, 0x8B, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1847 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1848 0x8C, 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1849 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1850 0x8D, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8E, 0x8E,
1851 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E,
1852 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8F, 0x8F, 0x8F,
1853 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F,
1854 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x90, 0x90,
1855 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90,
1856 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x91,
1857 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1858 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1859 0x91, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1860 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1861 0x92, 0x92, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1862 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1863 0x93, 0x93, 0x93, 0x93, 0x94, 0x94, 0x94, 0x94,
1864 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94,
1865 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x95, 0x95,
1866 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1867 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1868 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1869 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1870 0x96, 0x96, 0x96, 0x97, 0x97, 0x97, 0x97, 0x97,
1871 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97,
1872 0x97, 0x97, 0x97, 0x97, 0x97, 0x98, 0x98, 0x98,
1873 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1874 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1875 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1876 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1877 0x99, 0x99, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1878 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1879 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9B, 0x9B, 0x9B,
1880 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1881 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1882 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1883 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1884 0x9C, 0x9C, 0x9C, 0x9C, 0x9D, 0x9D, 0x9D, 0x9D,
1885 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
1886 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9E,
1887 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1888 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1889 0x9E, 0x9E, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1890 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1891 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0xA0, 0xA0,
1892 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1893 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1894 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1895 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1896 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2,
1897 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1898 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1899 0xA2, 0xA2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1900 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1901 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA4, 0xA4,
1902 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1903 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1904 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1905 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1906 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1907 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1908 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1909 0xA6, 0xA6, 0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA7,
1910 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1911 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1912 0xA7, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1913 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1914 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA9,
1915 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1916 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1917 0xA9, 0xA9, 0xA9, 0xA9, 0xAA, 0xAA, 0xAA, 0xAA,
1918 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1919 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1920 0xAA, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1921 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1922 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAC,
1923 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1924 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1925 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAD, 0xAD, 0xAD,
1926 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1927 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1928 0xAD, 0xAD, 0xAD, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1929 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1930 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1931 0xAE, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1932 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1933 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xB0,
1934 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1935 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1936 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB1,
1937 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1938 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1939 0xB1, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB2, 0xB2,
1940 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1941 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1942 0xB2, 0xB2, 0xB2, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1943 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1944 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1945 0xB3, 0xB3, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1946 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1947 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1948 0xB4, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1949 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1950 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1951 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1952 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1953 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1954 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1955 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1956 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB8,
1957 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1958 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1959 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB9,
1960 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1961 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1962 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xBA,
1963 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1964 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1965 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBB,
1966 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1967 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1968 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1969 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1970 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1971 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1972 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1973 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1974 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1975 0xBD, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1976 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1977 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1978 0xBE, 0xBE, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1979 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1980 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1981 0xBF, 0xBF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1982 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1983 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1984 0xC0, 0xC0, 0xC0, 0xC0, 0xC1, 0xC1, 0xC1, 0xC1,
1985 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1986 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1987 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC2, 0xC2, 0xC2,
1988 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1989 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1990 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC3, 0xC3,
1991 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1992 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1993 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1994 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1995 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1996 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1997 0xC4, 0xC4, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1998 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1999 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
2000 0xC5, 0xC5, 0xC5, 0xC5, 0xC6, 0xC6, 0xC6, 0xC6,
2001 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
2002 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
2003 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC7, 0xC7,
2004 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2005 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2006 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2007 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2008 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2009 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2010 0xC8, 0xC8, 0xC8, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2011 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2012 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2013 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xCA, 0xCA,
2014 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2015 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2016 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2017 0xCA, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2018 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2019 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2020 0xCB, 0xCB, 0xCB, 0xCB, 0xCC, 0xCC, 0xCC, 0xCC,
2021 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2022 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2023 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCD,
2024 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2025 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2026 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2027 0xCD, 0xCD, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2028 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2029 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2030 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCF, 0xCF,
2031 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2032 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2033 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2034 0xCF, 0xCF, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2035 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2036 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2037 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD1, 0xD1, 0xD1,
2038 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2039 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2040 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2041 0xD1, 0xD1, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2042 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2043 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2044 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD3, 0xD3,
2045 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2046 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2047 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2048 0xD3, 0xD3, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2049 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2050 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2051 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD5,
2052 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2053 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2054 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2055 0xD5, 0xD5, 0xD5, 0xD5, 0xD6, 0xD6, 0xD6, 0xD6,
2056 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2057 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2058 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2059 0xD6, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2060 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2061 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2062 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD8, 0xD8,
2063 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2064 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2065 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2066 0xD8, 0xD8, 0xD8, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2067 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2068 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2069 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2070 0xD9, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2071 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2072 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2073 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDB, 0xDB,
2074 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2075 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2076 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2077 0xDB, 0xDB, 0xDB, 0xDB, 0xDC, 0xDC, 0xDC, 0xDC,
2078 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2079 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2080 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2081 0xDC, 0xDC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2082 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2083 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2084 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2085 0xDD, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2086 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2087 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2088 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDF,
2089 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2090 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2091 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2092 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xE0, 0xE0,
2093 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2094 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2095 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2096 0xE0, 0xE0, 0xE0, 0xE0, 0xE1, 0xE1, 0xE1, 0xE1,
2097 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2098 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2099 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2100 0xE1, 0xE1, 0xE1, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2101 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2102 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2103 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2104 0xE2, 0xE2, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2105 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2106 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2107 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2108 0xE3, 0xE3, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2109 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2110 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2111 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2112 0xE4, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2113 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2114 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2115 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2116 0xE5, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2117 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2118 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2119 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2120 0xE6, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2121 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2122 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2123 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2124 0xE7, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2125 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2126 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2127 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2128 0xE8, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2129 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2130 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2131 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2132 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2133 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2134 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2135 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2136 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2137 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2138 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2139 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2140 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2141 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2142 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2143 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2144 0xEC, 0xEC, 0xEC, 0xEC, 0xED, 0xED, 0xED, 0xED,
2145 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2146 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2147 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2148 0xED, 0xED, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE,
2149 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2150 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2151 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2152 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF,
2153 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2154 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2155 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2156 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2157 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2158 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2159 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2160 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2161 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2162 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2163 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2164 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2165 0xF1, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF2, 0xF2,
2166 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2167 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2168 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2169 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF3, 0xF3,
2170 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2171 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2172 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2173 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2174 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2175 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2176 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2177 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2178 0xF4, 0xF4, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2179 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2180 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2181 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2182 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6,
2183 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2184 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2185 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2186 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2187 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2188 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2189 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2190 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2191 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2192 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2193 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2194 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2195 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9,
2196 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2197 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2198 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2199 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2200 0xF9, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2201 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2202 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2203 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2204 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB,
2205 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2206 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2207 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2208 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2209 0xFB, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2210 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2211 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2212 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2213 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFD, 0xFD, 0xFD,
2214 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2215 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2216 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2217 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2218 0xFD, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2219 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2220 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2221 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2222 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF,
2223 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2224 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2225};
2226
2227void mdp4_mixer_gc_lut_setup(int mixer_num)
2228{
2229 unsigned char *base;
2230 uint32 data;
2231 char val;
2232 int i, off;
2233
2234 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
2235 base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
2236 else
2237 base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
2238
2239 base += 0x4000; /* GC_LUT offset */
2240
2241 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2242 off = 0;
2243 for (i = 0; i < 4096; i++) {
2244 val = gc_lut[i];
2245 data = (val << 16 | val << 8 | val); /* R, B, and G are same */
2246 outpdw(base + off, data);
2247 off += 4;
2248 }
2249 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2250}
2251
2252uint32 igc_video_lut[] = { /* non linear */
2253 0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x7, 0x9,
2254 0xA, 0xB, 0xC, 0xE, 0xF, 0x10, 0x12, 0x14,
2255 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x21, 0x23,
2256 0x25, 0x28, 0x2A, 0x2D, 0x30, 0x32, 0x35, 0x38,
2257 0x3B, 0x3E, 0x42, 0x45, 0x48, 0x4C, 0x4F, 0x53,
2258 0x57, 0x5B, 0x5F, 0x63, 0x67, 0x6B, 0x70, 0x74,
2259 0x79, 0x7E, 0x83, 0x88, 0x8D, 0x92, 0x97, 0x9C,
2260 0xA2, 0xA8, 0xAD, 0xB3, 0xB9, 0xBF, 0xC5, 0xCC,
2261 0xD2, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, 0xFB, 0x102,
2262 0x109, 0x111, 0x118, 0x120, 0x128, 0x130, 0x138, 0x140,
2263 0x149, 0x151, 0x15A, 0x162, 0x16B, 0x174, 0x17D, 0x186,
2264 0x190, 0x199, 0x1A3, 0x1AC, 0x1B6, 0x1C0, 0x1CA, 0x1D5,
2265 0x1DF, 0x1EA, 0x1F4, 0x1FF, 0x20A, 0x215, 0x220, 0x22B,
2266 0x237, 0x242, 0x24E, 0x25A, 0x266, 0x272, 0x27F, 0x28B,
2267 0x298, 0x2A4, 0x2B1, 0x2BE, 0x2CB, 0x2D8, 0x2E6, 0x2F3,
2268 0x301, 0x30F, 0x31D, 0x32B, 0x339, 0x348, 0x356, 0x365,
2269 0x374, 0x383, 0x392, 0x3A1, 0x3B1, 0x3C0, 0x3D0, 0x3E0,
2270 0x3F0, 0x400, 0x411, 0x421, 0x432, 0x443, 0x454, 0x465,
2271 0x476, 0x487, 0x499, 0x4AB, 0x4BD, 0x4CF, 0x4E1, 0x4F3,
2272 0x506, 0x518, 0x52B, 0x53E, 0x551, 0x565, 0x578, 0x58C,
2273 0x5A0, 0x5B3, 0x5C8, 0x5DC, 0x5F0, 0x605, 0x61A, 0x62E,
2274 0x643, 0x659, 0x66E, 0x684, 0x699, 0x6AF, 0x6C5, 0x6DB,
2275 0x6F2, 0x708, 0x71F, 0x736, 0x74D, 0x764, 0x77C, 0x793,
2276 0x7AB, 0x7C3, 0x7DB, 0x7F3, 0x80B, 0x824, 0x83D, 0x855,
2277 0x86F, 0x888, 0x8A1, 0x8BB, 0x8D4, 0x8EE, 0x908, 0x923,
2278 0x93D, 0x958, 0x973, 0x98E, 0x9A9, 0x9C4, 0x9DF, 0x9FB,
2279 0xA17, 0xA33, 0xA4F, 0xA6C, 0xA88, 0xAA5, 0xAC2, 0xADF,
2280 0xAFC, 0xB19, 0xB37, 0xB55, 0xB73, 0xB91, 0xBAF, 0xBCE,
2281 0xBEC, 0xC0B, 0xC2A, 0xC4A, 0xC69, 0xC89, 0xCA8, 0xCC8,
2282 0xCE8, 0xD09, 0xD29, 0xD4A, 0xD6B, 0xD8C, 0xDAD, 0xDCF,
2283 0xDF0, 0xE12, 0xE34, 0xE56, 0xE79, 0xE9B, 0xEBE, 0xEE1,
2284 0xF04, 0xF27, 0xF4B, 0xF6E, 0xF92, 0xFB6, 0xFDB, 0xFFF,
2285};
2286
2287void mdp4_vg_igc_lut_setup(int vp_num)
2288{
2289 unsigned char *base;
2290 int i, voff, off;
2291 uint32 data, val;
2292
2293 voff = MDP4_VIDEO_OFF * vp_num;
2294 base = MDP_BASE + MDP4_VIDEO_BASE + voff + 0x5000;
2295
2296 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2297 off = 0;
2298 for (i = 0; i < 256; i++) {
2299 val = igc_video_lut[i];
2300 data = (val << 16 | val); /* color 0 and 1 */
2301 outpdw(base + off, data);
2302 outpdw(base + off + 0x800, val); /* color 2 */
2303 off += 4;
2304 }
2305 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2306}
2307
2308uint32 igc_rgb_lut[] = { /* linear */
2309 0x0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
2310 0x80, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, 0xE1, 0xF1,
2311 0x101, 0x111, 0x121, 0x131, 0x141, 0x151, 0x161, 0x171,
2312 0x181, 0x191, 0x1A2, 0x1B2, 0x1C2, 0x1D2, 0x1E2, 0x1F2,
2313 0x202, 0x212, 0x222, 0x232, 0x242, 0x252, 0x262, 0x272,
2314 0x282, 0x292, 0x2A2, 0x2B3, 0x2C3, 0x2D3, 0x2E3, 0x2F3,
2315 0x303, 0x313, 0x323, 0x333, 0x343, 0x353, 0x363, 0x373,
2316 0x383, 0x393, 0x3A3, 0x3B3, 0x3C4, 0x3D4, 0x3E4, 0x3F4,
2317 0x404, 0x414, 0x424, 0x434, 0x444, 0x454, 0x464, 0x474,
2318 0x484, 0x494, 0x4A4, 0x4B4, 0x4C4, 0x4D5, 0x4E5, 0x4F5,
2319 0x505, 0x515, 0x525, 0x535, 0x545, 0x555, 0x565, 0x575,
2320 0x585, 0x595, 0x5A5, 0x5B5, 0x5C5, 0x5D5, 0x5E6, 0x5F6,
2321 0x606, 0x616, 0x626, 0x636, 0x646, 0x656, 0x666, 0x676,
2322 0x686, 0x696, 0x6A6, 0x6B6, 0x6C6, 0x6D6, 0x6E6, 0x6F7,
2323 0x707, 0x717, 0x727, 0x737, 0x747, 0x757, 0x767, 0x777,
2324 0x787, 0x797, 0x7A7, 0x7B7, 0x7C7, 0x7D7, 0x7E7, 0x7F7,
2325 0x808, 0x818, 0x828, 0x838, 0x848, 0x858, 0x868, 0x878,
2326 0x888, 0x898, 0x8A8, 0x8B8, 0x8C8, 0x8D8, 0x8E8, 0x8F8,
2327 0x908, 0x919, 0x929, 0x939, 0x949, 0x959, 0x969, 0x979,
2328 0x989, 0x999, 0x9A9, 0x9B9, 0x9C9, 0x9D9, 0x9E9, 0x9F9,
2329 0xA09, 0xA19, 0xA2A, 0xA3A, 0xA4A, 0xA5A, 0xA6A, 0xA7A,
2330 0xA8A, 0xA9A, 0xAAA, 0xABA, 0xACA, 0xADA, 0xAEA, 0xAFA,
2331 0xB0A, 0xB1A, 0xB2A, 0xB3B, 0xB4B, 0xB5B, 0xB6B, 0xB7B,
2332 0xB8B, 0xB9B, 0xBAB, 0xBBB, 0xBCB, 0xBDB, 0xBEB, 0xBFB,
2333 0xC0B, 0xC1B, 0xC2B, 0xC3B, 0xC4C, 0xC5C, 0xC6C, 0xC7C,
2334 0xC8C, 0xC9C, 0xCAC, 0xCBC, 0xCCC, 0xCDC, 0xCEC, 0xCFC,
2335 0xD0C, 0xD1C, 0xD2C, 0xD3C, 0xD4C, 0xD5D, 0xD6D, 0xD7D,
2336 0xD8D, 0xD9D, 0xDAD, 0xDBD, 0xDCD, 0xDDD, 0xDED, 0xDFD,
2337 0xE0D, 0xE1D, 0xE2D, 0xE3D, 0xE4D, 0xE5D, 0xE6E, 0xE7E,
2338 0xE8E, 0xE9E, 0xEAE, 0xEBE, 0xECE, 0xEDE, 0xEEE, 0xEFE,
2339 0xF0E, 0xF1E, 0xF2E, 0xF3E, 0xF4E, 0xF5E, 0xF6E, 0xF7F,
2340 0xF8F, 0xF9F, 0xFAF, 0xFBF, 0xFCF, 0xFDF, 0xFEF, 0xFFF,
2341};
2342
2343void mdp4_rgb_igc_lut_setup(int num)
2344{
2345 unsigned char *base;
2346 int i, voff, off;
2347 uint32 data, val;
2348
2349 voff = MDP4_RGB_OFF * num;
2350 base = MDP_BASE + MDP4_RGB_BASE + voff + 0x5000;
2351
2352 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2353 off = 0;
2354 for (i = 0; i < 256; i++) {
2355 val = igc_rgb_lut[i];
2356 data = (val << 16 | val); /* color 0 and 1 */
2357 outpdw(base + off, data);
2358 outpdw(base + off + 0x800, val); /* color 2 */
2359 off += 4;
2360 }
2361 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2362}
2363
2364uint32 mdp4_rgb_igc_lut_cvt(uint32 ndx)
2365{
2366 return igc_rgb_lut[ndx & 0x0ff];
2367}
2368
2369uint32_t mdp4_ss_table_value(int8_t value, int8_t index)
2370{
2371 uint32_t out = 0x0;
2372 int8_t level = -1;
2373 uint32_t mask = 0xffffffff;
2374
2375 if (value < 0) {
2376 if (value == -128)
2377 value = 127;
2378 else
2379 value = -value;
2380 out = 0x11111111;
2381 } else {
2382 out = 0x88888888;
2383 mask = 0x0fffffff;
2384 }
2385
2386 if (value == 0)
2387 level = 0;
2388 else {
2389 while (value > 0 && level < 7) {
2390 level++;
2391 value -= 16;
2392 }
2393 }
2394
2395 if (level == 0) {
2396 if (index == 0)
2397 out = 0x0;
2398 else
2399 out = 0x20000000;
2400 } else {
2401 out += (0x11111111 * level);
2402 if (index == 1)
2403 out &= mask;
2404 }
2405
2406 return out;
2407}
2408
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2409static uint32_t mdp4_csc_block2base(uint32_t block)
2410{
2411 uint32_t base = 0x0;
2412 switch (block) {
2413 case MDP_BLOCK_OVERLAY_1:
2414 base = 0x1A000;
2415 break;
2416 case MDP_BLOCK_VG_1:
2417 base = 0x24000;
2418 break;
2419 case MDP_BLOCK_VG_2:
2420 base = 0x34000;
2421 break;
2422 case MDP_BLOCK_DMA_P:
2423 base = 0x93000;
2424 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2425 case MDP_BLOCK_DMA_S:
2426 base = (mdp_rev >= MDP_REV_42) ? 0xA3000 : 0x0;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2427 default:
2428 break;
2429 }
2430 return base;
2431}
2432
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2433int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2434{
2435 uint32_t output, base, temp, mask;
2436
2437 switch (config->block) {
2438 case MDP_BLOCK_DMA_P:
2439 base = 0x90070;
2440 output = (config->csc_data.flags << 3) & (0x08);
2441 temp = (config->csc_data.flags << 10) & (0x1800);
2442 output |= temp;
2443 mask = 0x08 | 0x1800;
2444 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2445 case MDP_BLOCK_DMA_S:
2446 base = 0xA0028;
2447 output = (config->csc_data.flags << 3) & (0x08);
2448 temp = (config->csc_data.flags << 10) & (0x1800);
2449 output |= temp;
2450 mask = 0x08 | 0x1800;
2451 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2452 case MDP_BLOCK_VG_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2453 base = 0x20058;
2454 output = (config->csc_data.flags << 11) & (0x800);
2455 temp = (config->csc_data.flags << 8) & (0x600);
2456 output |= temp;
2457 mask = 0x800 | 0x600;
2458 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2459 case MDP_BLOCK_VG_2:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2460 base = 0x30058;
2461 output = (config->csc_data.flags << 11) & (0x800);
2462 temp = (config->csc_data.flags << 8) & (0x600);
2463 output |= temp;
2464 mask = 0x800 | 0x600;
2465 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2466 case MDP_BLOCK_OVERLAY_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2467 base = 0x18200;
2468 output = config->csc_data.flags;
2469 mask = 0x07;
2470 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2471 default:
2472 pr_err("%s - CSC block does not exist on MDP_BLOCK = %d\n",
2473 __func__, config->block);
2474 return -EINVAL;
2475 }
2476
2477 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2478 temp = inpdw(MDP_BASE + base) & ~mask;
2479 output |= temp;
2480 outpdw(MDP_BASE + base, output);
2481 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2482 return 0;
2483}
2484
2485#define CSC_MV_OFF 0x400
2486#define CSC_BV_OFF 0x500
2487#define CSC_LV_OFF 0x600
2488#define CSC_POST_OFF 0x80
2489
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2490void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2491{
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2492 int i;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2493 uint32_t *off;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2494
2495 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2496 off = (uint32_t *) ((uint32_t) base + CSC_MV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2497 for (i = 0; i < 9; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2498 outpdw(off, data->csc_mv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2499 off++;
2500 }
2501
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2502 off = (uint32_t *) ((uint32_t) base + CSC_BV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2503 for (i = 0; i < 3; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2504 outpdw(off, data->csc_pre_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2505 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2506 data->csc_post_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2507 off++;
2508 }
2509
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2510 off = (uint32_t *) ((uint32_t) base + CSC_LV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2511 for (i = 0; i < 6; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2512 outpdw(off, data->csc_pre_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2513 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2514 data->csc_post_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2515 off++;
2516 }
2517 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2518}
2519
2520int mdp4_csc_config(struct mdp_csc_cfg_data *config)
2521{
2522 int ret = 0;
2523 uint32_t base;
2524
2525 base = mdp4_csc_block2base(config->block);
2526 if (!base) {
2527 pr_warn("%s: Block type %d isn't supported by CSC.\n",
2528 __func__, config->block);
2529 return -EINVAL;
2530 }
2531
2532 mdp4_csc_write(&config->csc_data, (uint32_t) (MDP_BASE + base));
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2533
2534 ret = mdp4_csc_enable(config);
2535
2536 return ret;
2537}
2538
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2539void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2540{
2541 struct mdp_buf_type *buf;
2542
2543 if (mix_num == MDP4_MIXER0)
2544 buf = mfd->ov0_wb_buf;
2545 else
2546 buf = mfd->ov1_wb_buf;
2547
2548 buf->ihdl = NULL;
2549 buf->phys_addr = 0;
2550}
2551
2552u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2553{
2554 struct mdp_buf_type *buf;
2555 ion_phys_addr_t addr;
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2556 size_t buffer_size;
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]2557 unsigned long len;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2558
2559 if (mix_num == MDP4_MIXER0)
2560 buf = mfd->ov0_wb_buf;
2561 else
2562 buf = mfd->ov1_wb_buf;
2563
2564 if (buf->phys_addr || !IS_ERR_OR_NULL(buf->ihdl))
2565 return 0;
2566
2567 if (!buf->size) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2568 pr_err("%s:%d In valid size\n", __func__, __LINE__);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2569 return -EINVAL;
2570 }
2571
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2572 buffer_size = roundup(mfd->panel_info.xres * \
2573 mfd->panel_info.yres * 3 * 2, SZ_4K);
2574
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2575 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanama3b168b2012-03-26 11:13:11 -0700[diff] [blame]2576 pr_info("%s:%d ion based allocation mfd->mem_hid 0x%x\n",
2577 __func__, __LINE__, mfd->mem_hid);
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2578 buf->ihdl = ion_alloc(mfd->iclient, buffer_size, SZ_4K,
Ravishangar Kalyanama3b168b2012-03-26 11:13:11 -0700[diff] [blame]2579 mfd->mem_hid);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2580 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]2581 if (ion_map_iommu(mfd->iclient, buf->ihdl,
2582 DISPLAY_DOMAIN, GEN_POOL, SZ_4K, 0, &addr,
2583 &len, 0, 0)) {
2584 pr_err("ion_map_iommu() failed\n");
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2585 return -ENOMEM;
2586 }
2587 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2588 pr_err("%s:%d: ion_alloc failed\n", __func__,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2589 __LINE__);
2590 return -ENOMEM;
2591 }
2592 } else {
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2593 addr = allocate_contiguous_memory_nomap(buffer_size,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2594 mfd->mem_hid, 4);
2595 }
2596 if (addr) {
2597 pr_info("allocating %d bytes at %x for mdp writeback\n",
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2598 buffer_size, (u32) addr);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2599 buf->phys_addr = addr;
2600 return 0;
2601 } else {
2602 pr_err("%s cannot allocate memory for mdp writeback!\n",
2603 __func__);
2604 return -ENOMEM;
2605 }
2606}
2607
2608void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2609{
2610 struct mdp_buf_type *buf;
2611
2612 if (mix_num == MDP4_MIXER0)
2613 buf = mfd->ov0_wb_buf;
2614 else
2615 buf = mfd->ov1_wb_buf;
2616
2617 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2618 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]2619 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2620 DISPLAY_DOMAIN, GEN_POOL);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2621 ion_free(mfd->iclient, buf->ihdl);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2622 pr_debug("%s:%d free writeback imem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2623 __LINE__);
2624 buf->ihdl = NULL;
2625 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2626 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2627 if (buf->phys_addr) {
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2628 free_contiguous_memory_by_paddr(buf->phys_addr);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2629 pr_debug("%s:%d free writeback pmem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2630 __LINE__);
2631 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2632 }
2633 buf->phys_addr = 0;
2634}
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2635
2636static int mdp4_update_pcc_regs(uint32_t offset,
2637 struct mdp_pcc_cfg_data *cfg_ptr)
2638{
2639 int ret = -1;
2640
2641 if (offset && cfg_ptr) {
2642
2643 outpdw(offset, cfg_ptr->r.c);
2644 outpdw(offset + 0x30, cfg_ptr->g.c);
2645 outpdw(offset + 0x60, cfg_ptr->b.c);
2646 offset += 4;
2647
2648 outpdw(offset, cfg_ptr->r.r);
2649 outpdw(offset + 0x30, cfg_ptr->g.r);
2650 outpdw(offset + 0x60, cfg_ptr->b.r);
2651 offset += 4;
2652
2653 outpdw(offset, cfg_ptr->r.g);
2654 outpdw(offset + 0x30, cfg_ptr->g.g);
2655 outpdw(offset + 0x60, cfg_ptr->b.g);
2656 offset += 4;
2657
2658 outpdw(offset, cfg_ptr->r.b);
2659 outpdw(offset + 0x30, cfg_ptr->g.b);
2660 outpdw(offset + 0x60, cfg_ptr->b.b);
2661 offset += 4;
2662
2663 outpdw(offset, cfg_ptr->r.rr);
2664 outpdw(offset + 0x30, cfg_ptr->g.rr);
2665 outpdw(offset + 0x60, cfg_ptr->b.rr);
2666 offset += 4;
2667
2668 outpdw(offset, cfg_ptr->r.gg);
2669 outpdw(offset + 0x30, cfg_ptr->g.gg);
2670 outpdw(offset + 0x60, cfg_ptr->b.gg);
2671 offset += 4;
2672
2673 outpdw(offset, cfg_ptr->r.bb);
2674 outpdw(offset + 0x30, cfg_ptr->g.bb);
2675 outpdw(offset + 0x60, cfg_ptr->b.bb);
2676 offset += 4;
2677
2678 outpdw(offset, cfg_ptr->r.rg);
2679 outpdw(offset + 0x30, cfg_ptr->g.rg);
2680 outpdw(offset + 0x60, cfg_ptr->b.rg);
2681 offset += 4;
2682
2683 outpdw(offset, cfg_ptr->r.gb);
2684 outpdw(offset + 0x30, cfg_ptr->g.gb);
2685 outpdw(offset + 0x60, cfg_ptr->b.gb);
2686 offset += 4;
2687
2688 outpdw(offset, cfg_ptr->r.rb);
2689 outpdw(offset + 0x30, cfg_ptr->g.rb);
2690 outpdw(offset + 0x60, cfg_ptr->b.rb);
2691 offset += 4;
2692
2693 outpdw(offset, cfg_ptr->r.rgb_0);
2694 outpdw(offset + 0x30, cfg_ptr->g.rgb_0);
2695 outpdw(offset + 0x60, cfg_ptr->b.rgb_0);
2696 offset += 4;
2697
2698 outpdw(offset, cfg_ptr->r.rgb_1);
2699 outpdw(offset + 0x30, cfg_ptr->g.rgb_1);
2700 outpdw(offset + 0x60, cfg_ptr->b.rgb_1);
2701
2702 ret = 0;
2703 }
2704
2705 return ret;
2706}
2707
2708static int mdp4_read_pcc_regs(uint32_t offset,
2709 struct mdp_pcc_cfg_data *cfg_ptr)
2710{
2711 int ret = -1;
2712
2713 if (offset && cfg_ptr) {
2714 cfg_ptr->r.c = inpdw(offset);
2715 cfg_ptr->g.c = inpdw(offset + 0x30);
2716 cfg_ptr->b.c = inpdw(offset + 0x60);
2717 offset += 4;
2718
2719 cfg_ptr->r.r = inpdw(offset);
2720 cfg_ptr->g.r = inpdw(offset + 0x30);
2721 cfg_ptr->b.r = inpdw(offset + 0x60);
2722 offset += 4;
2723
2724 cfg_ptr->r.g = inpdw(offset);
2725 cfg_ptr->g.g = inpdw(offset + 0x30);
2726 cfg_ptr->b.g = inpdw(offset + 0x60);
2727 offset += 4;
2728
2729 cfg_ptr->r.b = inpdw(offset);
2730 cfg_ptr->g.b = inpdw(offset + 0x30);
2731 cfg_ptr->b.b = inpdw(offset + 0x60);
2732 offset += 4;
2733
2734 cfg_ptr->r.rr = inpdw(offset);
2735 cfg_ptr->g.rr = inpdw(offset + 0x30);
2736 cfg_ptr->b.rr = inpdw(offset + 0x60);
2737 offset += 4;
2738
2739 cfg_ptr->r.gg = inpdw(offset);
2740 cfg_ptr->g.gg = inpdw(offset + 0x30);
2741 cfg_ptr->b.gg = inpdw(offset + 0x60);
2742 offset += 4;
2743
2744 cfg_ptr->r.bb = inpdw(offset);
2745 cfg_ptr->g.bb = inpdw(offset + 0x30);
2746 cfg_ptr->b.bb = inpdw(offset + 0x60);
2747 offset += 4;
2748
2749 cfg_ptr->r.rg = inpdw(offset);
2750 cfg_ptr->g.rg = inpdw(offset + 0x30);
2751 cfg_ptr->b.rg = inpdw(offset + 0x60);
2752 offset += 4;
2753
2754 cfg_ptr->r.gb = inpdw(offset);
2755 cfg_ptr->g.gb = inpdw(offset + 0x30);
2756 cfg_ptr->b.gb = inpdw(offset + 0x60);
2757 offset += 4;
2758
2759 cfg_ptr->r.rb = inpdw(offset);
2760 cfg_ptr->g.rb = inpdw(offset + 0x30);
2761 cfg_ptr->b.rb = inpdw(offset + 0x60);
2762 offset += 4;
2763
2764 cfg_ptr->r.rgb_0 = inpdw(offset);
2765 cfg_ptr->g.rgb_0 = inpdw(offset + 0x30);
2766 cfg_ptr->b.rgb_0 = inpdw(offset + 0x60);
2767 offset += 4;
2768
2769 cfg_ptr->r.rgb_1 = inpdw(offset);
2770 cfg_ptr->g.rgb_1 = inpdw(offset + 0x30);
2771 cfg_ptr->b.rgb_1 = inpdw(offset + 0x60);
2772
2773 ret = 0;
2774 }
2775
2776 return ret;
2777}
2778
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2779
2780#define MDP_PCC_OFFSET 0xA000
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2781#define MDP_DMA_GC_OFFSET 0x8800
2782#define MDP_LM_0_GC_OFFSET 0x4800
2783#define MDP_LM_1_GC_OFFSET 0x4880
2784
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2785
2786#define MDP_DMA_P_OP_MODE_OFFSET 0x70
2787#define MDP_DMA_S_OP_MODE_OFFSET 0x28
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2788#define MDP_LM_OP_MODE_OFFSET 0x10
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2789
2790#define DMA_PCC_R2_OFFSET 0x100
2791
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2792#define MDP_GC_COLOR_OFFSET 0x100
2793#define MDP_GC_PARMS_OFFSET 0x80
2794
2795#define MDP_AR_GC_MAX_STAGES 16
2796
2797static uint32_t mdp_pp_block2pcc(uint32_t block)
2798{
2799 uint32_t valid = 0;
2800
2801 switch (block) {
2802 case MDP_BLOCK_DMA_P:
2803 case MDP_BLOCK_DMA_S:
2804 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2805 break;
2806
2807 default:
2808 break;
2809 }
2810
2811 return valid;
2812}
2813
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2814int mdp4_pcc_cfg(struct mdp_pcc_cfg_data *cfg_ptr)
2815{
2816 int ret = -1;
2817 uint32_t pcc_offset = 0, mdp_cfg_offset = 0;
2818 uint32_t mdp_dma_op_mode = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2819 uint32_t blockbase;
2820
2821 if (!mdp_pp_block2pcc(cfg_ptr->block))
2822 return ret;
2823
2824 blockbase = mdp_block2base(cfg_ptr->block);
2825 if (!blockbase)
2826 return ret;
2827
2828 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2829
2830 switch (cfg_ptr->block) {
2831 case MDP_BLOCK_DMA_P:
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2832 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2833 pcc_offset = blockbase + MDP_PCC_OFFSET;
2834 mdp_cfg_offset = blockbase;
2835 mdp_dma_op_mode = blockbase +
2836 (MDP_BLOCK_DMA_P == cfg_ptr->block ?
2837 MDP_DMA_P_OP_MODE_OFFSET
2838 : MDP_DMA_S_OP_MODE_OFFSET);
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2839 break;
2840
2841 default:
2842 break;
2843 }
2844
2845 if (0x8 & cfg_ptr->ops)
2846 pcc_offset += DMA_PCC_R2_OFFSET;
2847
2848 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2849
2850 switch ((0x6 & cfg_ptr->ops)>>1) {
2851 case 0x1:
2852 ret = mdp4_read_pcc_regs(pcc_offset, cfg_ptr);
2853 break;
2854
2855 case 0x2:
2856 ret = mdp4_update_pcc_regs(pcc_offset, cfg_ptr);
2857 break;
2858
2859 default:
2860 break;
2861 }
2862
2863 if (0x8 & cfg_ptr->ops)
2864 outpdw(mdp_dma_op_mode,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2865 ((inpdw(mdp_dma_op_mode) & ~(0x1<<10)) |
2866 ((0x8 & cfg_ptr->ops)<<10)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2867
2868 outpdw(mdp_cfg_offset,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2869 ((inpdw(mdp_cfg_offset) & ~(0x1<<29)) |
2870 ((cfg_ptr->ops & 0x1)<<29)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2871
2872 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2873
2874 return ret;
2875}
2876
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2877static uint32_t mdp_pp_block2argc(uint32_t block)
2878{
2879 uint32_t valid = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2880
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2881 switch (block) {
2882 case MDP_BLOCK_DMA_P:
2883 case MDP_BLOCK_DMA_S:
2884 case MDP_BLOCK_OVERLAY_0:
2885 case MDP_BLOCK_OVERLAY_1:
2886 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2887 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2888
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2889 default:
2890 break;
2891 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2892
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2893 return valid;
2894}
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2895
2896static int update_ar_gc_lut(uint32_t *offset, struct mdp_pgc_lut_data *lut_data)
2897{
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2898 int count = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2899
2900 uint32_t *c0_offset = offset;
2901 uint32_t *c0_params_offset = (uint32_t *)((uint32_t)c0_offset
2902 + MDP_GC_PARMS_OFFSET);
2903
2904 uint32_t *c1_offset = (uint32_t *)((uint32_t)offset
2905 + MDP_GC_COLOR_OFFSET);
2906
2907 uint32_t *c1_params_offset = (uint32_t *)((uint32_t)c1_offset
2908 + MDP_GC_PARMS_OFFSET);
2909
2910 uint32_t *c2_offset = (uint32_t *)((uint32_t)offset
2911 + 2*MDP_GC_COLOR_OFFSET);
2912
2913 uint32_t *c2_params_offset = (uint32_t *)((uint32_t)c2_offset
2914 +MDP_GC_PARMS_OFFSET);
2915
2916
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2917 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2918 for (count = 0; count < MDP_AR_GC_MAX_STAGES; count++) {
2919 if (count < lut_data->num_r_stages) {
2920 outpdw(c0_offset+count,
2921 ((0xfff & lut_data->r_data[count].x_start)
2922 | 0x10000));
2923
2924 outpdw(c0_params_offset+count,
2925 ((0x7fff & lut_data->r_data[count].slope)
2926 | ((0xffff
2927 & lut_data->r_data[count].offset)
2928 << 16)));
2929 } else
2930 outpdw(c0_offset+count, 0);
2931
2932 if (count < lut_data->num_b_stages) {
2933 outpdw(c1_offset+count,
2934 ((0xfff & lut_data->b_data[count].x_start)
2935 | 0x10000));
2936
2937 outpdw(c1_params_offset+count,
2938 ((0x7fff & lut_data->b_data[count].slope)
2939 | ((0xffff
2940 & lut_data->b_data[count].offset)
2941 << 16)));
2942 } else
2943 outpdw(c1_offset+count, 0);
2944
2945 if (count < lut_data->num_g_stages) {
2946 outpdw(c2_offset+count,
2947 ((0xfff & lut_data->g_data[count].x_start)
2948 | 0x10000));
2949
2950 outpdw(c2_params_offset+count,
2951 ((0x7fff & lut_data->g_data[count].slope)
2952 | ((0xffff
2953 & lut_data->g_data[count].offset)
2954 << 16)));
2955 } else
2956 outpdw(c2_offset+count, 0);
2957 }
2958
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2959 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2960
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2961 return 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2962}
2963
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2964static int mdp4_argc_process_write_req(uint32_t *offset,
2965 struct mdp_pgc_lut_data *pgc_ptr)
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2966{
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2967 int ret = -1;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2968 struct mdp_ar_gc_lut_data r[MDP_AR_GC_MAX_STAGES];
2969 struct mdp_ar_gc_lut_data g[MDP_AR_GC_MAX_STAGES];
2970 struct mdp_ar_gc_lut_data b[MDP_AR_GC_MAX_STAGES];
2971
2972 ret = copy_from_user(&r[0], pgc_ptr->r_data,
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2973 pgc_ptr->num_r_stages * sizeof(struct mdp_ar_gc_lut_data));
2974
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2975 if (!ret) {
2976 ret = copy_from_user(&g[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2977 pgc_ptr->g_data,
2978 pgc_ptr->num_g_stages
2979 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2980 if (!ret)
2981 ret = copy_from_user(&b[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2982 pgc_ptr->b_data,
2983 pgc_ptr->num_b_stages
2984 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2985 }
2986
2987 if (ret)
2988 return ret;
2989
2990 pgc_ptr->r_data = &r[0];
2991 pgc_ptr->g_data = &g[0];
2992 pgc_ptr->b_data = &b[0];
2993
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2994 ret = update_ar_gc_lut(offset, pgc_ptr);
2995 return ret;
2996}
2997
2998int mdp4_argc_cfg(struct mdp_pgc_lut_data *pgc_ptr)
2999{
3000 int ret = -1;
3001 uint32_t *offset = 0, *pgc_enable_offset = 0, lshift_bits = 0;
3002 uint32_t blockbase;
3003
3004 if (!mdp_pp_block2argc(pgc_ptr->block))
3005 return ret;
3006
3007 blockbase = mdp_block2base(pgc_ptr->block);
3008 if (!blockbase)
3009 return ret;
3010
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3011 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3012 ret = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3013
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3014 switch (pgc_ptr->block) {
3015 case MDP_BLOCK_DMA_P:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3016 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3017 offset = (uint32_t *)(blockbase + MDP_DMA_GC_OFFSET);
3018 pgc_enable_offset = (uint32_t *) blockbase;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3019 lshift_bits = 28;
3020 break;
3021
3022 case MDP_BLOCK_OVERLAY_0:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3023 case MDP_BLOCK_OVERLAY_1:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3024 offset = (uint32_t *)(blockbase +
3025 (MDP_BLOCK_OVERLAY_0 == pgc_ptr->block ?
3026 MDP_LM_0_GC_OFFSET
3027 : MDP_LM_1_GC_OFFSET));
3028
3029 pgc_enable_offset = (uint32_t *)(blockbase
3030 + MDP_LM_OP_MODE_OFFSET);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3031 lshift_bits = 2;
3032 break;
3033
3034 default:
3035 ret = -1;
3036 break;
3037 }
3038
3039 if (!ret) {
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3040
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3041 switch ((0x6 & pgc_ptr->flags)>>1) {
3042 case 0x1:
3043 ret = -ENOTTY;
3044 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3045
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3046 case 0x2:
3047 ret = mdp4_argc_process_write_req(offset, pgc_ptr);
3048 break;
3049
3050 default:
3051 break;
3052 }
3053
3054 if (!ret) {
3055 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]3056 outpdw(pgc_enable_offset, (inpdw(pgc_enable_offset) &
3057 ~(0x1<<lshift_bits)) |
3058 ((0x1 & pgc_ptr->flags) << lshift_bits));
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3059 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF,
3060 FALSE);
3061 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3062 }
3063
3064 return ret;
3065}
3066
Carl Vanderlipacde4b62011-12-16 15:50:56 -0800[diff] [blame]3067static uint32_t mdp4_pp_block2igc(uint32_t block)
3068{
3069 uint32_t valid = 0;
3070 switch (block) {
3071 case MDP_BLOCK_VG_1:
3072 valid = 0x1;
3073 break;
3074 case MDP_BLOCK_VG_2:
3075 valid = 0x1;
3076 break;
3077 case MDP_BLOCK_RGB_1:
3078 valid = 0x1;
3079 break;
3080 case MDP_BLOCK_RGB_2:
3081 valid = 0x1;
3082 break;
3083 case MDP_BLOCK_DMA_P:
3084 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3085 break;
3086 case MDP_BLOCK_DMA_S:
3087 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3088 break;
3089 default:
3090 break;
3091 }
3092 return valid;
3093}
3094
3095static int mdp4_igc_lut_write(struct mdp_igc_lut_data *cfg, uint32_t en_off,
3096 uint32_t lut_off)
3097{
3098 int i;
3099 uint32_t base, *off_low, *off_high;
3100 uint32_t low[cfg->len];
3101 uint32_t high[cfg->len];
3102
3103 base = mdp_block2base(cfg->block);
3104
3105 if (cfg->len != 256)
3106 return -EINVAL;
3107
3108 off_low = (uint32_t *)(MDP_BASE + base + lut_off);
3109 off_high = (uint32_t *)(MDP_BASE + base + lut_off + 0x800);
3110 if (copy_from_user(&low, cfg->c0_c1_data, cfg->len * sizeof(uint32_t)))
3111 return -EFAULT;
3112 if (copy_from_user(&high, cfg->c2_data, cfg->len * sizeof(uint32_t)))
3113 return -EFAULT;
3114
3115 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3116 for (i = 0; i < cfg->len; i++) {
3117 MDP_OUTP(off_low++, low[i]);
3118 /*low address write should occur before high address write*/
3119 wmb();
3120 MDP_OUTP(off_high++, high[i]);
3121 }
3122 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3123 return 0;
3124}
3125
3126static int mdp4_igc_lut_ctrl(struct mdp_igc_lut_data *cfg)
3127{
3128 uint32_t mask, out;
3129 uint32_t base = mdp_block2base(cfg->block);
3130 int8_t shift = 0;
3131
3132 switch (cfg->block) {
3133 case MDP_BLOCK_DMA_P:
3134 case MDP_BLOCK_DMA_S:
3135 base = base;
3136 shift = 30;
3137 break;
3138 case MDP_BLOCK_VG_1:
3139 case MDP_BLOCK_VG_2:
3140 case MDP_BLOCK_RGB_1:
3141 case MDP_BLOCK_RGB_2:
3142 base += 0x58;
3143 shift = 16;
3144 break;
3145 default:
3146 return -EINVAL;
3147
3148 }
3149 out = 1<<shift;
3150 mask = ~out;
3151 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3152 out = inpdw(MDP_BASE + base) & mask;
3153 MDP_OUTP(MDP_BASE + base, out | ((cfg->ops & 0x1)<<shift));
3154 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3155
3156 return 0;
3157}
3158
3159static int mdp4_igc_lut_write_cfg(struct mdp_igc_lut_data *cfg)
3160{
3161 int ret = 0;
3162
3163 switch (cfg->block) {
3164 case MDP_BLOCK_DMA_P:
3165 case MDP_BLOCK_DMA_S:
3166 ret = mdp4_igc_lut_write(cfg, 0x00, 0x9000);
3167 break;
3168 case MDP_BLOCK_VG_1:
3169 case MDP_BLOCK_VG_2:
3170 case MDP_BLOCK_RGB_1:
3171 case MDP_BLOCK_RGB_2:
3172 ret = mdp4_igc_lut_write(cfg, 0x58, 0x5000);
3173 break;
3174 default:
3175 ret = -EINVAL;
3176 }
3177
3178 return ret;
3179}
3180
3181int mdp4_igc_lut_config(struct mdp_igc_lut_data *cfg)
3182{
3183 int ret = 0;
3184
3185 if (!mdp4_pp_block2igc(cfg->block)) {
3186 ret = -ENOTTY;
3187 goto error;
3188 }
3189
3190 switch ((cfg->ops & 0x6) >> 1) {
3191 case 0x1:
3192 pr_info("%s: IGC LUT read not supported\n", __func__);
3193 break;
3194 case 0x2:
3195 ret = mdp4_igc_lut_write_cfg(cfg);
3196 if (ret)
3197 goto error;
3198 break;
3199 default:
3200 break;
3201 }
3202
3203 ret = mdp4_igc_lut_ctrl(cfg);
3204
3205error:
3206 return ret;
3207}
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame^]3208
3209#define QSEED_TABLE_1_COUNT 2
3210#define QSEED_TABLE_2_COUNT 1024
3211
3212static uint32_t mdp4_pp_block2qseed(uint32_t block)
3213{
3214 uint32_t valid = 0;
3215 switch (block) {
3216 case MDP_BLOCK_VG_1:
3217 case MDP_BLOCK_VG_2:
3218 valid = 0x1;
3219 break;
3220 default:
3221 break;
3222 }
3223 return valid;
3224}
3225
3226static int mdp4_qseed_write_cfg(struct mdp_qseed_cfg_data *cfg)
3227{
3228 int i, ret = 0;
3229 uint32_t base = (uint32_t) (MDP_BASE + mdp_block2base(cfg->block));
3230 uint32_t *values;
3231
3232 if ((cfg->table_num != 1) && (cfg->table_num != 2)) {
3233 ret = -ENOTTY;
3234 goto error;
3235 }
3236
3237 if (((cfg->table_num == 1) && (cfg->len != QSEED_TABLE_1_COUNT)) ||
3238 ((cfg->table_num == 2) && (cfg->len != QSEED_TABLE_2_COUNT))) {
3239 ret = -EINVAL;
3240 goto error;
3241 }
3242
3243 values = kmalloc(cfg->len * sizeof(uint32_t), GFP_KERNEL);
3244 if (!values) {
3245 ret = -ENOMEM;
3246 goto error;
3247 }
3248
3249 ret = copy_from_user(values, cfg->data, sizeof(uint32_t) * cfg->len);
3250
3251 base += (cfg->table_num == 1) ? MDP4_QSEED_TABLE1_OFF :
3252 MDP4_QSEED_TABLE2_OFF;
3253 for (i = 0; i < cfg->len; i++) {
3254 MDP_OUTP(base , values[i]);
3255 base += sizeof(uint32_t);
3256 }
3257
3258 kfree(values);
3259error:
3260 return ret;
3261}
3262
3263int mdp4_qseed_cfg(struct mdp_qseed_cfg_data *cfg)
3264{
3265 int ret = 0;
3266
3267 if (!mdp4_pp_block2qseed(cfg->block)) {
3268 ret = -ENOTTY;
3269 goto error;
3270 }
3271
3272 if (cfg->table_num != 1) {
3273 ret = -ENOTTY;
3274 pr_info("%s: Only QSEED table1 supported.\n", __func__);
3275 goto error;
3276 }
3277
3278 switch ((cfg->ops & 0x6) >> 1) {
3279 case 0x1:
3280 pr_info("%s: QSEED read not supported\n", __func__);
3281 ret = -ENOTTY;
3282 break;
3283 case 0x2:
3284 ret = mdp4_qseed_write_cfg(cfg);
3285 if (ret)
3286 goto error;
3287 break;
3288 default:
3289 break;
3290 }
3291
3292error:
3293 return ret;
3294}