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Praveen Chidambaram78499012011-11-01 17:15:17 -06001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Arun Menonaabf2632012-02-24 15:30:47 -080016#include <linux/ion.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060017#include <mach/msm_iomap.h>
18#include <mach/irqs-8930.h>
19#include <mach/rpm.h>
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -070020#include <mach/msm_dcvs.h>
Arun Menonaabf2632012-02-24 15:30:47 -080021#include <mach/msm_bus.h>
Gagan Maccd5b3272012-02-09 18:13:10 -070022#include <mach/msm_bus_board.h>
Arun Menonaabf2632012-02-24 15:30:47 -080023#include <mach/board.h>
24#include <mach/socinfo.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060025
26#include "devices.h"
27#include "rpm_log.h"
28#include "rpm_stats.h"
29
30#ifdef CONFIG_MSM_MPM
Subhash Jadavani909e04f2012-04-12 10:52:50 +053031#include <mach/mpm.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060032#endif
33
34struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
35 .reg_base_addrs = {
36 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
37 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
38 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
39 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
40 },
41 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -080042 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambarame396ce62012-03-30 11:15:57 -060043 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -060044 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
45 .ipc_rpm_val = 4,
46 .target_id = {
47 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
48 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
49 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -070050 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
51 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -060052 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
53 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
54 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
55 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
56 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
57 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
58 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
59 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
60 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
61 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
62 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
63 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
64 APPS_FABRIC_CFG_HALT, 2),
65 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
66 APPS_FABRIC_CFG_CLKMOD, 3),
67 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
68 APPS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060069 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
Praveen Chidambaram78499012011-11-01 17:15:17 -060070 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
71 SYS_FABRIC_CFG_HALT, 2),
72 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
73 SYS_FABRIC_CFG_CLKMOD, 3),
74 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
75 SYS_FABRIC_CFG_IOCTL, 1),
76 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060077 SYSTEM_FABRIC_ARB, 20),
Praveen Chidambaram78499012011-11-01 17:15:17 -060078 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
79 MMSS_FABRIC_CFG_HALT, 2),
80 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
81 MMSS_FABRIC_CFG_CLKMOD, 3),
82 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
83 MMSS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060084 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
Praveen Chidambaram78499012011-11-01 17:15:17 -060085 MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
86 MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
87 MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
88 MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
89 MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
90 MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
91 MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
92 MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
93 MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
94 MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
95 MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
96 MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
97 MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
98 MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
99 MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
100 MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
101 MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
102 MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
103 MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
104 MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
105 MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
106 MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
107 MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
108 MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
109 MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
110 MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
111 MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
112 MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
113 MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
114 MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
115 MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
116 MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
117 MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
118 MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
119 MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
120 MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
121 MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
122 MSM_RPM_MAP(8930, NCP_0, NCP, 2),
123 MSM_RPM_MAP(8930, CXO_BUFFERS, CXO_BUFFERS, 1),
124 MSM_RPM_MAP(8930, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
125 MSM_RPM_MAP(8930, HDMI_SWITCH, HDMI_SWITCH, 1),
126 MSM_RPM_MAP(8930, QDSS_CLK, QDSS_CLK, 1),
Mahesh Sivasubramanian9e52ce42012-02-01 16:00:19 -0700127 MSM_RPM_MAP(8930, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600128 },
129 .target_status = {
130 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
131 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
132 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
133 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
134 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
135 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
136 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
137 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
138 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
139 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
140 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
141 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
142 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
143 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
144 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
145 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
146 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
147 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
148 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
149 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
150 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
151 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
152 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
153 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
154 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
155 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
156 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
157 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
158 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
159 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
160 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
161 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
162 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
163 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
164 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
165 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
166 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
167 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
168 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
169 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
170 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
171 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
172 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
173 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
174 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
175 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
176 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
177 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
178 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
179 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
180 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
181 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
182 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
183 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
184 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
185 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
186 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
187 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
188 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
189 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
190 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
191 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
192 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
193 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
194 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
195 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
196 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
197 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
198 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
199 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
200 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
201 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
202 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
203 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
204 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
205 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
206 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
207 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
208 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
209 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
210 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
211 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
212 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
213 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
214 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
215 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
216 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
217 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
218 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
219 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
220 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
221 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
222 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
223 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
224 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
225 MSM_RPM_STATUS_ID_MAP(8930, NCP_0),
226 MSM_RPM_STATUS_ID_MAP(8930, NCP_1),
227 MSM_RPM_STATUS_ID_MAP(8930, CXO_BUFFERS),
228 MSM_RPM_STATUS_ID_MAP(8930, USB_OTG_SWITCH),
229 MSM_RPM_STATUS_ID_MAP(8930, HDMI_SWITCH),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -0700230 MSM_RPM_STATUS_ID_MAP(8930, QDSS_CLK),
Mahesh Sivasubramanian9e52ce42012-02-01 16:00:19 -0700231 MSM_RPM_STATUS_ID_MAP(8930, VOLTAGE_CORNER),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600232 },
233 .target_ctrl_id = {
234 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
235 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
236 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
237 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
238 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
239 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
240 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
241 },
242 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
243 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
244 .sel_last = MSM_RPM_8930_SEL_LAST,
245 .ver = {3, 0, 0},
246};
247
248struct platform_device msm8930_rpm_device = {
249 .name = "msm_rpm",
250 .id = -1,
251};
252
253static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
254 .phys_addr_base = 0x0010C000,
255 .reg_offsets = {
256 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
257 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
258 },
259 .phys_size = SZ_8K,
260 .log_len = 4096, /* log's buffer length in bytes */
261 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
262};
263
264struct platform_device msm8930_rpm_log_device = {
265 .name = "msm_rpm_log",
266 .id = -1,
267 .dev = {
268 .platform_data = &msm_rpm_log_pdata,
269 },
270};
271
272static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
273 .phys_addr_base = 0x0010D204,
274 .phys_size = SZ_8K,
275};
276
277struct platform_device msm8930_rpm_stat_device = {
278 .name = "msm_rpm_stat",
279 .id = -1,
280 .dev = {
281 .platform_data = &msm_rpm_stat_pdata,
282 },
283};
284
Praveen Chidambaram8ea3dcd2011-12-07 14:46:31 -0700285static int msm8930_LPM_latency = 1000; /* >100 usec for WFI */
286
287struct platform_device msm8930_cpu_idle_device = {
288 .name = "msm_cpu_idle",
289 .id = -1,
290 .dev = {
291 .platform_data = &msm8930_LPM_latency,
292 },
293};
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -0700294
295static struct msm_dcvs_freq_entry msm8930_freq[] = {
296 { 384000, 166981, 345600},
297 { 702000, 213049, 632502},
298 {1026000, 285712, 925613},
299 {1242000, 383945, 1176550},
300 {1458000, 419729, 1465478},
301 {1512000, 434116, 1546674},
302
303};
304
305static struct msm_dcvs_core_info msm8930_core_info = {
306 .freq_tbl = &msm8930_freq[0],
307 .core_param = {
308 .max_time_us = 100000,
309 .num_freq = ARRAY_SIZE(msm8930_freq),
310 },
311 .algo_param = {
312 .slack_time_us = 58000,
313 .scale_slack_time = 0,
314 .scale_slack_time_pct = 0,
315 .disable_pc_threshold = 1458000,
316 .em_window_size = 100000,
317 .em_max_util_pct = 97,
318 .ss_window_size = 1000000,
319 .ss_util_pct = 95,
320 .ss_iobusy_conv = 100,
321 },
322};
323
324struct platform_device msm8930_msm_gov_device = {
325 .name = "msm_dcvs_gov",
326 .id = -1,
327 .dev = {
328 .platform_data = &msm8930_core_info,
329 },
330};
Gagan Maccd5b3272012-02-09 18:13:10 -0700331
332struct platform_device msm_bus_8930_sys_fabric = {
333 .name = "msm_bus_fabric",
334 .id = MSM_BUS_FAB_SYSTEM,
335};
336struct platform_device msm_bus_8930_apps_fabric = {
337 .name = "msm_bus_fabric",
338 .id = MSM_BUS_FAB_APPSS,
339};
340struct platform_device msm_bus_8930_mm_fabric = {
341 .name = "msm_bus_fabric",
342 .id = MSM_BUS_FAB_MMSS,
343};
344struct platform_device msm_bus_8930_sys_fpb = {
345 .name = "msm_bus_fabric",
346 .id = MSM_BUS_FAB_SYSTEM_FPB,
347};
348struct platform_device msm_bus_8930_cpss_fpb = {
349 .name = "msm_bus_fabric",
350 .id = MSM_BUS_FAB_CPSS_FPB,
351};
352
Arun Menonaabf2632012-02-24 15:30:47 -0800353/* MSM Video core device */
354#ifdef CONFIG_MSM_BUS_SCALING
355static struct msm_bus_vectors vidc_init_vectors[] = {
356 {
357 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
358 .dst = MSM_BUS_SLAVE_EBI_CH0,
359 .ab = 0,
360 .ib = 0,
361 },
362 {
363 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
364 .dst = MSM_BUS_SLAVE_EBI_CH0,
365 .ab = 0,
366 .ib = 0,
367 },
368 {
369 .src = MSM_BUS_MASTER_AMPSS_M0,
370 .dst = MSM_BUS_SLAVE_EBI_CH0,
371 .ab = 0,
372 .ib = 0,
373 },
374 {
375 .src = MSM_BUS_MASTER_AMPSS_M0,
376 .dst = MSM_BUS_SLAVE_EBI_CH0,
377 .ab = 0,
378 .ib = 0,
379 },
380};
381static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
382 {
383 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
384 .dst = MSM_BUS_SLAVE_EBI_CH0,
385 .ab = 54525952,
386 .ib = 436207616,
387 },
388 {
389 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
390 .dst = MSM_BUS_SLAVE_EBI_CH0,
391 .ab = 72351744,
392 .ib = 289406976,
393 },
394 {
395 .src = MSM_BUS_MASTER_AMPSS_M0,
396 .dst = MSM_BUS_SLAVE_EBI_CH0,
397 .ab = 500000,
398 .ib = 1000000,
399 },
400 {
401 .src = MSM_BUS_MASTER_AMPSS_M0,
402 .dst = MSM_BUS_SLAVE_EBI_CH0,
403 .ab = 500000,
404 .ib = 1000000,
405 },
406};
407static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
408 {
409 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
410 .dst = MSM_BUS_SLAVE_EBI_CH0,
411 .ab = 40894464,
412 .ib = 327155712,
413 },
414 {
415 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
416 .dst = MSM_BUS_SLAVE_EBI_CH0,
417 .ab = 48234496,
418 .ib = 192937984,
419 },
420 {
421 .src = MSM_BUS_MASTER_AMPSS_M0,
422 .dst = MSM_BUS_SLAVE_EBI_CH0,
423 .ab = 500000,
424 .ib = 2000000,
425 },
426 {
427 .src = MSM_BUS_MASTER_AMPSS_M0,
428 .dst = MSM_BUS_SLAVE_EBI_CH0,
429 .ab = 500000,
430 .ib = 2000000,
431 },
432};
433static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
434 {
435 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
436 .dst = MSM_BUS_SLAVE_EBI_CH0,
437 .ab = 163577856,
438 .ib = 1308622848,
439 },
440 {
441 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
442 .dst = MSM_BUS_SLAVE_EBI_CH0,
443 .ab = 219152384,
444 .ib = 876609536,
445 },
446 {
447 .src = MSM_BUS_MASTER_AMPSS_M0,
448 .dst = MSM_BUS_SLAVE_EBI_CH0,
449 .ab = 1750000,
450 .ib = 3500000,
451 },
452 {
453 .src = MSM_BUS_MASTER_AMPSS_M0,
454 .dst = MSM_BUS_SLAVE_EBI_CH0,
455 .ab = 1750000,
456 .ib = 3500000,
457 },
458};
459static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
460 {
461 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
462 .dst = MSM_BUS_SLAVE_EBI_CH0,
463 .ab = 121634816,
464 .ib = 973078528,
465 },
466 {
467 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
468 .dst = MSM_BUS_SLAVE_EBI_CH0,
469 .ab = 155189248,
470 .ib = 620756992,
471 },
472 {
473 .src = MSM_BUS_MASTER_AMPSS_M0,
474 .dst = MSM_BUS_SLAVE_EBI_CH0,
475 .ab = 1750000,
476 .ib = 7000000,
477 },
478 {
479 .src = MSM_BUS_MASTER_AMPSS_M0,
480 .dst = MSM_BUS_SLAVE_EBI_CH0,
481 .ab = 1750000,
482 .ib = 7000000,
483 },
484};
485static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
486 {
487 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
488 .dst = MSM_BUS_SLAVE_EBI_CH0,
489 .ab = 372244480,
490 .ib = 2560000000U,
491 },
492 {
493 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
494 .dst = MSM_BUS_SLAVE_EBI_CH0,
495 .ab = 501219328,
496 .ib = 2560000000U,
497 },
498 {
499 .src = MSM_BUS_MASTER_AMPSS_M0,
500 .dst = MSM_BUS_SLAVE_EBI_CH0,
501 .ab = 2500000,
502 .ib = 5000000,
503 },
504 {
505 .src = MSM_BUS_MASTER_AMPSS_M0,
506 .dst = MSM_BUS_SLAVE_EBI_CH0,
507 .ab = 2500000,
508 .ib = 5000000,
509 },
510};
511static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
512 {
513 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
514 .dst = MSM_BUS_SLAVE_EBI_CH0,
515 .ab = 222298112,
516 .ib = 2560000000U,
517 },
518 {
519 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
520 .dst = MSM_BUS_SLAVE_EBI_CH0,
521 .ab = 330301440,
522 .ib = 2560000000U,
523 },
524 {
525 .src = MSM_BUS_MASTER_AMPSS_M0,
526 .dst = MSM_BUS_SLAVE_EBI_CH0,
527 .ab = 2500000,
528 .ib = 700000000,
529 },
530 {
531 .src = MSM_BUS_MASTER_AMPSS_M0,
532 .dst = MSM_BUS_SLAVE_EBI_CH0,
533 .ab = 2500000,
534 .ib = 10000000,
535 },
536};
537
538static struct msm_bus_paths vidc_bus_client_config[] = {
539 {
540 ARRAY_SIZE(vidc_init_vectors),
541 vidc_init_vectors,
542 },
543 {
544 ARRAY_SIZE(vidc_venc_vga_vectors),
545 vidc_venc_vga_vectors,
546 },
547 {
548 ARRAY_SIZE(vidc_vdec_vga_vectors),
549 vidc_vdec_vga_vectors,
550 },
551 {
552 ARRAY_SIZE(vidc_venc_720p_vectors),
553 vidc_venc_720p_vectors,
554 },
555 {
556 ARRAY_SIZE(vidc_vdec_720p_vectors),
557 vidc_vdec_720p_vectors,
558 },
559 {
560 ARRAY_SIZE(vidc_venc_1080p_vectors),
561 vidc_venc_1080p_vectors,
562 },
563 {
564 ARRAY_SIZE(vidc_vdec_1080p_vectors),
565 vidc_vdec_1080p_vectors,
566 },
567};
568
569static struct msm_bus_scale_pdata vidc_bus_client_data = {
570 vidc_bus_client_config,
571 ARRAY_SIZE(vidc_bus_client_config),
572 .name = "vidc",
573};
574#endif
575
576#define MSM_VIDC_BASE_PHYS 0x04400000
577#define MSM_VIDC_BASE_SIZE 0x00100000
578
579static struct resource apq8930_device_vidc_resources[] = {
580 {
581 .start = MSM_VIDC_BASE_PHYS,
582 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
583 .flags = IORESOURCE_MEM,
584 },
585 {
586 .start = VCODEC_IRQ,
587 .end = VCODEC_IRQ,
588 .flags = IORESOURCE_IRQ,
589 },
590};
591
592struct msm_vidc_platform_data apq8930_vidc_platform_data = {
593#ifdef CONFIG_MSM_BUS_SCALING
594 .vidc_bus_client_pdata = &vidc_bus_client_data,
595#endif
596#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
597 .memtype = ION_CP_MM_HEAP_ID,
598 .enable_ion = 1,
599#else
600 .memtype = MEMTYPE_EBI1,
601 .enable_ion = 0,
602#endif
603 .disable_dmx = 0,
604 .disable_fullhd = 0,
605};
606
607struct platform_device apq8930_msm_device_vidc = {
608 .name = "msm_vidc",
609 .id = 0,
610 .num_resources = ARRAY_SIZE(apq8930_device_vidc_resources),
611 .resource = apq8930_device_vidc_resources,
612 .dev = {
613 .platform_data = &apq8930_vidc_platform_data,
614 },
615};
616
617struct platform_device *vidc_device[] __initdata = {
618 &apq8930_msm_device_vidc
619};
620
621void __init msm8930_add_vidc_device(void)
622{
623 if (cpu_is_msm8627()) {
624 struct msm_vidc_platform_data *pdata;
625 pdata = (struct msm_vidc_platform_data *)
626 apq8930_msm_device_vidc.dev.platform_data;
627 pdata->disable_fullhd = 1;
628 }
629 platform_add_devices(vidc_device, ARRAY_SIZE(vidc_device));
630}