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review.evervolv.com / android_kernel_htc_msm8960 / e46ef6f1bc4d6d406e90e8e4dbcbeef0e2257cae / . / include / media / tavarua.h
blob: a6c00bd3461395312f5abdb0d482f4540a965b8a [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1#ifndef __LINUX_TAVARUA_H
2#define __LINUX_TAVARUA_H
3
4#ifdef __KERNEL__
5#include <linux/types.h>
6#include <asm/sizes.h>
7#else
8#include <stdint.h>
9#endif
10#include <linux/ioctl.h>
11#include <linux/videodev2.h>
12
13
14#undef FM_DEBUG
15
16/* constants */
17#define RDS_BLOCKS_NUM (4)
18#define BYTES_PER_BLOCK (3)
19#define MAX_PS_LENGTH (96)
20#define MAX_RT_LENGTH (64)
21
22#define XFRDAT0 (0x20)
23#define XFRDAT1 (0x21)
24#define XFRDAT2 (0x22)
25
26#define INTDET_PEEK_MSB (0x88)
27#define INTDET_PEEK_LSB (0x26)
28
29#define RMSSI_PEEK_MSB (0x88)
30#define RMSSI_PEEK_LSB (0xA8)
31
32#define MPX_DCC_BYPASS_POKE_MSB (0x88)
33#define MPX_DCC_BYPASS_POKE_LSB (0xC0)
34
35#define MPX_DCC_PEEK_MSB_REG1 (0x88)
36#define MPX_DCC_PEEK_LSB_REG1 (0xC2)
37
38#define MPX_DCC_PEEK_MSB_REG2 (0x88)
39#define MPX_DCC_PEEK_LSB_REG2 (0xC3)
40
41#define MPX_DCC_PEEK_MSB_REG3 (0x88)
42#define MPX_DCC_PEEK_LSB_REG3 (0xC4)
43
44/* Standard buffer size */
45#define STD_BUF_SIZE (64)
46/* Search direction */
47#define SRCH_DIR_UP (0)
48#define SRCH_DIR_DOWN (1)
49
50/* control options */
51#define CTRL_ON (1)
52#define CTRL_OFF (0)
53
54#define US_LOW_BAND (87.5)
55#define US_HIGH_BAND (108)
56
57/* constant for Tx */
58
59#define MASK_PI (0x0000FFFF)
60#define MASK_PI_MSB (0x0000FF00)
61#define MASK_PI_LSB (0x000000FF)
62#define MASK_PTY (0x0000001F)
63#define MASK_TXREPCOUNT (0x0000000F)
64
65#undef FMDBG
66#ifdef FM_DEBUG
67 #define FMDBG(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
68#else
69 #define FMDBG(fmt, args...)
70#endif
71
72#undef FMDERR
73#define FMDERR(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
74
75#undef FMDBG_I2C
76#ifdef FM_DEBUG_I2C
77 #define FMDBG_I2C(fmt, args...) printk(KERN_INFO "fm_i2c: " fmt, ##args)
78#else
79 #define FMDBG_I2C(fmt, args...)
80#endif
81
82/* function declarations */
83/* FM Core audio paths. */
84#define TAVARUA_AUDIO_OUT_ANALOG_OFF (0)
85#define TAVARUA_AUDIO_OUT_ANALOG_ON (1)
86#define TAVARUA_AUDIO_OUT_DIGITAL_OFF (0)
87#define TAVARUA_AUDIO_OUT_DIGITAL_ON (1)
88
89int tavarua_set_audio_path(int digital_on, int analog_on);
90
91/* defines and enums*/
92
93#define MARIMBA_A0 0x01010013
94#define MARIMBA_2_1 0x02010204
95#define BAHAMA_1_0 0x0302010A
96#define BAHAMA_2_0 0x04020205
97#define WAIT_TIMEOUT 2000
98#define RADIO_INIT_TIME 15
99#define TAVARUA_DELAY 10
100/*
101 * The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
102 * 62.5 kHz otherwise.
103 * The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
104 * tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
105 * The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
106 */
107#define FREQ_MUL (1000000 / 62.5)
108
109enum v4l2_cid_private_tavarua_t {
110 V4L2_CID_PRIVATE_TAVARUA_SRCHMODE = (V4L2_CID_PRIVATE_BASE + 1),
111 V4L2_CID_PRIVATE_TAVARUA_SCANDWELL,
112 V4L2_CID_PRIVATE_TAVARUA_SRCHON,
113 V4L2_CID_PRIVATE_TAVARUA_STATE,
114 V4L2_CID_PRIVATE_TAVARUA_TRANSMIT_MODE,
115 V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,
116 V4L2_CID_PRIVATE_TAVARUA_REGION,
117 V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,
118 V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY,
119 V4L2_CID_PRIVATE_TAVARUA_SRCH_PI,
120 V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT,
121 V4L2_CID_PRIVATE_TAVARUA_EMPHASIS,
122 V4L2_CID_PRIVATE_TAVARUA_RDS_STD,
123 V4L2_CID_PRIVATE_TAVARUA_SPACING,
124 V4L2_CID_PRIVATE_TAVARUA_RDSON,
125 V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC,
126 V4L2_CID_PRIVATE_TAVARUA_LP_MODE,
127 V4L2_CID_PRIVATE_TAVARUA_ANTENNA,
128 V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,
129 V4L2_CID_PRIVATE_TAVARUA_PSALL,
130 /*v4l2 Tx controls*/
131 V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT,
132 V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME,
133 V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT,
134 V4L2_CID_PRIVATE_TAVARUA_IOVERC,
135 V4L2_CID_PRIVATE_TAVARUA_INTDET,
136 V4L2_CID_PRIVATE_TAVARUA_MPX_DCC,
Anantha Krishnane46ef6f2011-06-29 23:56:03 +0530[diff] [blame^]137 V4L2_CID_PRIVATE_TAVARUA_AF_JUMP,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]138};
139
140enum tavarua_buf_t {
141 TAVARUA_BUF_SRCH_LIST,
142 TAVARUA_BUF_EVENTS,
143 TAVARUA_BUF_RT_RDS,
144 TAVARUA_BUF_PS_RDS,
145 TAVARUA_BUF_RAW_RDS,
146 TAVARUA_BUF_AF_LIST,
147 TAVARUA_BUF_MAX
148};
149
150enum tavarua_xfr_t {
151 TAVARUA_XFR_SYNC,
152 TAVARUA_XFR_ERROR,
153 TAVARUA_XFR_SRCH_LIST,
154 TAVARUA_XFR_RT_RDS,
155 TAVARUA_XFR_PS_RDS,
156 TAVARUA_XFR_AF_LIST,
157 TAVARUA_XFR_MAX
158};
159
160/* offsets */
161#define RAW_RDS 0x0F
162#define RDS_BLOCK 3
163
164/* registers*/
165#define MARIMBA_XO_BUFF_CNTRL 0x07
166#define RADIO_REGISTERS 0x30
167#define XFR_REG_NUM 16
168#define STATUS_REG_NUM 3
169
170/* TX constants */
171#define HEADER_SIZE 4
172#define TX_ON 0x80
173#define TAVARUA_TX_RT RDS_RT_0
174#define TAVARUA_TX_PS RDS_PS_0
175
176enum register_t {
177 STATUS_REG1 = 0,
178 STATUS_REG2,
179 STATUS_REG3,
180 RDCTRL,
181 FREQ,
182 TUNECTRL,
183 SRCHRDS1,
184 SRCHRDS2,
185 SRCHCTRL,
186 IOCTRL,
187 RDSCTRL,
188 ADVCTRL,
189 AUDIOCTRL,
190 RMSSI,
191 IOVERC,
192 AUDIOIND = 0x1E,
193 XFRCTRL,
194 FM_CTL0 = 0xFF,
195 LEAKAGE_CNTRL = 0xFE,
196};
197#define BAHAMA_RBIAS_CTL1 0x07
198#define BAHAMA_FM_MODE_REG 0xFD
199#define BAHAMA_FM_CTL1_REG 0xFE
200#define BAHAMA_FM_CTL0_REG 0xFF
201#define BAHAMA_FM_MODE_NORMAL 0x00
202#define BAHAMA_LDO_DREG_CTL0 0xF0
203#define BAHAMA_LDO_AREG_CTL0 0xF4
204
205/* Radio Control */
206#define RDCTRL_STATE_OFFSET 0
207#define RDCTRL_STATE_MASK (3 << RDCTRL_STATE_OFFSET)
208#define RDCTRL_BAND_OFFSET 2
209#define RDCTRL_BAND_MASK (1 << RDCTRL_BAND_OFFSET)
210#define RDCTRL_CHSPACE_OFFSET 3
211#define RDCTRL_CHSPACE_MASK (3 << RDCTRL_CHSPACE_OFFSET)
212#define RDCTRL_DEEMPHASIS_OFFSET 5
213#define RDCTRL_DEEMPHASIS_MASK (1 << RDCTRL_DEEMPHASIS_OFFSET)
214#define RDCTRL_HLSI_OFFSET 6
215#define RDCTRL_HLSI_MASK (3 << RDCTRL_HLSI_OFFSET)
Anantha Krishnane46ef6f2011-06-29 23:56:03 +0530[diff] [blame^]216#define RDSAF_OFFSET 6
217#define RDSAF_MASK (1 << RDSAF_OFFSET)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]218
219/* Tune Control */
220#define TUNE_STATION 0x01
221#define ADD_OFFSET (1 << 1)
222#define SIGSTATE (1 << 5)
223#define MOSTSTATE (1 << 6)
224#define RDSSYNC (1 << 7)
225/* Search Control */
226#define SRCH_MODE_OFFSET 0
227#define SRCH_MODE_MASK (7 << SRCH_MODE_OFFSET)
228#define SRCH_DIR_OFFSET 3
229#define SRCH_DIR_MASK (1 << SRCH_DIR_OFFSET)
230#define SRCH_DWELL_OFFSET 4
231#define SRCH_DWELL_MASK (7 << SRCH_DWELL_OFFSET)
232#define SRCH_STATE_OFFSET 7
233#define SRCH_STATE_MASK (1 << SRCH_STATE_OFFSET)
234
235/* I/O Control */
236#define IOC_HRD_MUTE 0x03
237#define IOC_SFT_MUTE (1 << 2)
238#define IOC_MON_STR (1 << 3)
239#define IOC_SIG_BLND (1 << 4)
240#define IOC_INTF_BLND (1 << 5)
241#define IOC_ANTENNA (1 << 6)
242#define IOC_ANTENNA_OFFSET 6
243#define IOC_ANTENNA_MASK (1 << IOC_ANTENNA_OFFSET)
244
245/* RDS Control */
246#define RDS_ON 0x01
247#define RDSCTRL_STANDARD_OFFSET 1
248#define RDSCTRL_STANDARD_MASK (1 << RDSCTRL_STANDARD_OFFSET)
249
250/* Advanced features controls */
251#define RDSRTEN (1 << 3)
252#define RDSPSEN (1 << 4)
253
254/* Audio path control */
255#define AUDIORX_ANALOG_OFFSET 0
256#define AUDIORX_ANALOG_MASK (1 << AUDIORX_ANALOG_OFFSET)
257#define AUDIORX_DIGITAL_OFFSET 1
258#define AUDIORX_DIGITAL_MASK (1 << AUDIORX_DIGITAL_OFFSET)
259#define AUDIOTX_OFFSET 2
260#define AUDIOTX_MASK (1 << AUDIOTX_OFFSET)
261#define I2SCTRL_OFFSET 3
262#define I2SCTRL_MASK (1 << I2SCTRL_OFFSET)
263
264/* Search options */
265enum search_t {
266 SEEK,
267 SCAN,
268 SCAN_FOR_STRONG,
269 SCAN_FOR_WEAK,
270 RDS_SEEK_PTY,
271 RDS_SCAN_PTY,
272 RDS_SEEK_PI,
273 RDS_AF_JUMP,
274};
275
276#define SRCH_MODE 0x07
277#define SRCH_DIR 0x08 /* 0-up 1-down */
278#define SCAN_DWELL 0x70
279#define SRCH_ON 0x80
280
281/* RDS CONFIG */
282#define RDS_CONFIG_PSALL 0x01
283
284#define FM_ENABLE 0x22
285#define SET_REG_FIELD(reg, val, offset, mask) \
286 (reg = (reg & ~mask) | (((val) << offset) & mask))
287#define GET_REG_FIELD(reg, offset, mask) ((reg & mask) >> offset)
288
289enum radio_state_t {
290 FM_OFF,
291 FM_RECV,
292 FM_TRANS,
293 FM_RESET,
294};
295
296#define XFRCTRL_WRITE (1 << 7)
297
298/* Interrupt status */
299
300/* interrupt register 1 */
301#define READY (1 << 0) /* Radio ready after powerup or reset */
302#define TUNE (1 << 1) /* Tune completed */
303#define SEARCH (1 << 2) /* Search completed (read FREQ) */
304#define SCANNEXT (1 << 3) /* Scanning for next station */
305#define SIGNAL (1 << 4) /* Signal indicator change (read SIGSTATE) */
306#define INTF (1 << 5) /* Interference cnt has fallen outside range */
307#define SYNC (1 << 6) /* RDS sync state change (read RDSSYNC) */
308#define AUDIO (1 << 7) /* Audio Control indicator (read AUDIOIND) */
309
310/* interrupt register 2 */
311#define RDSDAT (1 << 0) /* New unread RDS data group available */
312#define BLOCKB (1 << 1) /* Block-B match condition exists */
313#define PROGID (1 << 2) /* Block-A or Block-C matched stored PI value*/
314#define RDSPS (1 << 3) /* New RDS Program Service Table available */
315#define RDSRT (1 << 4) /* New RDS Radio Text available */
316#define RDSAF (1 << 5) /* New RDS AF List available */
317#define TXRDSDAT (1 << 6) /* Transmitted an RDS group */
318#define TXRDSDONE (1 << 7) /* RDS raw group one-shot transmit completed */
319
320/* interrupt register 3 */
321#define TRANSFER (1 << 0) /* Data transfer (XFR) completed */
322#define RDSPROC (1 << 1) /* Dynamic RDS Processing complete */
323#define ERROR (1 << 7) /* Err occurred.Read code to determine cause */
324
325
326#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */
327#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */
328/* Transfer */
329enum tavarua_xfr_ctrl_t {
330 RDS_PS_0 = 0x01,
331 RDS_PS_1,
332 RDS_PS_2,
333 RDS_PS_3,
334 RDS_PS_4,
335 RDS_PS_5,
336 RDS_PS_6,
337 RDS_RT_0,
338 RDS_RT_1,
339 RDS_RT_2,
340 RDS_RT_3,
341 RDS_RT_4,
342 RDS_AF_0,
343 RDS_AF_1,
344 RDS_CONFIG,
345 RDS_TX_GROUPS,
346 RDS_COUNT_0,
347 RDS_COUNT_1,
348 RDS_COUNT_2,
349 RADIO_CONFIG,
350 RX_CONFIG,
351 RX_TIMERS,
352 RX_STATIONS_0,
353 RX_STATIONS_1,
354 INT_CTRL,
355 ERROR_CODE,
356 CHIPID,
357 CAL_DAT_0 = 0x20,
358 CAL_DAT_1,
359 CAL_DAT_2,
360 CAL_DAT_3,
361 CAL_CFG_0,
362 CAL_CFG_1,
363 DIG_INTF_0,
364 DIG_INTF_1,
365 DIG_AGC_0,
366 DIG_AGC_1,
367 DIG_AGC_2,
368 DIG_AUDIO_0,
369 DIG_AUDIO_1,
370 DIG_AUDIO_2,
371 DIG_AUDIO_3,
372 DIG_AUDIO_4,
373 DIG_RXRDS,
374 DIG_DCC,
375 DIG_SPUR,
376 DIG_MPXDCC,
377 DIG_PILOT,
378 DIG_DEMOD,
379 DIG_MOST,
380 DIG_TX_0,
381 DIG_TX_1,
382 PHY_TXGAIN = 0x3B,
383 PHY_CONFIG,
384 PHY_TXBLOCK,
385 PHY_TCB,
386 XFR_PEEK_MODE = 0x40,
387 XFR_POKE_MODE = 0xC0,
388 TAVARUA_XFR_CTRL_MAX
389};
390
391enum tavarua_evt_t {
392 TAVARUA_EVT_RADIO_READY,
393 TAVARUA_EVT_TUNE_SUCC,
394 TAVARUA_EVT_SEEK_COMPLETE,
395 TAVARUA_EVT_SCAN_NEXT,
396 TAVARUA_EVT_NEW_RAW_RDS,
397 TAVARUA_EVT_NEW_RT_RDS,
398 TAVARUA_EVT_NEW_PS_RDS,
399 TAVARUA_EVT_ERROR,
400 TAVARUA_EVT_BELOW_TH,
401 TAVARUA_EVT_ABOVE_TH,
402 TAVARUA_EVT_STEREO,
403 TAVARUA_EVT_MONO,
404 TAVARUA_EVT_RDS_AVAIL,
405 TAVARUA_EVT_RDS_NOT_AVAIL,
406 TAVARUA_EVT_NEW_SRCH_LIST,
407 TAVARUA_EVT_NEW_AF_LIST,
408 TAVARUA_EVT_TXRDSDAT,
409 TAVARUA_EVT_TXRDSDONE
410};
411
412enum tavarua_region_t {
413 TAVARUA_REGION_US,
414 TAVARUA_REGION_EU,
415 TAVARUA_REGION_JAPAN,
416 TAVARUA_REGION_JAPAN_WIDE,
417 TAVARUA_REGION_OTHER
418};
419
420#endif /* __LINUX_TAVARUA_H */