blob: 88cd37da13effa22c996b34613a37ee5acd3c841 [file] [log] [blame]
Zang Roy-r619114b3afca2006-08-25 16:43:25 +08001/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13
14/ {
15 model = "mpc7448hpc2";
16 compatible = "mpc74xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080019
20 cpus {
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080021 #address-cells = <1>;
22 #size-cells =<0>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080023
24 PowerPC,7448@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <20>; // 32 bytes
28 i-cache-line-size = <20>; // 32 bytes
29 d-cache-size = <8000>; // L1, 32K bytes
30 i-cache-size = <8000>; // L1, 32K bytes
31 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080034 };
35 };
36
37 memory {
38 device_type = "memory";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080039 reg = <00000000 20000000 // DDR2 512M at 0
40 >;
41 };
42
43 tsi108@c0000000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
Roy Zang006af9e2007-07-11 14:39:17 +080046 device_type = "tsi-bridge";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080047 ranges = <00000000 c0000000 00010000>;
48 reg = <c0000000 00010000>;
49 bus-frequency = <0>;
50
51 i2c@7000 {
Kumar Gala5c1992f2007-05-15 16:12:27 -050052 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080053 interrupts = <E 0>;
54 reg = <7000 400>;
55 device_type = "i2c";
David Gibsone58ca3d2007-06-13 14:53:00 +100056 compatible = "tsi108-i2c";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080057 };
58
David Gibsone58ca3d2007-06-13 14:53:00 +100059 MDIO: mdio@6000 {
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080060 device_type = "mdio";
David Gibsone58ca3d2007-06-13 14:53:00 +100061 compatible = "tsi108-mdio";
62 reg = <6000 50>;
63 #address-cells = <1>;
64 #size-cells = <0>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080065
David Gibsone58ca3d2007-06-13 14:53:00 +100066 phy8: ethernet-phy@8 {
Kumar Gala5c1992f2007-05-15 16:12:27 -050067 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080068 interrupts = <2 1>;
David Gibsone58ca3d2007-06-13 14:53:00 +100069 reg = <8>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080070 };
71
David Gibsone58ca3d2007-06-13 14:53:00 +100072 phy9: ethernet-phy@9 {
Kumar Gala5c1992f2007-05-15 16:12:27 -050073 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080074 interrupts = <2 1>;
David Gibsone58ca3d2007-06-13 14:53:00 +100075 reg = <9>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080076 };
77
78 };
79
80 ethernet@6200 {
81 #size-cells = <0>;
82 device_type = "network";
David Gibsone58ca3d2007-06-13 14:53:00 +100083 compatible = "tsi108-ethernet";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080084 reg = <6000 200>;
85 address = [ 00 06 D2 00 00 01 ];
86 interrupts = <10 2>;
Kumar Gala5c1992f2007-05-15 16:12:27 -050087 interrupt-parent = <&mpic>;
David Gibsone58ca3d2007-06-13 14:53:00 +100088 mdio-handle = <&MDIO>;
Kumar Gala5c1992f2007-05-15 16:12:27 -050089 phy-handle = <&phy8>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080090 };
91
92 ethernet@6600 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 device_type = "network";
David Gibsone58ca3d2007-06-13 14:53:00 +100096 compatible = "tsi108-ethernet";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +080097 reg = <6400 200>;
98 address = [ 00 06 D2 00 00 02 ];
99 interrupts = <11 2>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500100 interrupt-parent = <&mpic>;
David Gibsone58ca3d2007-06-13 14:53:00 +1000101 mdio-handle = <&MDIO>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500102 phy-handle = <&phy9>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800103 };
104
105 serial@7808 {
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <7808 200>;
109 clock-frequency = <3f6b5a00>;
110 interrupts = <c 0>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500111 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800112 };
113
114 serial@7c08 {
115 device_type = "serial";
116 compatible = "ns16550";
117 reg = <7c08 200>;
118 clock-frequency = <3f6b5a00>;
119 interrupts = <d 0>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500120 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800121 };
122
Kumar Gala5c1992f2007-05-15 16:12:27 -0500123 mpic: pic@7400 {
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800124 clock-frequency = <0>;
125 interrupt-controller;
126 #address-cells = <0>;
127 #interrupt-cells = <2>;
128 reg = <7400 400>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800129 compatible = "chrp,open-pic";
130 device_type = "open-pic";
131 big-endian;
132 };
133 pci@1000 {
David Gibsone58ca3d2007-06-13 14:53:00 +1000134 compatible = "tsi108-pci";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800135 device_type = "pci";
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800136 #interrupt-cells = <1>;
137 #size-cells = <2>;
138 #address-cells = <3>;
139 reg = <1000 1000>;
140 bus-range = <0 0>;
141 ranges = <02000000 0 e0000000 e0000000 0 1A000000
142 01000000 0 00000000 fa000000 0 00010000>;
143 clock-frequency = <7f28154>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500144 interrupt-parent = <&mpic>;
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800145 interrupts = <17 2>;
146 interrupt-map-mask = <f800 0 0 7>;
147 interrupt-map = <
148
149 /* IDSEL 0x11 */
Kumar Gala5c1992f2007-05-15 16:12:27 -0500150 0800 0 0 1 &RT0 24 0
151 0800 0 0 2 &RT0 25 0
152 0800 0 0 3 &RT0 26 0
153 0800 0 0 4 &RT0 27 0
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800154
155 /* IDSEL 0x12 */
Kumar Gala5c1992f2007-05-15 16:12:27 -0500156 1000 0 0 1 &RT0 25 0
157 1000 0 0 2 &RT0 26 0
158 1000 0 0 3 &RT0 27 0
159 1000 0 0 4 &RT0 24 0
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800160
161 /* IDSEL 0x13 */
Kumar Gala5c1992f2007-05-15 16:12:27 -0500162 1800 0 0 1 &RT0 26 0
163 1800 0 0 2 &RT0 27 0
164 1800 0 0 3 &RT0 24 0
165 1800 0 0 4 &RT0 25 0
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800166
167 /* IDSEL 0x14 */
Kumar Gala5c1992f2007-05-15 16:12:27 -0500168 2000 0 0 1 &RT0 27 0
169 2000 0 0 2 &RT0 24 0
170 2000 0 0 3 &RT0 25 0
171 2000 0 0 4 &RT0 26 0
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800172 >;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500173
174 RT0: router@1180 {
Zang Roy-r619115873c9b2006-11-14 14:31:50 +0800175 clock-frequency = <0>;
176 interrupt-controller;
177 device_type = "pic-router";
178 #address-cells = <0>;
179 #interrupt-cells = <2>;
Zang Roy-r619115873c9b2006-11-14 14:31:50 +0800180 big-endian;
181 interrupts = <17 2>;
Kumar Gala5c1992f2007-05-15 16:12:27 -0500182 interrupt-parent = <&mpic>;
Zang Roy-r619115873c9b2006-11-14 14:31:50 +0800183 };
Zang Roy-r619114b3afca2006-08-25 16:43:25 +0800184 };
185 };
186
187};