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review.evervolv.com / android_kernel_htc_msm8960 / e5cabeb3d60f9cd3e3950aff071319ae0e2d08d8 / . / drivers / rapidio / switches / tsi57x.c
blob: 23040b92ea76c2412f44ee5d3455d7bf8ccdf707 [file] [log] [blame]
Alexandre Bounine07590ff2010-05-26 14:43:57 -0700[diff] [blame]1/*
2 * RapidIO Tsi57x switch family support
3 *
4 * Copyright 2009 Integrated Device Technology, Inc.
5 * Copyright 2005 MontaVista Software, Inc.
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/rio.h>
15#include <linux/rio_drv.h>
16#include <linux/rio_ids.h>
17#include <linux/delay.h>
18#include "../rio.h"
19
20/* Global (broadcast) route registers */
21#define SPBC_ROUTE_CFG_DESTID 0x10070
22#define SPBC_ROUTE_CFG_PORT 0x10074
23
24/* Per port route registers */
25#define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
26#define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
27
Alexandre Bouninee5cabeb2010-05-26 14:43:59 -0700[diff] [blame^]28#define TSI578_SP_MODE(n) (0x11004 + n*0x100)
29#define TSI578_SP_MODE_PW_DIS 0x08000000
30
31#define TSI578_SP_CTL_INDEP(n) (0x13004 + n*0x100)
32#define TSI578_SP_LUT_PEINF(n) (0x13010 + n*0x100)
33#define TSI578_SP_CS_TX(n) (0x13014 + n*0x100)
34#define TSI578_SP_INT_STATUS(n) (0x13018 + n*0x100)
35
Alexandre Bounine07590ff2010-05-26 14:43:57 -0700[diff] [blame]36static int
37tsi57x_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
38 u16 table, u16 route_destid, u8 route_port)
39{
40 if (table == RIO_GLOBAL_TABLE) {
41 rio_mport_write_config_32(mport, destid, hopcount,
42 SPBC_ROUTE_CFG_DESTID, route_destid);
43 rio_mport_write_config_32(mport, destid, hopcount,
44 SPBC_ROUTE_CFG_PORT, route_port);
45 } else {
46 rio_mport_write_config_32(mport, destid, hopcount,
47 SPP_ROUTE_CFG_DESTID(table), route_destid);
48 rio_mport_write_config_32(mport, destid, hopcount,
49 SPP_ROUTE_CFG_PORT(table), route_port);
50 }
51
52 udelay(10);
53
54 return 0;
55}
56
57static int
58tsi57x_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
59 u16 table, u16 route_destid, u8 *route_port)
60{
61 int ret = 0;
62 u32 result;
63
64 if (table == RIO_GLOBAL_TABLE) {
65 /* Use local RT of the ingress port to avoid possible
66 race condition */
67 rio_mport_read_config_32(mport, destid, hopcount,
68 RIO_SWP_INFO_CAR, &result);
69 table = (result & RIO_SWP_INFO_PORT_NUM_MASK);
70 }
71
72 rio_mport_write_config_32(mport, destid, hopcount,
73 SPP_ROUTE_CFG_DESTID(table), route_destid);
74 rio_mport_read_config_32(mport, destid, hopcount,
75 SPP_ROUTE_CFG_PORT(table), &result);
76
77 *route_port = (u8)result;
78 if (*route_port > 15)
79 ret = -1;
80
81 return ret;
82}
83
84static int
85tsi57x_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
86 u16 table)
87{
88 u32 route_idx;
89 u32 lut_size;
90
91 lut_size = (mport->sys_size) ? 0x1ff : 0xff;
92
93 if (table == RIO_GLOBAL_TABLE) {
94 rio_mport_write_config_32(mport, destid, hopcount,
95 SPBC_ROUTE_CFG_DESTID, 0x80000000);
96 for (route_idx = 0; route_idx <= lut_size; route_idx++)
97 rio_mport_write_config_32(mport, destid, hopcount,
98 SPBC_ROUTE_CFG_PORT,
99 RIO_INVALID_ROUTE);
100 } else {
101 rio_mport_write_config_32(mport, destid, hopcount,
102 SPP_ROUTE_CFG_DESTID(table), 0x80000000);
103 for (route_idx = 0; route_idx <= lut_size; route_idx++)
104 rio_mport_write_config_32(mport, destid, hopcount,
105 SPP_ROUTE_CFG_PORT(table) , RIO_INVALID_ROUTE);
106 }
107
108 return 0;
109}
110
111DECLARE_RIO_ROUTE_OPS(RIO_VID_TUNDRA, RIO_DID_TSI572, tsi57x_route_add_entry, tsi57x_route_get_entry, tsi57x_route_clr_table);
112DECLARE_RIO_ROUTE_OPS(RIO_VID_TUNDRA, RIO_DID_TSI574, tsi57x_route_add_entry, tsi57x_route_get_entry, tsi57x_route_clr_table);
113DECLARE_RIO_ROUTE_OPS(RIO_VID_TUNDRA, RIO_DID_TSI577, tsi57x_route_add_entry, tsi57x_route_get_entry, tsi57x_route_clr_table);
114DECLARE_RIO_ROUTE_OPS(RIO_VID_TUNDRA, RIO_DID_TSI578, tsi57x_route_add_entry, tsi57x_route_get_entry, tsi57x_route_clr_table);
Alexandre Bouninee5cabeb2010-05-26 14:43:59 -0700[diff] [blame^]115
116static int
117tsi57x_em_init(struct rio_dev *rdev)
118{
119 struct rio_mport *mport = rdev->net->hport;
120 u16 destid = rdev->rswitch->destid;
121 u8 hopcount = rdev->rswitch->hopcount;
122 u32 regval;
123 int portnum;
124
125 pr_debug("TSI578 %s [%d:%d]\n", __func__, destid, hopcount);
126
127 for (portnum = 0; portnum < 16; portnum++) {
128 /* Make sure that Port-Writes are enabled (for all ports) */
129 rio_mport_read_config_32(mport, destid, hopcount,
130 TSI578_SP_MODE(portnum), &regval);
131 rio_mport_write_config_32(mport, destid, hopcount,
132 TSI578_SP_MODE(portnum),
133 regval & ~TSI578_SP_MODE_PW_DIS);
134
135 /* Clear all pending interrupts */
136 rio_mport_read_config_32(mport, destid, hopcount,
137 rdev->phys_efptr +
138 RIO_PORT_N_ERR_STS_CSR(portnum),
139 &regval);
140 rio_mport_write_config_32(mport, destid, hopcount,
141 rdev->phys_efptr +
142 RIO_PORT_N_ERR_STS_CSR(portnum),
143 regval & 0x07120214);
144
145 rio_mport_read_config_32(mport, destid, hopcount,
146 TSI578_SP_INT_STATUS(portnum), &regval);
147 rio_mport_write_config_32(mport, destid, hopcount,
148 TSI578_SP_INT_STATUS(portnum),
149 regval & 0x000700bd);
150
151 /* Enable all interrupts to allow ports to send a port-write */
152 rio_mport_read_config_32(mport, destid, hopcount,
153 TSI578_SP_CTL_INDEP(portnum), &regval);
154 rio_mport_write_config_32(mport, destid, hopcount,
155 TSI578_SP_CTL_INDEP(portnum),
156 regval | 0x000b0000);
157
158 /* Skip next (odd) port if the current port is in x4 mode */
159 rio_mport_read_config_32(mport, destid, hopcount,
160 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
161 &regval);
162 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
163 portnum++;
164 }
165
166 return 0;
167}
168
169static int
170tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
171{
172 struct rio_mport *mport = rdev->net->hport;
173 u16 destid = rdev->rswitch->destid;
174 u8 hopcount = rdev->rswitch->hopcount;
175 u32 intstat, err_status;
176 int sendcount, checkcount;
177 u8 route_port;
178 u32 regval;
179
180 rio_mport_read_config_32(mport, destid, hopcount,
181 rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
182 &err_status);
183
184 if ((err_status & RIO_PORT_N_ERR_STS_PORT_OK) &&
185 (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
186 RIO_PORT_N_ERR_STS_PW_INP_ES))) {
187 /* Remove any queued packets by locking/unlocking port */
188 rio_mport_read_config_32(mport, destid, hopcount,
189 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
190 &regval);
191 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
192 rio_mport_write_config_32(mport, destid, hopcount,
193 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
194 regval | RIO_PORT_N_CTL_LOCKOUT);
195 udelay(50);
196 rio_mport_write_config_32(mport, destid, hopcount,
197 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
198 regval);
199 }
200
201 /* Read from link maintenance response register to clear
202 * valid bit
203 */
204 rio_mport_read_config_32(mport, destid, hopcount,
205 rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
206 &regval);
207
208 /* Send a Packet-Not-Accepted/Link-Request-Input-Status control
209 * symbol to recover from IES/OES
210 */
211 sendcount = 3;
212 while (sendcount) {
213 rio_mport_write_config_32(mport, destid, hopcount,
214 TSI578_SP_CS_TX(portnum), 0x40fc8000);
215 checkcount = 3;
216 while (checkcount--) {
217 udelay(50);
218 rio_mport_read_config_32(
219 mport, destid, hopcount,
220 rdev->phys_efptr +
221 RIO_PORT_N_MNT_RSP_CSR(portnum),
222 &regval);
223 if (regval & RIO_PORT_N_MNT_RSP_RVAL)
224 goto exit_es;
225 }
226
227 sendcount--;
228 }
229 }
230
231exit_es:
232 /* Clear implementation specific error status bits */
233 rio_mport_read_config_32(mport, destid, hopcount,
234 TSI578_SP_INT_STATUS(portnum), &intstat);
235 pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
236 destid, hopcount, portnum, intstat);
237
238 if (intstat & 0x10000) {
239 rio_mport_read_config_32(mport, destid, hopcount,
240 TSI578_SP_LUT_PEINF(portnum), &regval);
241 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
242 route_port = rdev->rswitch->route_table[regval];
243 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
244 rio_name(rdev), portnum, regval);
245 tsi57x_route_add_entry(mport, destid, hopcount,
246 RIO_GLOBAL_TABLE, regval, route_port);
247 }
248
249 rio_mport_write_config_32(mport, destid, hopcount,
250 TSI578_SP_INT_STATUS(portnum),
251 intstat & 0x000700bd);
252
253 return 0;
254}
255
256DECLARE_RIO_EM_OPS(RIO_VID_TUNDRA, RIO_DID_TSI572, tsi57x_em_init, tsi57x_em_handler);
257DECLARE_RIO_EM_OPS(RIO_VID_TUNDRA, RIO_DID_TSI574, tsi57x_em_init, tsi57x_em_handler);
258DECLARE_RIO_EM_OPS(RIO_VID_TUNDRA, RIO_DID_TSI577, tsi57x_em_init, tsi57x_em_handler);
259DECLARE_RIO_EM_OPS(RIO_VID_TUNDRA, RIO_DID_TSI578, tsi57x_em_init, tsi57x_em_handler);