| Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1 | /* | 
|  | 2 | * Copyright 2010 Advanced Micro Devices, Inc. | 
|  | 3 | * | 
|  | 4 | * Permission is hereby granted, free of charge, to any person obtaining a | 
|  | 5 | * copy of this software and associated documentation files (the "Software"), | 
|  | 6 | * to deal in the Software without restriction, including without limitation | 
|  | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | 
|  | 8 | * and/or sell copies of the Software, and to permit persons to whom the | 
|  | 9 | * Software is furnished to do so, subject to the following conditions: | 
|  | 10 | * | 
|  | 11 | * The above copyright notice and this permission notice shall be included in | 
|  | 12 | * all copies or substantial portions of the Software. | 
|  | 13 | * | 
|  | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 
|  | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 
|  | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL | 
|  | 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | 
|  | 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | 
|  | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | 
|  | 20 | * OTHER DEALINGS IN THE SOFTWARE. | 
|  | 21 | * | 
|  | 22 | * Authors: Alex Deucher | 
|  | 23 | */ | 
|  | 24 | #ifndef NI_H | 
|  | 25 | #define NI_H | 
|  | 26 |  | 
|  | 27 | #define MC_SHARED_BLACKOUT_CNTL           		0x20ac | 
|  | 28 | #define MC_SEQ_SUP_CNTL           			0x28c8 | 
|  | 29 | #define		RUN_MASK      				(1 << 0) | 
|  | 30 | #define MC_SEQ_SUP_PGM           			0x28cc | 
|  | 31 | #define MC_IO_PAD_CNTL_D0           			0x29d0 | 
|  | 32 | #define		MEM_FALL_OUT_CMD      			(1 << 8) | 
|  | 33 | #define MC_SEQ_MISC0           				0x2a00 | 
|  | 34 | #define		MC_SEQ_MISC0_GDDR5_SHIFT      		28 | 
|  | 35 | #define		MC_SEQ_MISC0_GDDR5_MASK      		0xf0000000 | 
|  | 36 | #define		MC_SEQ_MISC0_GDDR5_VALUE      		5 | 
|  | 37 | #define MC_SEQ_IO_DEBUG_INDEX           		0x2a44 | 
|  | 38 | #define MC_SEQ_IO_DEBUG_DATA           			0x2a48 | 
|  | 39 |  | 
|  | 40 | #endif | 
|  | 41 |  |