blob: 0913d11e09ee63933508d8a9bc5c447a5903a181 [file] [log] [blame]
Dan Williamsbf40a682009-09-08 17:42:55 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
24 *
25 * BSD LICENSE
26 *
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
31 *
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
37 * distribution.
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55/*
56 * Support routines for v3+ hardware
57 */
58
59#include <linux/pci.h>
60#include <linux/dmaengine.h>
61#include <linux/dma-mapping.h>
62#include "registers.h"
63#include "hw.h"
64#include "dma.h"
65#include "dma_v2.h"
66
67static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
68 struct ioat_ring_ent *desc)
69{
70 struct ioat_chan_common *chan = &ioat->base;
71 struct pci_dev *pdev = chan->device->pdev;
72 size_t len = desc->len;
73 size_t offset = len - desc->hw->size;
74 struct dma_async_tx_descriptor *tx = &desc->txd;
75 enum dma_ctrl_flags flags = tx->flags;
76
77 switch (desc->hw->ctl_f.op) {
78 case IOAT_OP_COPY:
79 ioat_dma_unmap(chan, flags, len, desc->hw);
80 break;
81 case IOAT_OP_FILL: {
82 struct ioat_fill_descriptor *hw = desc->fill;
83
84 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
85 ioat_unmap(pdev, hw->dst_addr - offset, len,
86 PCI_DMA_FROMDEVICE, flags, 1);
87 break;
88 }
89 default:
90 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
91 __func__, desc->hw->ctl_f.op);
92 }
93}
94
95
96static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
97{
98 struct ioat_chan_common *chan = &ioat->base;
99 struct ioat_ring_ent *desc;
100 bool seen_current = false;
101 u16 active;
102 int i;
103
104 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
105 __func__, ioat->head, ioat->tail, ioat->issued);
106
107 active = ioat2_ring_active(ioat);
108 for (i = 0; i < active && !seen_current; i++) {
109 struct dma_async_tx_descriptor *tx;
110
111 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
112 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
113 dump_desc_dbg(ioat, desc);
114 tx = &desc->txd;
115 if (tx->cookie) {
116 chan->completed_cookie = tx->cookie;
117 ioat3_dma_unmap(ioat, desc);
118 tx->cookie = 0;
119 if (tx->callback) {
120 tx->callback(tx->callback_param);
121 tx->callback = NULL;
122 }
123 }
124
125 if (tx->phys == phys_complete)
126 seen_current = true;
127 }
128 ioat->tail += i;
129 BUG_ON(!seen_current); /* no active descs have written a completion? */
130 chan->last_completion = phys_complete;
131 if (ioat->head == ioat->tail) {
132 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
133 __func__);
134 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
135 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
136 }
137}
138
139static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
140{
141 struct ioat_chan_common *chan = &ioat->base;
142 unsigned long phys_complete;
143
144 prefetch(chan->completion);
145
146 if (!spin_trylock_bh(&chan->cleanup_lock))
147 return;
148
149 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
150 spin_unlock_bh(&chan->cleanup_lock);
151 return;
152 }
153
154 if (!spin_trylock_bh(&ioat->ring_lock)) {
155 spin_unlock_bh(&chan->cleanup_lock);
156 return;
157 }
158
159 __cleanup(ioat, phys_complete);
160
161 spin_unlock_bh(&ioat->ring_lock);
162 spin_unlock_bh(&chan->cleanup_lock);
163}
164
165static void ioat3_cleanup_tasklet(unsigned long data)
166{
167 struct ioat2_dma_chan *ioat = (void *) data;
168
169 ioat3_cleanup(ioat);
Dan Williamse61daca2009-09-08 17:42:57 -0700170 writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN,
171 ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williamsbf40a682009-09-08 17:42:55 -0700172}
173
174static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
175{
176 struct ioat_chan_common *chan = &ioat->base;
177 unsigned long phys_complete;
178 u32 status;
179
180 status = ioat_chansts(chan);
181 if (is_ioat_active(status) || is_ioat_idle(status))
182 ioat_suspend(chan);
183 while (is_ioat_active(status) || is_ioat_idle(status)) {
184 status = ioat_chansts(chan);
185 cpu_relax();
186 }
187
188 if (ioat_cleanup_preamble(chan, &phys_complete))
189 __cleanup(ioat, phys_complete);
190
191 __ioat2_restart_chan(ioat);
192}
193
194static void ioat3_timer_event(unsigned long data)
195{
196 struct ioat2_dma_chan *ioat = (void *) data;
197 struct ioat_chan_common *chan = &ioat->base;
198
199 spin_lock_bh(&chan->cleanup_lock);
200 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
201 unsigned long phys_complete;
202 u64 status;
203
204 spin_lock_bh(&ioat->ring_lock);
205 status = ioat_chansts(chan);
206
207 /* when halted due to errors check for channel
208 * programming errors before advancing the completion state
209 */
210 if (is_ioat_halted(status)) {
211 u32 chanerr;
212
213 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
214 BUG_ON(is_ioat_bug(chanerr));
215 }
216
217 /* if we haven't made progress and we have already
218 * acknowledged a pending completion once, then be more
219 * forceful with a restart
220 */
221 if (ioat_cleanup_preamble(chan, &phys_complete))
222 __cleanup(ioat, phys_complete);
223 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
224 ioat3_restart_channel(ioat);
225 else {
226 set_bit(IOAT_COMPLETION_ACK, &chan->state);
227 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
228 }
229 spin_unlock_bh(&ioat->ring_lock);
230 } else {
231 u16 active;
232
233 /* if the ring is idle, empty, and oversized try to step
234 * down the size
235 */
236 spin_lock_bh(&ioat->ring_lock);
237 active = ioat2_ring_active(ioat);
238 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
239 reshape_ring(ioat, ioat->alloc_order-1);
240 spin_unlock_bh(&ioat->ring_lock);
241
242 /* keep shrinking until we get back to our minimum
243 * default size
244 */
245 if (ioat->alloc_order > ioat_get_alloc_order())
246 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
247 }
248 spin_unlock_bh(&chan->cleanup_lock);
249}
250
251static enum dma_status
252ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie,
253 dma_cookie_t *done, dma_cookie_t *used)
254{
255 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
256
257 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
258 return DMA_SUCCESS;
259
260 ioat3_cleanup(ioat);
261
262 return ioat_is_complete(c, cookie, done, used);
263}
264
265static struct dma_async_tx_descriptor *
266ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
267 size_t len, unsigned long flags)
268{
269 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
270 struct ioat_ring_ent *desc;
271 size_t total_len = len;
272 struct ioat_fill_descriptor *fill;
273 int num_descs;
274 u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
275 u16 idx;
276 int i;
277
278 num_descs = ioat2_xferlen_to_descs(ioat, len);
279 if (likely(num_descs) &&
280 ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
281 /* pass */;
282 else
283 return NULL;
284 for (i = 0; i < num_descs; i++) {
285 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
286
287 desc = ioat2_get_ring_ent(ioat, idx + i);
288 fill = desc->fill;
289
290 fill->size = xfer_size;
291 fill->src_data = src_data;
292 fill->dst_addr = dest;
293 fill->ctl = 0;
294 fill->ctl_f.op = IOAT_OP_FILL;
295
296 len -= xfer_size;
297 dest += xfer_size;
298 dump_desc_dbg(ioat, desc);
299 }
300
301 desc->txd.flags = flags;
302 desc->len = total_len;
303 fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
304 fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
305 fill->ctl_f.compl_write = 1;
306 dump_desc_dbg(ioat, desc);
307
308 /* we leave the channel locked to ensure in order submission */
309 return &desc->txd;
310}
311
312int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
313{
314 struct pci_dev *pdev = device->pdev;
315 struct dma_device *dma;
316 struct dma_chan *c;
317 struct ioat_chan_common *chan;
318 int err;
319 u16 dev_id;
320 u32 cap;
321
322 device->enumerate_channels = ioat2_enumerate_channels;
323 device->cleanup_tasklet = ioat3_cleanup_tasklet;
324 device->timer_fn = ioat3_timer_event;
325 dma = &device->common;
326 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
327 dma->device_issue_pending = ioat2_issue_pending;
328 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
329 dma->device_free_chan_resources = ioat2_free_chan_resources;
330 dma->device_is_tx_complete = ioat3_is_complete;
331 cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
332 if (cap & IOAT_CAP_FILL_BLOCK) {
333 dma_cap_set(DMA_MEMSET, dma->cap_mask);
334 dma->device_prep_dma_memset = ioat3_prep_memset_lock;
335 }
336
337 /* -= IOAT ver.3 workarounds =- */
338 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
339 * that can cause stability issues for IOAT ver.3
340 */
341 pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
342
343 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
344 * (workaround for spurious config parity error after restart)
345 */
346 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
347 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
348 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
349
350 err = ioat_probe(device);
351 if (err)
352 return err;
353 ioat_set_tcp_copy_break(262144);
354
355 list_for_each_entry(c, &dma->channels, device_node) {
356 chan = to_chan_common(c);
357 writel(IOAT_DMA_DCA_ANY_CPU,
358 chan->reg_base + IOAT_DCACTRL_OFFSET);
359 }
360
361 err = ioat_register(device);
362 if (err)
363 return err;
Dan Williams5669e312009-09-08 17:42:56 -0700364
365 ioat_kobject_add(device, &ioat2_ktype);
366
Dan Williamsbf40a682009-09-08 17:42:55 -0700367 if (dca)
368 device->dca = ioat3_dca_init(pdev, device->reg_base);
369
370 return 0;
371}