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Sathish Ambley9d69ac32012-03-21 10:28:26 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -070012
13/include/ "skeleton.dtsi"
Praveen Chidambaramaa9d52b2012-04-02 11:09:47 -060014/include/ "msmcopper_pm.dtsi"
David Collinsb20f6362012-04-19 16:36:51 -070015/include/ "msm-pm8x41-rpm-regulator.dtsi"
David Collins153d45a2012-03-26 11:57:50 -070016/include/ "msm-pm8841.dtsi"
17/include/ "msm-pm8941.dtsi"
18/include/ "msmcopper-regulator.dtsi"
Michael Bohan8b909b42012-04-18 17:39:12 -070019/include/ "msmcopper-gpio.dtsi"
Sathish Ambleyd1b89ed2012-02-07 21:47:47 -080020/include/ "msmcopper-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -080021/include/ "msm-gdsc.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -070022
23/ {
24 model = "Qualcomm MSM Copper";
Sathish Ambley9d69ac32012-03-21 10:28:26 -070025 compatible = "qcom,msmcopper";
Sathish Ambley4df614c2011-10-07 16:30:46 -070026 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@F9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -080031 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -070032 reg = <0xF9000000 0x1000>,
33 <0xF9002000 0x1000>;
34 };
Sathish Ambley3d50c762011-10-25 15:26:00 -070035
Sathish Ambleye046b242012-04-09 12:38:05 -070036 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -080037 compatible = "qcom,msm-gpio";
38 interrupt-controller;
39 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -070040 reg = <0xfd510000 0x4000>;
41 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -080042 };
43
Sathish Ambley098f9bd2011-11-09 16:32:53 -080044 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -070045 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -070046 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -070047 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -080048 };
49
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -080050 qcom,vidc@fdc00000 {
51 compatible = "qcom,msm-vidc";
52 reg = <0xfdc00000 0xff000>;
53 interrupts = <0 44 0>;
54 };
55
David Brown225abee2012-02-09 22:28:50 -080056 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -070057 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -080058 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080059 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -070060 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053061
Sathish Ambley9d69ac32012-03-21 10:28:26 -070062 serial@f995e000 {
63 compatible = "qcom,msm-lsuart-v14";
64 reg = <0xf995e000 0x1000>;
65 interrupts = <0 114 0>;
66 };
67
David Brown225abee2012-02-09 22:28:50 -080068 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053069 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -080070 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -080071 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -070072 HSUSB_VDDCX-supply = <&pm8841_s2>;
73 HSUSB_1p8-supply = <&pm8941_l6>;
74 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053075
76 qcom,hsusb-otg-phy-type = <2>;
77 qcom,hsusb-otg-mode = <1>;
78 qcom,hsusb-otg-otg-control = <1>;
79 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053080
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053081 qcom,sdcc@f9824000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053082 cell-index = <1>;
83 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053084 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080085 interrupts = <0 123 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053086
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053087 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
88 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053089 qcom,sdcc-bus-width = <8>;
Subhash Jadavani56e0eaa2012-03-13 18:06:04 +053090 qcom,sdcc-hs200;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053091 qcom,sdcc-nonremovable;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053092 };
93
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053094 qcom,sdcc@f98a4000 {
95 cell-index = <2>;
96 compatible = "qcom,msm-sdcc";
97 reg = <0xf98a4000 0x1000>;
98 interrupts = <0 125 0>;
99
100 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
101 qcom,sdcc-sup-voltages = <2950 2950>;
102 qcom,sdcc-bus-width = <4>;
103 };
104
105 qcom,sdcc@f9864000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530106 cell-index = <3>;
107 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530108 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800109 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530110
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530111 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
112 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530113 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530114 };
115
116 qcom,sdcc@f98e4000 {
117 cell-index = <4>;
118 compatible = "qcom,msm-sdcc";
119 reg = <0xf98e4000 0x1000>;
120 interrupts = <0 129 0>;
121
122 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
123 qcom,sdcc-sup-voltages = <1800 1800>;
124 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530125 };
Yan He1466daa2011-11-30 17:25:38 -0800126
David Brown225abee2012-02-09 22:28:50 -0800127 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800128 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800129 reg = <0xf9984000 0x15000>,
130 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800131 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800132
133 qcom,bam-dma-res-pipes = <6>;
134 };
135
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700136
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700137 spi@f9924000 {
138 compatible = "qcom,spi-qup-v2";
139 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800140 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700141 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700142 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700143
Sagar Dhariaa316a962012-03-21 16:13:22 -0600144 slim@fe12f000 {
145 cell-index = <1>;
146 compatible = "qcom,slim-msm";
147 reg = <0xfe12f000 0x35000>,
148 <0xfe104000 0x20000>;
149 reg-names = "slimbus_physical", "slimbus_bam_physical";
150 interrupts = <0 163 0 0 164 0>;
151 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
152 qcom,min-clk-gear = <10>;
153 };
154
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700155 qcom,spmi@fc4c0000 {
156 cell-index = <0>;
157 compatible = "qcom,spmi-pmic-arb";
158 reg = <0xfc4cf000 0x1000>,
159 <0Xfc4cb000 0x1000>;
160 /* 190,ee0_krait_hlos_spmi_periph_irq */
161 /* 187,channel_0_krait_hlos_trans_done_irq */
162 interrupts = <0 190 0 0 187 0>;
163 qcom,pmic-arb-ee = <0>;
164 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700165 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
166 <0x13100001>, /* PM8941_LDO2 */
167 <0x13200002>, /* PM8941_LDO3 */
168 <0x13300003>, /* PM8941_LDO4 */
169 <0x13400004>, /* PM8941_LDO5 */
170 <0x13500005>, /* PM8941_LDO6 */
171 <0x13600006>, /* PM8941_LDO7 */
172 <0x13700007>, /* PM8941_LDO8 */
173 <0x13800008>, /* PM8941_LDO9 */
174 <0x13900009>, /* PM8941_LDO10 */
175 <0x13a0000a>, /* PM8941_LDO11 */
176 <0x13b0000b>, /* PM8941_LDO12 */
177 <0x13c0000c>, /* PM8941_LDO13 */
178 <0x13d0000d>, /* PM8941_LDO14 */
179 <0x13e0000e>, /* PM8941_LDO15 */
180 <0x13f0000f>, /* PM8941_LDO16 */
181 <0x14000010>, /* PM8941_LDO17 */
182 <0x14100011>, /* PM8941_LDO18 */
183 <0x14200012>, /* PM8941_LDO19 */
184 <0x14300013>, /* PM8941_LDO20 */
185 <0x14400014>, /* PM8941_LDO21 */
186 <0x14500015>, /* PM8941_LDO22 */
187 <0x14600016>, /* PM8941_LDO23 */
188 <0x14700017>, /* PM8941_LDO24 */
189 <0x14800018>, /* PM8941_LDO25 */
190 <0x14900019>, /* PM8941_LDO26 */
191 <0x0c00001a>, /* PM8941_GPIO1 */
192 <0x0c10001b>, /* PM8941_GPIO2 */
193 <0x0c20001c>, /* PM8941_GPIO3 */
194 <0x0c30001d>, /* PM8941_GPIO4 */
195 <0x0c40001e>, /* PM8941_GPIO5 */
196 <0x0c50001f>, /* PM8941_GPIO6 */
197 <0x0c600020>, /* PM8941_GPIO7 */
198 <0x0c700021>, /* PM8941_GPIO8 */
199 <0x0c800022>, /* PM8941_GPIO9 */
200 <0x0c900023>, /* PM8941_GPIO10 */
201 <0x0ca00024>, /* PM8941_GPIO11 */
202 <0x0cb00025>, /* PM8941_GPIO12 */
203 <0x0cc00026>, /* PM8941_GPIO13 */
204 <0x0cd00027>, /* PM8941_GPIO14 */
205 <0x0ce00028>, /* PM8941_GPIO15 */
206 <0x0cf00029>, /* PM8941_GPIO16 */
207 <0x0d00002a>, /* PM8941_GPIO17 */
208 <0x0d10002b>, /* PM8941_GPIO18 */
209 <0x0d20002c>, /* PM8941_GPIO19 */
210 <0x0d30002d>, /* PM8941_GPIO20 */
211 <0x0d40002e>, /* PM8941_GPIO21 */
212 <0x0d50002f>, /* PM8941_GPIO22 */
213 <0x0d600030>, /* PM8941_GPIO23 */
214 <0x0d700031>, /* PM8941_GPIO24 */
215 <0x0d800032>, /* PM8941_GPIO25 */
216 <0x0d900033>, /* PM8941_GPIO26 */
217 <0x0da00034>, /* PM8941_GPIO27 */
218 <0x0db00035>, /* PM8941_GPIO28 */
219 <0x0dc00036>, /* PM8941_GPIO29 */
220 <0x0dd00037>, /* PM8941_GPIO30 */
221 <0x0de00038>, /* PM8941_GPIO31 */
222 <0x0df00039>, /* PM8941_GPIO32 */
223 <0x0e00003a>, /* PM8941_GPIO33 */
224 <0x0e10003b>, /* PM8941_GPIO34 */
225 <0x0e20003c>, /* PM8941_GPIO35 */
226 <0x0e30003d>, /* PM8941_GPIO36 */
227 <0x0280003e>, /* COINCELL */
228 <0x0100003f>, /* SMBC_OVP */
229 <0x01100040>, /* SMBC_CHG */
230 <0x01200041>, /* SMBC_BIF */
231 <0x00500042>, /* INTERRUPT */
232 <0x00100043>, /* PM8941_0 */
233 <0x20100044>, /* PM8841_0 */
234 <0x10100045>, /* PM8941_1 */
235 <0x30100046>, /* PM8841_1 */
236 <0x00800047>, /* PON0 */
237 <0x20800048>, /* PON1 */
238 <0x11000049>, /* PM8941_SMPS1 */
239 <0x1110004a>, /* PM8941_SMPS2 */
240 <0x1120004b>, /* PM8941_SMPS3 */
241 <0x3100004c>, /* PM8841_SMPS1 */
242 <0x3110004d>, /* PM8841_SMPS2 */
243 <0x3120004e>, /* PM8841_SMPS3 */
244 <0x3130004f>, /* PM8841_SMPS4 */
245 <0x31400050>, /* PM8841_SMPS5 */
246 <0x31500051>, /* PM8841_SMPS6 */
247 <0x31600052>, /* PM8841_SMPS7 */
248 <0x31700053>, /* PM8841_SMPS8 */
249 <0x05000054>, /* SHARED_XO */
250 <0x05100055>, /* BB_CLK1 */
251 <0x05200056>, /* BB_CLK2 */
252 <0x05900057>, /* SLEEP_CLK */
253 <0x07000058>, /* PBS_CORE */
254 <0x07100059>, /* PBS_CLIENT1 */
255 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700256 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700257
258 i2c@f9966000 {
259 cell-index = <0>;
260 compatible = "qcom,i2c-qup";
261 reg = <0Xf9966000 0x1000>;
262 reg-names = "qup_phys_addr";
263 interrupts = <0 104 0>;
264 interrupt-names = "qup_err_intr";
265 qcom,i2c-bus-freq = <100000>;
266 qcom,i2c-src-freq = <24000000>;
267 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800268
Matt Wagantall48523022012-04-23 13:28:42 -0700269 qcom,acpuclk@f9000000 {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800270 compatible = "qcom,acpuclk-copper";
271 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200272
273 qcom,ssusb@F9200000 {
274 compatible = "qcom,dwc-usb3-msm";
275 reg = <0xF9200000 0xCCFF>;
276 interrupts = <0 131 0>;
277 qcom,dwc-usb3-msm-dbm-eps = <4>;
278 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700279
Matt Wagantallfc727212012-01-06 18:18:25 -0800280 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
281 parent-supply = <&pm8841_s4>;
282 };
283
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700284 qcom,lpass@fe200000 {
285 compatible = "qcom,pil-q6v5-lpass";
286 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700287 <0xfd485100 0x00010>;
288
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700289 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700290 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800291
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700292 qcom,mss@fc880000 {
293 compatible = "qcom,pil-q6v5-mss";
294 reg = <0xfc880000 0x100>,
295 <0xfd485000 0x400>,
296 <0xfc820000 0x020>,
297 <0xfc401680 0x004>;
298 vdd_mss-supply = <&pm8841_s3>;
299
300 qcom,firmware-name = "mba";
301 qcom,pil-self-auth = <1>;
302 };
303
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800304 qcom,mba@fc820000 {
305 compatible = "qcom,pil-mba";
306 reg = <0xfc820000 0x0020>,
307 <0x0d1fc000 0x4000>;
308
309 qcom,firmware-name = "modem";
310 qcom,depends-on = "mba";
311 };
312
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800313 qcom,pronto@fb21b000 {
314 compatible = "qcom,pil-pronto";
315 reg = <0xfb21b000 0x3000>,
316 <0xfc401700 0x4>,
317 <0xfd485300 0xc>;
318 vdd_pronto_pll-supply = <&pm8941_l12>;
319
320 qcom,firmware-name = "wcnss";
321 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700322
323 qcom,ocmem@fdd00000 {
324 compatible = "qcom,msm_ocmem";
325 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600326
327 qcom,rpm-smd {
328 compatible = "qcom,rpm-smd";
329 rpm-channel-name = "rpm_requests";
330 rpm-channel-type = <15>; /* SMD_APPS_RPM */
331 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700332
333 qcom,msm-rng@f9bff000 {
334 compatible = "qcom,msm-rng";
335 reg = <0xf9bff000 0x200>;
336 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700337};