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review.evervolv.com / android_kernel_htc_msm8960 / e8bf5d53d8c07645f8955516136d9f3b074ff7b8 / . / arch / arm / boot / dts / msm8974.dtsi
blob: f9efec554247f1f0095a9cc84e2e460fd671a17a [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Kevin Chan350b6932012-08-01 02:21:00 -0700[diff] [blame]16/include/ "msm8974-camera.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Olav Haugan49173442012-08-01 13:23:18 -0700[diff] [blame]18/include/ "msm8974-ion.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]19/include/ "msm8974-gpu.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]20
21/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]22 model = "Qualcomm MSM 8974";
23 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]24 interrupt-parent = <&intc>;
25
26 intc: interrupt-controller@F9000000 {
27 compatible = "qcom,msm-qgic2";
28 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]29 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]30 reg = <0xF9000000 0x1000>,
31 <0xF9002000 0x1000>;
32 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]33
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]34 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]35 compatible = "qcom,msm-gpio";
Rohit Vaswanib1cc4932012-07-23 21:30:11 -0700[diff] [blame]36 gpio-controller;
37 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]38 interrupt-controller;
39 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]40 reg = <0xfd510000 0x4000>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]41 };
42
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]43 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]44 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]45 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]46 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]47 };
48
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]49 qcom,vidc@fdc00000 {
50 compatible = "qcom,msm-vidc";
51 reg = <0xfdc00000 0xff000>;
52 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]53 vidc-cp-map = <0x1000000 0x40000000>;
54 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -0700[diff] [blame]55 load-freq-tbl = <979200 410000000>,
56 <560145 266670000>,
57 <421161 200000000>,
58 <243000 133330000>,
59 <108000 100000000>,
60 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]61 };
62
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]63 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]64 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]65 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]66 interrupts = <0 109 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]67 status = "disabled";
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]68 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]69
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]70 serial@f995e000 {
71 compatible = "qcom,msm-lsuart-v14";
72 reg = <0xf995e000 0x1000>;
73 interrupts = <0 114 0>;
Stepan Moskovchenko43f11582012-08-08 17:20:38 -0700[diff] [blame]74 status = "disabled";
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]75 };
76
Stepan Moskovchenko5269b602012-08-08 17:57:09 -0700[diff] [blame]77 serial@f991e000 {
78 compatible = "qcom,msm-lsuart-v14";
79 reg = <0xf991e000 0x1000>;
80 interrupts = <0 108 0>;
81 status = "disabled";
82 };
83
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]84 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]85 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]86 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]87 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]88 HSUSB_VDDCX-supply = <&pm8841_s2>;
89 HSUSB_1p8-supply = <&pm8941_l6>;
90 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]91
92 qcom,hsusb-otg-phy-type = <2>;
93 qcom,hsusb-otg-mode = <1>;
94 qcom,hsusb-otg-otg-control = <1>;
Manu Gautambd53fba2012-07-31 16:13:06 +0530[diff] [blame]95 qcom,hsusb-otg-disable-reset;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]96 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]97
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]98 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]99 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]100 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]101 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]102 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]103 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]104 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]105 vdd-supply = <&pm8941_l20>;
106 vdd-io-supply = <&pm8941_s3>;
107
108 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
109 qcom,sdcc-vdd-current_level = <800 500000>;
110
111 qcom,sdcc-vdd-io-always_on;
112 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
113 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]114
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]115 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
116 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
117 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
118 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
119
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]120 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
121 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]122 qcom,sdcc-bus-width = <8>;
123 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]124 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]125 };
126
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]127 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]128 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]129 compatible = "qcom,msm-sdcc";
130 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]131 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]132 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]133 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]134 vdd-supply = <&pm8941_l21>;
135 vdd-io-supply = <&pm8941_l13>;
136
137 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
138 qcom,sdcc-vdd-current_level = <9000 800000>;
139
140 qcom,sdcc-vdd-io-always_on;
141 qcom,sdcc-vdd-io-lpm_sup;
142 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
143 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]144
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]145 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
146 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
147 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
148 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
149
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]150 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
151 qcom,sdcc-sup-voltages = <2950 2950>;
152 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]153 qcom,sdcc-xpc;
154 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
155 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]156 };
157
158 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]159 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]160 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]161 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]162 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]163 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]164 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]165
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]166 gpios = <&msmgpio 40 0>, /* CLK */
167 <&msmgpio 39 0>, /* CMD */
168 <&msmgpio 38 0>, /* DATA0 */
169 <&msmgpio 37 0>, /* DATA1 */
170 <&msmgpio 36 0>, /* DATA2 */
171 <&msmgpio 35 0>; /* DATA3 */
172 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
173
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]174 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
175 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]176 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]177 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]178 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]179 };
180
181 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]182 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]183 compatible = "qcom,msm-sdcc";
184 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]185 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]186 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]187 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]188
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]189 gpios = <&msmgpio 93 0>, /* CLK */
190 <&msmgpio 91 0>, /* CMD */
191 <&msmgpio 96 0>, /* DATA0 */
192 <&msmgpio 95 0>, /* DATA1 */
193 <&msmgpio 94 0>, /* DATA2 */
194 <&msmgpio 92 0>; /* DATA3 */
195 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
196
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]197 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
198 qcom,sdcc-sup-voltages = <1800 1800>;
199 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]200 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]201 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]202 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]203
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]204 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]205 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]206 reg = <0xf9984000 0x15000>,
207 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]208 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]209
210 qcom,bam-dma-res-pipes = <6>;
211 };
212
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]213
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]214 spi@f9924000 {
215 compatible = "qcom,spi-qup-v2";
216 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]217 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]218 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]219 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]220
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]221 slim@fe12f000 {
222 cell-index = <1>;
223 compatible = "qcom,slim-msm";
224 reg = <0xfe12f000 0x35000>,
225 <0xfe104000 0x20000>;
226 reg-names = "slimbus_physical", "slimbus_bam_physical";
227 interrupts = <0 163 0 0 164 0>;
228 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
229 qcom,min-clk-gear = <10>;
Sagar Dhariac0d6cf52012-07-31 19:17:26 -0600[diff] [blame]230 qcom,rxreg-access;
Kiran Kandie8bf5d52012-08-06 16:03:16 -0700[diff] [blame^]231
232 taiko_codec {
233 compatible = "qcom,taiko-slim-pgd";
234 elemental-addr = [00 01 A0 00 17 02];
235
236 qcom,cdc-reset-gpio = <&msmgpio 63 0>;
237
238 cdc-vdd-buck-supply = <&pm8941_s2>;
239 qcom,cdc-vdd-buck-voltage = <2150000 2150000>;
240 qcom,cdc-vdd-buck-current = <650000>;
241
242 cdc-vdd-tx-h-supply = <&pm8941_s3>;
243 qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
244 qcom,cdc-vdd-tx-h-current = <25000>;
245
246 cdc-vdd-rx-h-supply = <&pm8941_s3>;
247 qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
248 qcom,cdc-vdd-rx-h-current = <25000>;
249
250 cdc-vddpx-1-supply = <&pm8941_s3>;
251 qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
252 qcom,cdc-vddpx-1-current = <10000>;
253
254 cdc-vdd-a-1p2v-supply = <&pm8941_l1>;
255 qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>;
256 qcom,cdc-vdd-a-1p2v-current = <10000>;
257
258 cdc-vddcx-1-supply = <&pm8941_l1>;
259 qcom,cdc-vddcx-1-voltage = <1225000 1225000>;
260 qcom,cdc-vddcx-1-current = <10000>;
261
262 cdc-vddcx-2-supply = <&pm8941_l1>;
263 qcom,cdc-vddcx-2-voltage = <1225000 1225000>;
264 qcom,cdc-vddcx-2-current = <10000>;
265
266 qcom,cdc-micbias-ldoh-v = <0x3>;
267 qcom,cdc-micbias-cfilt1-mv = <1800>;
268 qcom,cdc-micbias-cfilt2-mv = <2700>;
269 qcom,cdc-micbias-cfilt3-mv = <1800>;
270 qcom,cdc-micbias1-cfilt-sel = <0x0>;
271 qcom,cdc-micbias2-cfilt-sel = <0x1>;
272 qcom,cdc-micbias3-cfilt-sel = <0x2>;
273 qcom,cdc-micbias4-cfilt-sel = <0x2>;
274
275 qcom,cdc-slim-ifd = "taiko-slim-ifd";
276 qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02];
277 };
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]278 };
279
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]280 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]281 cell-index = <0>;
282 compatible = "qcom,spmi-pmic-arb";
283 reg = <0xfc4cf000 0x1000>,
284 <0Xfc4cb000 0x1000>;
285 /* 190,ee0_krait_hlos_spmi_periph_irq */
286 /* 187,channel_0_krait_hlos_trans_done_irq */
287 interrupts = <0 190 0 0 187 0>;
288 qcom,pmic-arb-ee = <0>;
289 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]290 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
291 <0x13100001>, /* PM8941_LDO2 */
292 <0x13200002>, /* PM8941_LDO3 */
293 <0x13300003>, /* PM8941_LDO4 */
294 <0x13400004>, /* PM8941_LDO5 */
295 <0x13500005>, /* PM8941_LDO6 */
296 <0x13600006>, /* PM8941_LDO7 */
297 <0x13700007>, /* PM8941_LDO8 */
298 <0x13800008>, /* PM8941_LDO9 */
299 <0x13900009>, /* PM8941_LDO10 */
300 <0x13a0000a>, /* PM8941_LDO11 */
301 <0x13b0000b>, /* PM8941_LDO12 */
302 <0x13c0000c>, /* PM8941_LDO13 */
303 <0x13d0000d>, /* PM8941_LDO14 */
304 <0x13e0000e>, /* PM8941_LDO15 */
305 <0x13f0000f>, /* PM8941_LDO16 */
306 <0x14000010>, /* PM8941_LDO17 */
307 <0x14100011>, /* PM8941_LDO18 */
308 <0x14200012>, /* PM8941_LDO19 */
309 <0x14300013>, /* PM8941_LDO20 */
310 <0x14400014>, /* PM8941_LDO21 */
311 <0x14500015>, /* PM8941_LDO22 */
312 <0x14600016>, /* PM8941_LDO23 */
313 <0x14700017>, /* PM8941_LDO24 */
314 <0x14800018>, /* PM8941_LDO25 */
315 <0x14900019>, /* PM8941_LDO26 */
316 <0x0c00001a>, /* PM8941_GPIO1 */
317 <0x0c10001b>, /* PM8941_GPIO2 */
318 <0x0c20001c>, /* PM8941_GPIO3 */
319 <0x0c30001d>, /* PM8941_GPIO4 */
320 <0x0c40001e>, /* PM8941_GPIO5 */
321 <0x0c50001f>, /* PM8941_GPIO6 */
322 <0x0c600020>, /* PM8941_GPIO7 */
323 <0x0c700021>, /* PM8941_GPIO8 */
324 <0x0c800022>, /* PM8941_GPIO9 */
325 <0x0c900023>, /* PM8941_GPIO10 */
326 <0x0ca00024>, /* PM8941_GPIO11 */
327 <0x0cb00025>, /* PM8941_GPIO12 */
328 <0x0cc00026>, /* PM8941_GPIO13 */
329 <0x0cd00027>, /* PM8941_GPIO14 */
330 <0x0ce00028>, /* PM8941_GPIO15 */
331 <0x0cf00029>, /* PM8941_GPIO16 */
332 <0x0d00002a>, /* PM8941_GPIO17 */
333 <0x0d10002b>, /* PM8941_GPIO18 */
334 <0x0d20002c>, /* PM8941_GPIO19 */
335 <0x0d30002d>, /* PM8941_GPIO20 */
336 <0x0d40002e>, /* PM8941_GPIO21 */
337 <0x0d50002f>, /* PM8941_GPIO22 */
338 <0x0d600030>, /* PM8941_GPIO23 */
339 <0x0d700031>, /* PM8941_GPIO24 */
340 <0x0d800032>, /* PM8941_GPIO25 */
341 <0x0d900033>, /* PM8941_GPIO26 */
342 <0x0da00034>, /* PM8941_GPIO27 */
343 <0x0db00035>, /* PM8941_GPIO28 */
344 <0x0dc00036>, /* PM8941_GPIO29 */
345 <0x0dd00037>, /* PM8941_GPIO30 */
346 <0x0de00038>, /* PM8941_GPIO31 */
347 <0x0df00039>, /* PM8941_GPIO32 */
348 <0x0e00003a>, /* PM8941_GPIO33 */
349 <0x0e10003b>, /* PM8941_GPIO34 */
350 <0x0e20003c>, /* PM8941_GPIO35 */
351 <0x0e30003d>, /* PM8941_GPIO36 */
352 <0x0280003e>, /* COINCELL */
353 <0x0100003f>, /* SMBC_OVP */
354 <0x01100040>, /* SMBC_CHG */
355 <0x01200041>, /* SMBC_BIF */
356 <0x00500042>, /* INTERRUPT */
357 <0x00100043>, /* PM8941_0 */
358 <0x20100044>, /* PM8841_0 */
359 <0x10100045>, /* PM8941_1 */
360 <0x30100046>, /* PM8841_1 */
361 <0x00800047>, /* PON0 */
362 <0x20800048>, /* PON1 */
363 <0x11000049>, /* PM8941_SMPS1 */
364 <0x1110004a>, /* PM8941_SMPS2 */
365 <0x1120004b>, /* PM8941_SMPS3 */
366 <0x3100004c>, /* PM8841_SMPS1 */
367 <0x3110004d>, /* PM8841_SMPS2 */
368 <0x3120004e>, /* PM8841_SMPS3 */
369 <0x3130004f>, /* PM8841_SMPS4 */
370 <0x31400050>, /* PM8841_SMPS5 */
371 <0x31500051>, /* PM8841_SMPS6 */
372 <0x31600052>, /* PM8841_SMPS7 */
373 <0x31700053>, /* PM8841_SMPS8 */
374 <0x05000054>, /* SHARED_XO */
375 <0x05100055>, /* BB_CLK1 */
376 <0x05200056>, /* BB_CLK2 */
377 <0x05900057>, /* SLEEP_CLK */
378 <0x07000058>, /* PBS_CORE */
379 <0x07100059>, /* PBS_CLIENT1 */
380 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]381 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]382
383 i2c@f9966000 {
384 cell-index = <0>;
385 compatible = "qcom,i2c-qup";
386 reg = <0Xf9966000 0x1000>;
387 reg-names = "qup_phys_addr";
388 interrupts = <0 104 0>;
389 interrupt-names = "qup_err_intr";
390 qcom,i2c-bus-freq = <100000>;
391 qcom,i2c-src-freq = <24000000>;
392 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]393
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]394 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]395 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]396 krait0-supply = <&krait0_vreg>;
397 krait1-supply = <&krait1_vreg>;
398 krait2-supply = <&krait2_vreg>;
399 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]400 krait0_mem-supply = <&pm8841_s1_ao>;
401 krait1_mem-supply = <&pm8841_s1_ao>;
402 krait2_mem-supply = <&pm8841_s1_ao>;
403 krait3_mem-supply = <&pm8841_s1_ao>;
404 krait0_dig-supply = <&pm8841_s2_corner_ao>;
405 krait1_dig-supply = <&pm8841_s2_corner_ao>;
406 krait2_dig-supply = <&pm8841_s2_corner_ao>;
407 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]408 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
409 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
410 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
411 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
412 l2_hfpll_a-supply = <&pm8941_s2_ao>;
413 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
414 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
415 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
416 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
417 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]418 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]419
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]420 qcom,ssusb@f9200000 {
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]421 compatible = "qcom,dwc-usb3-msm";
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]422 reg = <0xf9200000 0xfc000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]423 interrupts = <0 131 0 0 179 0>;
424 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]425 SSUSB_VDDCX-supply = <&pm8841_s2>;
426 SSUSB_1p8-supply = <&pm8941_l6>;
427 HSUSB_VDDCX-supply = <&pm8841_s2>;
428 HSUSB_1p8-supply = <&pm8941_l6>;
429 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]430 qcom,dwc-usb3-msm-dbm-eps = <4>;
431 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]432
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]433 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
434 parent-supply = <&pm8841_s4>;
435 };
436
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]437 qcom,lpass@fe200000 {
438 compatible = "qcom,pil-q6v5-lpass";
439 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]440 <0xfd485100 0x00010>;
441
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]442 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]443 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]444
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]445 qcom,msm-pcm {
446 compatible = "qcom,msm-pcm-dsp";
447 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]448
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]449 qcom,msm-pcm-routing {
450 compatible = "qcom,msm-pcm-routing";
451 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]452
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]453 qcom,msm-pcm-lpa {
454 compatible = "qcom,msm-pcm-lpa";
455 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]456
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]457 qcom,msm-compr-dsp {
458 compatible = "qcom,msm-compr-dsp";
459 };
460
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]461 qcom,msm-voip-dsp {
462 compatible = "qcom,msm-voip-dsp";
463 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]464
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]465 qcom,msm-stub-codec {
466 compatible = "qcom,msm-stub-codec";
467 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]468
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]469 qcom,msm-dai-fe {
470 compatible = "qcom,msm-dai-fe";
471 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]472
Joonwoo Park6572ac52012-07-10 17:17:00 -0700[diff] [blame]473 qcom,msm-dai-q6 {
474 compatible = "qcom,msm-dai-q6";
475 qcom,msm-dai-q6-sb-0-rx {
476 compatible = "qcom,msm-dai-q6-dev";
477 qcom,msm-dai-q6-dev-id = <16384>;
478 };
479
480 qcom,msm-dai-q6-sb-0-tx {
481 compatible = "qcom,msm-dai-q6-dev";
482 qcom,msm-dai-q6-dev-id = <16385>;
483 };
484 };
485
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]486 qcom,msm-auxpcm {
487 compatible = "qcom,msm-auxpcm-resource";
488 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
489 qcom,msm-cpudai-auxpcm-mode = <0>;
490 qcom,msm-cpudai-auxpcm-sync = <1>;
491 qcom,msm-cpudai-auxpcm-frame = <5>;
492 qcom,msm-cpudai-auxpcm-quant = <2>;
493 qcom,msm-cpudai-auxpcm-slot = <1>;
494 qcom,msm-cpudai-auxpcm-data = <0>;
495 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]496
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]497 qcom,msm-auxpcm-rx {
498 qcom,msm-auxpcm-dev-id = <4106>;
499 compatible = "qcom,msm-auxpcm-dev";
500 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]501
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]502 qcom,msm-auxpcm-tx {
503 qcom,msm-auxpcm-dev-id = <4107>;
504 compatible = "qcom,msm-auxpcm-dev";
505 };
506 };
507
508 qcom,msm-pcm-hostless {
509 compatible = "qcom,msm-pcm-hostless";
510 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]511
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700[diff] [blame]512 qcom,msm-ocmem-audio {
513 compatible = "qcom,msm-ocmem-audio";
514 qcom,msm-ocmem-audio-src-id = <11>;
515 qcom,msm-ocmem-audio-dst-id = <604>;
516 qcom,msm-ocmem-audio-ab = <32505856>;
517 qcom,msm-ocmem-audio-ib = <32505856>;
518 };
519
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]520 qcom,mss@fc880000 {
521 compatible = "qcom,pil-q6v5-mss";
522 reg = <0xfc880000 0x100>,
523 <0xfd485000 0x400>,
524 <0xfc820000 0x020>,
Matt Wagantall16bc5cc2012-08-09 21:33:23 -0700[diff] [blame]525 <0xfc401680 0x004>,
526 <0xfc980008 0x004>;
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]527 vdd_mss-supply = <&pm8841_s3>;
528
529 qcom,firmware-name = "mba";
530 qcom,pil-self-auth = <1>;
531 };
532
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]533 qcom,mba@fc820000 {
534 compatible = "qcom,pil-mba";
535 reg = <0xfc820000 0x0020>,
536 <0x0d1fc000 0x4000>;
537
538 qcom,firmware-name = "modem";
539 qcom,depends-on = "mba";
540 };
541
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]542 qcom,pronto@fb21b000 {
543 compatible = "qcom,pil-pronto";
544 reg = <0xfb21b000 0x3000>,
545 <0xfc401700 0x4>,
546 <0xfd485300 0xc>;
547 vdd_pronto_pll-supply = <&pm8941_l12>;
548
549 qcom,firmware-name = "wcnss";
550 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]551
552 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]553 compatible = "qcom,msm-ocmem";
554 reg = <0xfdd00000 0x2000>,
555 <0xfdd02000 0x2000>,
556 <0xfe039000 0x400>,
557 <0xfec00000 0x180000>;
558 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
559 interrupts = <0 76 0 0 77 0>;
560 interrupt-names = "ocmem_irq", "dm_irq";
561 qcom,ocmem-num-regions = <0x3>;
Naveen Ramarajba3a6262012-08-02 17:14:27 -0700[diff] [blame]562 qcom,resource-type = <0x706d636f>;
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]563 #address-cells = <1>;
564 #size-cells = <1>;
565 ranges = <0x0 0xfec00000 0x180000>;
566
567 partition@0 {
568 reg = <0x0 0x100000>;
569 qcom,ocmem-part-name = "graphics";
570 qcom,ocmem-part-min = <0x80000>;
571 };
572
573 partition@80000 {
574 reg = <0x80000 0xA0000>;
575 qcom,ocmem-part-name = "lp_audio";
576 qcom,ocmem-part-min = <0xA0000>;
577 };
578
579 partition@E0000 {
580 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame]581 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]582 qcom,ocmem-part-min = <0x20000>;
583 };
584
585 partition@100000 {
586 reg = <0x100000 0x80000>;
587 qcom,ocmem-part-name = "video";
588 qcom,ocmem-part-min = <0x55000>;
589 };
590
591 partition@140000 {
592 reg = <0x140000 0x40000>;
593 qcom,ocmem-part-name = "sensors";
594 qcom,ocmem-part-min = <0x40000>;
595 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]596 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]597
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]598 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]599 compatible = "qcom,rpm-smd";
600 rpm-channel-name = "rpm_requests";
601 rpm-channel-type = <15>; /* SMD_APPS_RPM */
602 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]603
604 qcom,msm-rng@f9bff000 {
605 compatible = "qcom,msm-rng";
606 reg = <0xf9bff000 0x200>;
607 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]608
609 qcom,qseecom@fe806000 {
610 compatible = "qcom,qseecom";
611 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]612
613 qcom,mdss_mdp@fd900000 {
614 cell-index = <0>;
615 compatible = "qcom,mdss_mdp";
616 reg = <0xfd900000 0x22100>;
617 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]618 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]619 };
620
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]621 mdss_dsi: qcom,mdss_dsi@fd922800 {
622 cell-index = <1>;
623 compatible = "qcom,msm-mdss-dsi";
624 reg = <0xfd922800 0x5ac>,
625 <0xfd8c0000 0x01000>;
Chandan Uddarajude63dec2012-05-29 18:55:10 -0700[diff] [blame]626 };
627
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]628 qcom,mdss_wb_panel {
629 cell-index = <1>;
630 compatible = "qcom,mdss_wb";
631 qcom,mdss_pan_res = <640 480>;
632 qcom,mdss_pan_bpp = <24>;
633 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]634
635 qcom,wdt@f9017000 {
636 compatible = "qcom,msm-watchdog";
637 reg = <0xf9017000 0x1000>;
638 interrupts = <0 3 0 0 4 0>;
639 qcom,bark-time = <11000>;
640 qcom,pet-time = <10000>;
641 qcom,ipi-ping = <1>;
642 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]643
644 qcom,tz-log@fe805720 {
645 compatible = "qcom,tz-log";
646 reg = <0xfe805720 0x1000>;
647 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]648
649 qcom,venus@fdce0000 {
650 compatible = "qcom,pil-venus";
651 reg = <0xfdce0000 0x4000>,
652 <0xfdc80208 0x8>;
653 vdd-supply = <&gdsc_venus>;
654
655 qcom,firmware-name = "venus";
656 qcom,firmware-min-paddr = <0xF500000>;
657 qcom,firmware-max-paddr = <0xFA00000>;
658 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]659
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700[diff] [blame]660 qcom,cache_erp {
661 compatible = "qcom,cache_erp";
662 interrupts = <1 9 0>, <0 2 0>;
663 interrupt-names = "l1_irq", "l2_irq";
664 };
665
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]666 tsens@fc4a8000 {
667 compatible = "qcom,msm-tsens";
668 reg = <0xfc4a8000 0x2000>,
669 <0xfc4b80d0 0x5>;
670 reg-names = "tsens_physical", "tsens_eeprom_physical";
671 interrupts = <0 184 0>;
672 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700[diff] [blame]673 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
674 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]675 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700[diff] [blame]676
677 qcom,msm-rtb {
678 compatible = "qcom,msm-rtb";
679 qcom,memory-reservation-type = "EBI1";
680 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
681 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]682
683 qcom,qcedev@fd440000 {
684 compatible = "qcom,qcedev";
685 reg = <0xfd440000 0x20000>,
686 <0xfd444000 0x8000>;
687 interrupts = <0 235 0>;
688 qcom,bam-pipes = <0>;
689 };
690
691 qcom,qcrypto@fd444000 {
692 compatible = "qcom,qcrypto";
693 reg = <0xfd440000 0x20000>,
694 <0xfd444000 0x8000>;
695 interrupts = <0 235 0>;
696 qcom,bam-pipes = <1>;
697 };
Shimrit Malichi57ae1492012-08-06 14:03:45 +0300[diff] [blame]698
699 qcom,usbbam@f9304000 {
700 compatible = "qcom,usb-bam-msm";
701 reg = <0xf9304000 0x9000>;
702 interrupts = <0 132 0>;
703 qcom,usb-active-bam = <0>;
704 qcom,usb-total-bam-num = <1>;
705 qcom,usb-bam-num-pipes = <16>;
706 qcom,usb-base-address = <0xf9200000>;
707
708 qcom,pipe1 {
709 label = "usb-to-peri-qdss-dwc3";
710 qcom,usb-bam-type = <0>;
711 qcom,src-bam-physical-address = <0>;
712 qcom,src-bam-pipe-index = <0>;
713 qcom,dst-bam-physical-address = <0>;
714 qcom,dst-bam-pipe-index = <0>;
715 qcom,data-fifo-offset = <0>;
716 qcom,data-fifo-size = <0>;
717 qcom,descriptor-fifo-offset = <0>;
718 qcom,descriptor-fifo-size = <0>;
719 };
720
721 qcom,pipe2 {
722 label = "peri-to-usb-qdss-dwc3";
723 qcom,usb-bam-type = <0>;
724 qcom,src-bam-physical-address = <0xfc37C000>;
725 qcom,src-bam-pipe-index = <0>;
726 qcom,dst-bam-physical-address = <0xf9304000>;
727 qcom,dst-bam-pipe-index = <2>;
728 qcom,data-fifo-offset = <0xf0000>;
729 qcom,data-fifo-size = <0x4000>;
730 qcom,descriptor-fifo-offset = <0xf4000>;
731 qcom,descriptor-fifo-size = <0x1400>;
732 };
733 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]734};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]735
736/include/ "msm-pm8x41-rpm-regulator.dtsi"
737/include/ "msm-pm8841.dtsi"
738/include/ "msm-pm8941.dtsi"
739/include/ "msm8974-regulator.dtsi"
740/include/ "msm8974-gpio.dtsi"