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review.evervolv.com / android_kernel_htc_msm8960 / e8edc6e03a5c8562dc70a6d969f732bdb355a7e7 / . / drivers / pci / pcie / aer / aerdrv.h
blob: 5cca394d59993b14cdd2549781ea4aafe70648cc [file] [log] [blame]
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]1/*
2 * Copyright (C) 2006 Intel Corp.
3 * Tom Long Nguyen (tom.l.nguyen@intel.com)
4 * Zhang Yanmin (yanmin.zhang@intel.com)
5 *
6 */
7
8#ifndef _AERDRV_H_
9#define _AERDRV_H_
10
Alexey Dobriyane8edc6e2007-05-21 01:22:52 +0400[diff] [blame^]11#include <linux/workqueue.h>
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]12#include <linux/pcieport_if.h>
13#include <linux/aer.h>
14
15#define AER_NONFATAL 0
16#define AER_FATAL 1
17#define AER_CORRECTABLE 2
18#define AER_UNCORRECTABLE 4
19#define AER_ERROR_MASK 0x001fffff
20#define AER_ERROR(d) (d & AER_ERROR_MASK)
21
22#define OSC_METHOD_RUN_SUCCESS 0
23#define OSC_METHOD_NOT_SUPPORTED 1
24#define OSC_METHOD_RUN_FAILURE 2
25
26/* Root Error Status Register Bits */
27#define ROOT_ERR_STATUS_MASKS 0x0f
28
29#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
30 PCI_EXP_RTCTL_SENFEE| \
31 PCI_EXP_RTCTL_SEFEE)
32#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
33 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
34 PCI_ERR_ROOT_CMD_FATAL_EN)
35#define ERR_COR_ID(d) (d & 0xffff)
36#define ERR_UNCOR_ID(d) (d >> 16)
37
38#define AER_SUCCESS 0
39#define AER_UNSUCCESS 1
40#define AER_ERROR_SOURCES_MAX 100
41
42#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
43 PCI_ERR_UNC_ECRC| \
44 PCI_ERR_UNC_UNSUP| \
45 PCI_ERR_UNC_COMP_ABORT| \
46 PCI_ERR_UNC_UNX_COMP| \
47 PCI_ERR_UNC_MALF_TLP)
48
49/* AER Error Info Flags */
50#define AER_TLP_HEADER_VALID_FLAG 0x00000001
51#define AER_MULTI_ERROR_VALID_FLAG 0x00000002
52
53#define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
54#define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
55
56struct header_log_regs {
57 unsigned int dw0;
58 unsigned int dw1;
59 unsigned int dw2;
60 unsigned int dw3;
61};
62
63struct aer_err_info {
64 int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
65 int flags;
66 unsigned int status; /* COR/UNCOR Error Status */
67 struct header_log_regs tlp; /* TLP Header */
68};
69
70struct aer_err_source {
71 unsigned int status;
72 unsigned int id;
73};
74
75struct aer_rpc {
76 struct pcie_device *rpd; /* Root Port device */
77 struct work_struct dpc_handler;
78 struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
79 unsigned short prod_idx; /* Error Producer Index */
80 unsigned short cons_idx; /* Error Consumer Index */
81 int isr;
82 spinlock_t e_lock; /*
83 * Lock access to Error Status/ID Regs
84 * and error producer/consumer index
85 */
86 struct mutex rpc_mutex; /*
87 * only one thread could do
88 * recovery on the same
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +0100[diff] [blame]89 * root port hierarchy
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]90 */
91 wait_queue_head_t wait_release;
92};
93
94struct aer_broadcast_data {
95 enum pci_channel_state state;
96 enum pci_ers_result result;
97};
98
99static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
100 enum pci_ers_result new)
101{
102 switch (orig) {
103 case PCI_ERS_RESULT_CAN_RECOVER:
104 case PCI_ERS_RESULT_RECOVERED:
105 orig = new;
106 break;
107 case PCI_ERS_RESULT_DISCONNECT:
108 if (new == PCI_ERS_RESULT_NEED_RESET)
109 orig = new;
110 break;
111 default:
112 break;
113 }
114
115 return orig;
116}
117
118extern struct bus_type pcie_port_bus_type;
119extern void aer_enable_rootport(struct aer_rpc *rpc);
120extern void aer_delete_rootport(struct aer_rpc *rpc);
121extern int aer_init(struct pcie_device *dev);
David Howells65f27f32006-11-22 14:55:48 +0000[diff] [blame]122extern void aer_isr(struct work_struct *work);
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]123extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
124extern int aer_osc_setup(struct pci_dev *dev);
125
126#endif //_AERDRV_H_