Rohit Vaswani | e9a1ae3 | 2011-12-15 20:26:47 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/ioport.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <asm/mach-types.h> |
| 18 | #include <asm/mach/mmc.h> |
| 19 | #include <mach/msm_bus_board.h> |
| 20 | #include <mach/board.h> |
| 21 | #include <mach/gpiomux.h> |
| 22 | #include "devices.h" |
| 23 | |
| 24 | #if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT) \ |
| 25 | || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)) |
| 26 | |
| 27 | #define GPIO_SDC1_HW_DET 80 |
| 28 | #define GPIO_SDC2_DAT1_WAKEUP 26 |
| 29 | |
| 30 | /* MDM9x15 has 2 SDCC controllers */ |
| 31 | enum sdcc_controllers { |
| 32 | SDCC1, |
| 33 | SDCC2, |
| 34 | MAX_SDCC_CONTROLLER |
| 35 | }; |
| 36 | |
| 37 | #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT |
| 38 | /* All SDCC controllers requires VDD/VCC voltage */ |
| 39 | static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = { |
| 40 | /* SDCC1 : External card slot connected */ |
| 41 | [SDCC1] = { |
| 42 | .name = "sdc_vdd", |
| 43 | /* |
| 44 | * This is a gpio-regulator and does not support |
| 45 | * regulator_set_voltage and regulator_set_optimum_mode |
| 46 | */ |
| 47 | .high_vol_level = 2950000, |
| 48 | .low_vol_level = 2950000, |
| 49 | .hpm_uA = 600000, /* 600mA */ |
| 50 | } |
| 51 | }; |
| 52 | |
| 53 | /* All SDCC controllers may require voting for VDD PAD voltage */ |
| 54 | static struct msm_mmc_reg_data mmc_vddp_reg_data[MAX_SDCC_CONTROLLER] = { |
| 55 | /* SDCC1 : External card slot connected */ |
| 56 | [SDCC1] = { |
| 57 | .name = "sdc_vddp", |
| 58 | .high_vol_level = 2950000, |
| 59 | .low_vol_level = 1850000, |
| 60 | .always_on = true, |
| 61 | .lpm_sup = true, |
| 62 | /* Max. Active current required is 16 mA */ |
| 63 | .hpm_uA = 16000, |
| 64 | /* |
| 65 | * Sleep current required is ~300 uA. But min. vote can be |
| 66 | * in terms of mA (min. 1 mA). So let's vote for 2 mA |
| 67 | * during sleep. |
| 68 | */ |
| 69 | .lpm_uA = 2000, |
| 70 | } |
| 71 | }; |
| 72 | |
| 73 | static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = { |
| 74 | /* SDCC1 : External card slot connected */ |
| 75 | [SDCC1] = { |
| 76 | .vdd_data = &mmc_vdd_reg_data[SDCC1], |
| 77 | .vddp_data = &mmc_vddp_reg_data[SDCC1], |
| 78 | } |
| 79 | }; |
| 80 | |
| 81 | /* SDC1 pad data */ |
| 82 | static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = { |
| 83 | {TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA}, |
| 84 | {TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA}, |
| 85 | {TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA} |
| 86 | }; |
| 87 | |
| 88 | static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = { |
| 89 | {TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA}, |
| 90 | {TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA}, |
| 91 | {TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA} |
| 92 | }; |
| 93 | |
| 94 | static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = { |
| 95 | {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, |
| 96 | {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP}, |
| 97 | {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP} |
| 98 | }; |
| 99 | |
| 100 | static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = { |
| 101 | {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, |
| 102 | {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_DOWN}, |
| 103 | {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_DOWN} |
| 104 | }; |
| 105 | |
| 106 | static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = { |
| 107 | [SDCC1] = { |
| 108 | .on = sdc1_pad_pull_on_cfg, |
| 109 | .off = sdc1_pad_pull_off_cfg, |
| 110 | .size = ARRAY_SIZE(sdc1_pad_pull_on_cfg) |
| 111 | }, |
| 112 | }; |
| 113 | |
| 114 | static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = { |
| 115 | [SDCC1] = { |
| 116 | .on = sdc1_pad_drv_on_cfg, |
| 117 | .off = sdc1_pad_drv_off_cfg, |
| 118 | .size = ARRAY_SIZE(sdc1_pad_drv_on_cfg) |
| 119 | }, |
| 120 | }; |
| 121 | |
| 122 | static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = { |
| 123 | [SDCC1] = { |
| 124 | .pull = &mmc_pad_pull_data[SDCC1], |
| 125 | .drv = &mmc_pad_drv_data[SDCC1] |
| 126 | }, |
| 127 | }; |
| 128 | #endif |
| 129 | |
| 130 | #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT |
| 131 | |
| 132 | static struct msm_mmc_gpio sdc2_gpio_cfg[] = { |
| 133 | {25, "sdc2_dat_0"}, |
| 134 | {26, "sdc2_dat_1"}, |
| 135 | {27, "sdc2_dat_2"}, |
| 136 | {28, "sdc2_dat_3"}, |
| 137 | {29, "sdc2_cmd"}, |
| 138 | {30, "sdc2_clk"}, |
| 139 | }; |
| 140 | |
| 141 | static struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = { |
| 142 | [SDCC2] = { |
| 143 | .gpio = sdc2_gpio_cfg, |
| 144 | .size = ARRAY_SIZE(sdc2_gpio_cfg), |
| 145 | }, |
| 146 | }; |
| 147 | #endif |
| 148 | |
| 149 | static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = { |
| 150 | #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT |
| 151 | [SDCC1] = { |
| 152 | .is_gpio = 0, |
| 153 | .pad_data = &mmc_pad_data[SDCC1], |
| 154 | }, |
| 155 | #endif |
| 156 | #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT |
| 157 | [SDCC2] = { |
| 158 | .is_gpio = 1, |
| 159 | .gpio_data = &mmc_gpio_data[SDCC2], |
| 160 | }, |
| 161 | #endif |
| 162 | }; |
| 163 | |
| 164 | #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT |
| 165 | static unsigned int sdc1_sup_clk_rates[] = { |
| 166 | 400000, 24000000, 48000000 |
| 167 | }; |
| 168 | |
| 169 | static struct mmc_platform_data sdc1_data = { |
| 170 | .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, |
| 171 | .mmc_bus_width = MMC_CAP_4_BIT_DATA, |
| 172 | .sup_clk_table = sdc1_sup_clk_rates, |
| 173 | .sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates), |
| 174 | .pclk_src_dfab = true, |
| 175 | .vreg_data = &mmc_slot_vreg_data[SDCC1], |
| 176 | .pin_data = &mmc_slot_pin_data[SDCC1], |
| 177 | #ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION |
| 178 | .status_gpio = GPIO_SDC1_HW_DET, |
| 179 | .status_irq = MSM_GPIO_TO_INT(GPIO_SDC1_HW_DET), |
| 180 | .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 181 | #endif |
| 182 | .xpc_cap = 1, |
| 183 | .uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | |
| 184 | MMC_CAP_MAX_CURRENT_400) |
| 185 | }; |
| 186 | static struct mmc_platform_data *msm9615_sdc1_pdata = &sdc1_data; |
| 187 | #else |
| 188 | static struct mmc_platform_data *msm9615_sdc1_pdata; |
| 189 | #endif |
| 190 | |
| 191 | #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT |
| 192 | static unsigned int sdc2_sup_clk_rates[] = { |
| 193 | 400000, 24000000, 48000000 |
| 194 | }; |
| 195 | |
| 196 | static struct mmc_platform_data sdc2_data = { |
| 197 | .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, |
| 198 | .mmc_bus_width = MMC_CAP_4_BIT_DATA, |
| 199 | .sup_clk_table = sdc2_sup_clk_rates, |
| 200 | .sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates), |
| 201 | .pclk_src_dfab = 1, |
| 202 | .pin_data = &mmc_slot_pin_data[SDCC2], |
| 203 | #ifdef CONFIG_MMC_MSM_SDIO_SUPPORT |
| 204 | .sdiowakeup_irq = MSM_GPIO_TO_INT(GPIO_SDC2_DAT1_WAKEUP), |
| 205 | #endif |
| 206 | }; |
| 207 | static struct mmc_platform_data *msm9615_sdc2_pdata = &sdc2_data; |
| 208 | #else |
| 209 | static struct mmc_platform_data *msm9615_sdc2_pdata; |
| 210 | #endif |
| 211 | |
| 212 | void __init msm9615_init_mmc(void) |
| 213 | { |
| 214 | if (msm9615_sdc1_pdata) { |
| 215 | /* SDC1: External card slot for SD/MMC cards */ |
| 216 | msm_add_sdcc(1, msm9615_sdc1_pdata); |
| 217 | } |
| 218 | |
| 219 | if (msm9615_sdc2_pdata) { |
| 220 | /* SDC2: External card slot used for WLAN */ |
| 221 | msm_add_sdcc(2, msm9615_sdc2_pdata); |
| 222 | } |
| 223 | } |
| 224 | #else |
| 225 | void __init msm9615_init_mmc(void) |
| 226 | { |
| 227 | } |
| 228 | #endif |