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review.evervolv.com / android_kernel_htc_msm8960 / ea2562d94fade3d6ee9b22ed5addbbdba697d22a / . / arch / sparc64 / kernel / hvtramp.S
blob: b692e044a463420327862689d51097a60b129119 [file] [log] [blame]
David S. Miller4f0234f2007-07-13 16:03:42 -0700[diff] [blame]1/* hvtramp.S: Hypervisor start-cpu trampoline code.
2 *
3 * Copyright (C) 2007 David S. Miller <davem@davemloft.net>
4 */
5
6#include <asm/thread_info.h>
7#include <asm/hypervisor.h>
8#include <asm/scratchpad.h>
9#include <asm/spitfire.h>
10#include <asm/hvtramp.h>
11#include <asm/pstate.h>
12#include <asm/ptrace.h>
David S. Miller41120552007-07-16 21:33:19 -0700[diff] [blame]13#include <asm/head.h>
David S. Miller4f0234f2007-07-13 16:03:42 -0700[diff] [blame]14#include <asm/asi.h>
15
16 .text
17 .align 8
18 .globl hv_cpu_startup, hv_cpu_startup_end
19
20 /* This code executes directly out of the hypervisor
21 * with physical addressing (va==pa). %o0 contains
22 * our client argument which for Linux points to
23 * a descriptor data structure which defines the
24 * MMU entries we need to load up.
25 *
26 * After we set things up we enable the MMU and call
27 * into the kernel.
28 *
29 * First setup basic privileged cpu state.
30 */
31hv_cpu_startup:
David S. Miller41120552007-07-16 21:33:19 -0700[diff] [blame]32 SET_GL(0)
David S. Miller4f0234f2007-07-13 16:03:42 -0700[diff] [blame]33 wrpr %g0, 15, %pil
34 wrpr %g0, 0, %canrestore
35 wrpr %g0, 0, %otherwin
36 wrpr %g0, 6, %cansave
37 wrpr %g0, 6, %cleanwin
38 wrpr %g0, 0, %cwp
39 wrpr %g0, 0, %wstate
40 wrpr %g0, 0, %tl
41
42 sethi %hi(sparc64_ttable_tl0), %g1
43 wrpr %g1, %tba
44
45 mov %o0, %l0
46
47 lduw [%l0 + HVTRAMP_DESCR_CPU], %g1
48 mov SCRATCHPAD_CPUID, %g2
49 stxa %g1, [%g2] ASI_SCRATCHPAD
50
51 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
52 stxa %g2, [%g0] ASI_SCRATCHPAD
53
54 mov 0, %l1
55 lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
56 add %l0, HVTRAMP_DESCR_MAPS, %l3
57
581: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0
59 clr %o1
60 ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2
61 mov HV_MMU_IMMU | HV_MMU_DMMU, %o3
62 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
63 ta HV_FAST_TRAP
64
65 brnz,pn %o0, 80f
66 nop
67
68 add %l1, 1, %l1
69 cmp %l1, %l2
70 blt,a,pt %xcc, 1b
71 add %l3, HVTRAMP_MAPPING_SIZE, %l3
72
73 ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
74 mov HV_FAST_MMU_FAULT_AREA_CONF, %o5
75 ta HV_FAST_TRAP
76
77 brnz,pn %o0, 80f
78 nop
79
80 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
81
82 ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
83
84 mov 1, %o0
85 set 1f, %o1
86 mov HV_FAST_MMU_ENABLE, %o5
87 ta HV_FAST_TRAP
88
89 ba,pt %xcc, 80f
90 nop
91
921:
93 wr %g0, 0, %fprs
94 wr %g0, ASI_P, %asi
95
96 mov PRIMARY_CONTEXT, %g7
97 stxa %g0, [%g7] ASI_MMU
98 membar #Sync
99
100 mov SECONDARY_CONTEXT, %g7
101 stxa %g0, [%g7] ASI_MMU
102 membar #Sync
103
104 mov %l6, %g6
105 ldx [%g6 + TI_TASK], %g4
106
107 mov 1, %g5
108 sllx %g5, THREAD_SHIFT, %g5
109 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
110 add %g6, %g5, %sp
111 mov 0, %fp
112
113 call init_irqwork_curcpu
114 nop
115 call hard_smp_processor_id
116 nop
117
David S. Millerb434e712007-08-08 17:32:33 -0700[diff] [blame]118 call sun4v_register_mondo_queues
119 nop
David S. Miller4f0234f2007-07-13 16:03:42 -0700[diff] [blame]120
121 call init_cur_cpu_trap
122 mov %g6, %o0
123
124 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
125
126 call smp_callin
127 nop
128 call cpu_idle
129 mov 0, %o0
130 call cpu_panic
131 nop
132
13380: ba,pt %xcc, 80b
134 nop
135
136 .align 8
137hv_cpu_startup_end: