| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * include/asm-v850/v850e_utils.h -- Utility functions associated with | 
|  | 3 | *	V850E CPUs | 
|  | 4 | * | 
|  | 5 | *  Copyright (C) 2001,02,03  NEC Electronics Corporation | 
|  | 6 | *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org> | 
|  | 7 | * | 
|  | 8 | * This file is subject to the terms and conditions of the GNU General | 
|  | 9 | * Public License.  See the file COPYING in the main directory of this | 
|  | 10 | * archive for more details. | 
|  | 11 | * | 
|  | 12 | * Written by Miles Bader <miles@gnu.org> | 
|  | 13 | */ | 
|  | 14 |  | 
|  | 15 | #include <asm/v850e_utils.h> | 
|  | 16 |  | 
|  | 17 | /* Calculate counter clock-divider and count values to attain the | 
|  | 18 | desired frequency RATE from the base frequency BASE_FREQ.  The | 
|  | 19 | counter is expected to have a clock-divider, which can divide the | 
|  | 20 | system cpu clock by a power of two value from MIN_DIVLOG2 to | 
|  | 21 | MAX_DIV_LOG2, and a word-size of COUNTER_SIZE bits (the counter | 
|  | 22 | counts up and resets whenever it's equal to the compare register, | 
|  | 23 | generating an interrupt or whatever when it does so).  The returned | 
|  | 24 | values are: *DIVLOG2 -- log2 of the desired clock divider and *COUNT | 
|  | 25 | -- the counter compare value to use.  Returns true if it was possible | 
|  | 26 | to find a reasonable value, otherwise false (and the other return | 
|  | 27 | values will be set to be as good as possible).  */ | 
|  | 28 | int calc_counter_params (unsigned long base_freq, | 
|  | 29 | unsigned long rate, | 
|  | 30 | unsigned min_divlog2, unsigned max_divlog2, | 
|  | 31 | unsigned counter_size, | 
|  | 32 | unsigned *divlog2, unsigned *count) | 
|  | 33 | { | 
|  | 34 | unsigned _divlog2; | 
|  | 35 | int ok = 0; | 
|  | 36 |  | 
|  | 37 | /* Find the lowest clock divider setting that can represent RATE.  */ | 
|  | 38 | for (_divlog2 = min_divlog2; _divlog2 <= max_divlog2; _divlog2++) { | 
|  | 39 | /* Minimum interrupt rate possible using this divider.  */ | 
|  | 40 | unsigned min_int_rate | 
|  | 41 | = (base_freq >> _divlog2) >> counter_size; | 
|  | 42 |  | 
|  | 43 | if (min_int_rate <= rate) { | 
|  | 44 | /* This setting is the highest resolution | 
|  | 45 | setting that's slow enough enough to attain | 
|  | 46 | RATE interrupts per second, so use it.  */ | 
|  | 47 | ok = 1; | 
|  | 48 | break; | 
|  | 49 | } | 
|  | 50 | } | 
|  | 51 |  | 
|  | 52 | if (_divlog2 > max_divlog2) | 
|  | 53 | /* Can't find correct setting.  */ | 
|  | 54 | _divlog2 = max_divlog2; | 
|  | 55 |  | 
|  | 56 | if (divlog2) | 
|  | 57 | *divlog2 = _divlog2; | 
|  | 58 | if (count) | 
|  | 59 | *count = ((base_freq >> _divlog2) + rate/2) / rate; | 
|  | 60 |  | 
|  | 61 | return ok; | 
|  | 62 | } |