| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * ######################################################################## |
| 6 | * |
| 7 | * This program is free software; you can distribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License (Version 2) as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 19 | * |
| 20 | * ######################################################################## |
| 21 | * |
| 22 | * Defines for the Malta interrupt controller. |
| 23 | * |
| 24 | */ |
| 25 | #ifndef _MIPS_MALTAINT_H |
| 26 | #define _MIPS_MALTAINT_H |
| 27 | |
| Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 28 | #include <irq.h> |
| 29 | |
| Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 30 | /* |
| 31 | * Interrupts 0..15 are used for Malta ISA compatible interrupts |
| 32 | */ |
| 33 | #define MALTA_INT_BASE 0 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | |
| Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 35 | /* CPU interrupt offsets */ |
| 36 | #define MIPSCPU_INT_SW0 0 |
| 37 | #define MIPSCPU_INT_SW1 1 |
| 38 | #define MIPSCPU_INT_MB0 2 |
| 39 | #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 |
| 40 | #define MIPSCPU_INT_MB1 3 |
| 41 | #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 |
| 42 | #define MIPSCPU_INT_MB2 4 |
| 43 | #define MIPSCPU_INT_MB3 5 |
| 44 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 |
| 45 | #define MIPSCPU_INT_MB4 6 |
| 46 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 |
| Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * Interrupts 64..127 are used for Soc-it Classic interrupts |
| 50 | */ |
| 51 | #define MSC01C_INT_BASE 64 |
| 52 | |
| 53 | /* SOC-it Classic interrupt offsets */ |
| 54 | #define MSC01C_INT_TMR 0 |
| 55 | #define MSC01C_INT_PCI 1 |
| 56 | |
| 57 | /* |
| 58 | * Interrupts 64..127 are used for Soc-it EIC interrupts |
| 59 | */ |
| 60 | #define MSC01E_INT_BASE 64 |
| 61 | |
| 62 | /* SOC-it EIC interrupt offsets */ |
| 63 | #define MSC01E_INT_SW0 1 |
| 64 | #define MSC01E_INT_SW1 2 |
| 65 | #define MSC01E_INT_MB0 3 |
| 66 | #define MSC01E_INT_I8259A MSC01E_INT_MB0 |
| 67 | #define MSC01E_INT_MB1 4 |
| 68 | #define MSC01E_INT_SMI MSC01E_INT_MB1 |
| 69 | #define MSC01E_INT_MB2 5 |
| 70 | #define MSC01E_INT_MB3 6 |
| 71 | #define MSC01E_INT_COREHI MSC01E_INT_MB3 |
| 72 | #define MSC01E_INT_MB4 7 |
| 73 | #define MSC01E_INT_CORELO MSC01E_INT_MB4 |
| 74 | #define MSC01E_INT_TMR 8 |
| 75 | #define MSC01E_INT_PCI 9 |
| 76 | #define MSC01E_INT_PERFCTR 10 |
| 77 | #define MSC01E_INT_CPUCTR 11 |
| 78 | |
| 79 | #ifndef __ASSEMBLY__ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | extern void maltaint_init(void); |
| Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 81 | #endif |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | |
| 83 | #endif /* !(_MIPS_MALTAINT_H) */ |