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review.evervolv.com / android_kernel_htc_msm8960 / ea38f579d57e19bc054aaea4b9a2a9ddad85e9eb / . / arch / powerpc / boot / dts / mpc8569mds.dts
blob: 18fda4917d95e49b87308f54610a61702c1a8590 [file] [log] [blame]
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 pci1 = &pci1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8569@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
Anton Vorontsovea38f572009-05-02 06:16:51 +0400[diff] [blame^]56 reg = <0xe0005000 0x1000>;
57 interrupts = <19 2>;
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]58 interrupt-parent = <&mpic>;
59
60 ranges = <0x0 0x0 0xfe000000 0x02000000
61 0x1 0x0 0xf8000000 0x00008000
62 0x2 0x0 0xf0000000 0x04000000
Anton Vorontsovea38f572009-05-02 06:16:51 +0400[diff] [blame^]63 0x3 0x0 0xfc000000 0x00008000
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]64 0x4 0x0 0xf8008000 0x00008000
65 0x5 0x0 0xf8010000 0x00008000>;
66
67 nor@0,0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x02000000>;
72 bank-width = <2>;
73 device-width = <1>;
74 };
75
76 bcsr@1,0 {
77 compatible = "fsl,mpc8569mds-bcsr";
78 reg = <1 0 0x8000>;
79 };
80
Anton Vorontsovea38f572009-05-02 06:16:51 +0400[diff] [blame^]81 nand@3,0 {
82 compatible = "fsl,mpc8569-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <3 0 0x8000>;
85 };
86
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]87 pib@4,0 {
88 compatible = "fsl,mpc8569mds-pib";
89 reg = <4 0 0x8000>;
90 };
91
92 pib@5,0 {
93 compatible = "fsl,mpc8569mds-pib";
94 reg = <5 0 0x8000>;
95 };
96 };
97
98 soc@e0000000 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 device_type = "soc";
102 compatible = "fsl,mpc8569-immr", "simple-bus";
103 ranges = <0x0 0xe0000000 0x100000>;
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]104 bus-frequency = <0>;
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <10>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <17 2>;
116 interrupt-parent = <&mpic>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,mpc8569-memory-controller";
121 reg = <0x2000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <18 2>;
124 };
125
126 i2c@3000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 cell-index = <0>;
130 compatible = "fsl-i2c";
131 reg = <0x3000 0x100>;
132 interrupts = <43 2>;
133 interrupt-parent = <&mpic>;
134 dfsrr;
135
136 rtc@68 {
137 compatible = "dallas,ds1374";
138 reg = <0x68>;
139 };
140 };
141
142 i2c@3100 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 cell-index = <1>;
146 compatible = "fsl-i2c";
147 reg = <0x3100 0x100>;
148 interrupts = <43 2>;
149 interrupt-parent = <&mpic>;
150 dfsrr;
151 };
152
153 serial0: serial@4500 {
154 cell-index = <0>;
155 device_type = "serial";
156 compatible = "ns16550";
157 reg = <0x4500 0x100>;
158 clock-frequency = <0>;
159 interrupts = <42 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 serial1: serial@4600 {
164 cell-index = <1>;
165 device_type = "serial";
166 compatible = "ns16550";
167 reg = <0x4600 0x100>;
168 clock-frequency = <0>;
169 interrupts = <42 2>;
170 interrupt-parent = <&mpic>;
171 };
172
173 L2: l2-cache-controller@20000 {
174 compatible = "fsl,mpc8569-l2-cache-controller";
175 reg = <0x20000 0x1000>;
176 cache-line-size = <32>; // 32 bytes
177 cache-size = <0x80000>; // L2, 512K
178 interrupt-parent = <&mpic>;
179 interrupts = <16 2>;
180 };
181
182 dma@21300 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
186 reg = <0x21300 0x4>;
187 ranges = <0x0 0x21100 0x200>;
188 cell-index = <0>;
189 dma-channel@0 {
190 compatible = "fsl,mpc8569-dma-channel",
191 "fsl,eloplus-dma-channel";
192 reg = <0x0 0x80>;
193 cell-index = <0>;
194 interrupt-parent = <&mpic>;
195 interrupts = <20 2>;
196 };
197 dma-channel@80 {
198 compatible = "fsl,mpc8569-dma-channel",
199 "fsl,eloplus-dma-channel";
200 reg = <0x80 0x80>;
201 cell-index = <1>;
202 interrupt-parent = <&mpic>;
203 interrupts = <21 2>;
204 };
205 dma-channel@100 {
206 compatible = "fsl,mpc8569-dma-channel",
207 "fsl,eloplus-dma-channel";
208 reg = <0x100 0x80>;
209 cell-index = <2>;
210 interrupt-parent = <&mpic>;
211 interrupts = <22 2>;
212 };
213 dma-channel@180 {
214 compatible = "fsl,mpc8569-dma-channel",
215 "fsl,eloplus-dma-channel";
216 reg = <0x180 0x80>;
217 cell-index = <3>;
218 interrupt-parent = <&mpic>;
219 interrupts = <23 2>;
220 };
221 };
222
223 crypto@30000 {
224 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
225 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
226 reg = <0x30000 0x10000>;
227 interrupts = <45 2 58 2>;
228 interrupt-parent = <&mpic>;
229 fsl,num-channels = <4>;
230 fsl,channel-fifo-len = <24>;
Anton Vorontsovcd7e4a22009-05-02 06:16:49 +0400[diff] [blame]231 fsl,exec-units-mask = <0xbfe>;
Haiying Wang4b3b42b2009-05-01 15:40:50 -0400[diff] [blame]232 fsl,descriptor-types-mask = <0x3ab0ebf>;
233 };
234
235 mpic: pic@40000 {
236 interrupt-controller;
237 #address-cells = <0>;
238 #interrupt-cells = <2>;
239 reg = <0x40000 0x40000>;
240 compatible = "chrp,open-pic";
241 device_type = "open-pic";
242 };
243
244 global-utilities@e0000 {
245 compatible = "fsl,mpc8569-guts";
246 reg = <0xe0000 0x1000>;
247 fsl,has-rstcr;
248 };
249
250 par_io@e0100 {
251 reg = <0xe0100 0x100>;
252 device_type = "par_io";
253 num-ports = <7>;
254
255 pio1: ucc_pin@01 {
256 pio-map = <
257 /* port pin dir open_drain assignment has_irq */
258 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
259 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
260 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
261 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
262 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
263 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
264 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
265 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
266 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
267 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
268 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
269 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
270 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
271 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
272 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
273 };
274
275 pio2: ucc_pin@02 {
276 pio-map = <
277 /* port pin dir open_drain assignment has_irq */
278 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
279 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
280 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
281 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
282 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
283 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
284 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
285 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
286 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
287 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
288 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
289 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
290 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
291 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
292 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
293 };
294
295 pio3: ucc_pin@03 {
296 pio-map = <
297 /* port pin dir open_drain assignment has_irq */
298 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
299 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
300 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
301 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
302 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
303 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
304 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
305 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
306 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
307 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
308 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
309 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
310 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
311 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
312 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
313 };
314
315 pio4: ucc_pin@04 {
316 pio-map = <
317 /* port pin dir open_drain assignment has_irq */
318 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
319 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
320 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
321 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
322 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
323 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
324 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
325 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
326 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
327 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
328 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
329 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
330 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
331 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
332 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
333 };
334 };
335 };
336
337 qe@e0080000 {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 device_type = "qe";
341 compatible = "fsl,qe";
342 ranges = <0x0 0xe0080000 0x40000>;
343 reg = <0xe0080000 0x480>;
344 brg-frequency = <0>;
345 bus-frequency = <0>;
346 fsl,qe-num-riscs = <4>;
347 fsl,qe-num-snums = <46>;
348
349 qeic: interrupt-controller@80 {
350 interrupt-controller;
351 compatible = "fsl,qe-ic";
352 #address-cells = <0>;
353 #interrupt-cells = <1>;
354 reg = <0x80 0x80>;
355 interrupts = <46 2 46 2>; //high:30 low:30
356 interrupt-parent = <&mpic>;
357 };
358
359 spi@4c0 {
360 cell-index = <0>;
361 compatible = "fsl,spi";
362 reg = <0x4c0 0x40>;
363 interrupts = <2>;
364 interrupt-parent = <&qeic>;
365 mode = "cpu";
366 };
367
368 spi@500 {
369 cell-index = <1>;
370 compatible = "fsl,spi";
371 reg = <0x500 0x40>;
372 interrupts = <1>;
373 interrupt-parent = <&qeic>;
374 mode = "cpu";
375 };
376
377 enet0: ucc@2000 {
378 device_type = "network";
379 compatible = "ucc_geth";
380 cell-index = <1>;
381 reg = <0x2000 0x200>;
382 interrupts = <32>;
383 interrupt-parent = <&qeic>;
384 local-mac-address = [ 00 00 00 00 00 00 ];
385 rx-clock-name = "none";
386 tx-clock-name = "clk12";
387 pio-handle = <&pio1>;
388 phy-handle = <&qe_phy0>;
389 phy-connection-type = "rgmii-id";
390 };
391
392 mdio@2120 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 reg = <0x2120 0x18>;
396 compatible = "fsl,ucc-mdio";
397
398 qe_phy0: ethernet-phy@07 {
399 interrupt-parent = <&mpic>;
400 interrupts = <1 1>;
401 reg = <0x7>;
402 device_type = "ethernet-phy";
403 };
404 qe_phy1: ethernet-phy@01 {
405 interrupt-parent = <&mpic>;
406 interrupts = <2 1>;
407 reg = <0x1>;
408 device_type = "ethernet-phy";
409 };
410 qe_phy2: ethernet-phy@02 {
411 interrupt-parent = <&mpic>;
412 interrupts = <3 1>;
413 reg = <0x2>;
414 device_type = "ethernet-phy";
415 };
416 qe_phy3: ethernet-phy@03 {
417 interrupt-parent = <&mpic>;
418 interrupts = <4 1>;
419 reg = <0x3>;
420 device_type = "ethernet-phy";
421 };
422 };
423
424 enet2: ucc@2200 {
425 device_type = "network";
426 compatible = "ucc_geth";
427 cell-index = <3>;
428 reg = <0x2200 0x200>;
429 interrupts = <34>;
430 interrupt-parent = <&qeic>;
431 local-mac-address = [ 00 00 00 00 00 00 ];
432 rx-clock-name = "none";
433 tx-clock-name = "clk12";
434 pio-handle = <&pio3>;
435 phy-handle = <&qe_phy2>;
436 phy-connection-type = "rgmii-id";
437 };
438
439 enet1: ucc@3000 {
440 device_type = "network";
441 compatible = "ucc_geth";
442 cell-index = <2>;
443 reg = <0x3000 0x200>;
444 interrupts = <33>;
445 interrupt-parent = <&qeic>;
446 local-mac-address = [ 00 00 00 00 00 00 ];
447 rx-clock-name = "none";
448 tx-clock-name = "clk17";
449 pio-handle = <&pio2>;
450 phy-handle = <&qe_phy1>;
451 phy-connection-type = "rgmii-id";
452 };
453
454 enet3: ucc@3200 {
455 device_type = "network";
456 compatible = "ucc_geth";
457 cell-index = <4>;
458 reg = <0x3200 0x200>;
459 interrupts = <35>;
460 interrupt-parent = <&qeic>;
461 local-mac-address = [ 00 00 00 00 00 00 ];
462 rx-clock-name = "none";
463 tx-clock-name = "clk17";
464 pio-handle = <&pio4>;
465 phy-handle = <&qe_phy3>;
466 phy-connection-type = "rgmii-id";
467 };
468
469 muram@10000 {
470 #address-cells = <1>;
471 #size-cells = <1>;
472 compatible = "fsl,qe-muram", "fsl,cpm-muram";
473 ranges = <0x0 0x10000 0x20000>;
474
475 data-only@0 {
476 compatible = "fsl,qe-muram-data",
477 "fsl,cpm-muram-data";
478 reg = <0x0 0x20000>;
479 };
480 };
481
482 };
483
484 /* PCI Express */
485 pci1: pcie@e000a000 {
486 compatible = "fsl,mpc8548-pcie";
487 device_type = "pci";
488 #interrupt-cells = <1>;
489 #size-cells = <2>;
490 #address-cells = <3>;
491 reg = <0xe000a000 0x1000>;
492 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
493 interrupt-map = <
494 /* IDSEL 0x0 (PEX) */
495 00000 0x0 0x0 0x1 &mpic 0x0 0x1
496 00000 0x0 0x0 0x2 &mpic 0x1 0x1
497 00000 0x0 0x0 0x3 &mpic 0x2 0x1
498 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
499
500 interrupt-parent = <&mpic>;
501 interrupts = <26 2>;
502 bus-range = <0 255>;
503 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
504 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
505 clock-frequency = <33333333>;
506 pcie@0 {
507 reg = <0x0 0x0 0x0 0x0 0x0>;
508 #size-cells = <2>;
509 #address-cells = <3>;
510 device_type = "pci";
511 ranges = <0x2000000 0x0 0xa0000000
512 0x2000000 0x0 0xa0000000
513 0x0 0x10000000
514
515 0x1000000 0x0 0x0
516 0x1000000 0x0 0x0
517 0x0 0x800000>;
518 };
519 };
520};