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Vladimir Barinov310355c2008-02-18 11:40:22 +01001/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
Vladimir Barinovd6b52032008-09-29 23:14:11 +04004 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
Vladimir Barinov310355c2008-02-18 11:40:22 +01005 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/device.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/clk.h>
18
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/initval.h>
23#include <sound/soc.h>
24
25#include "davinci-pcm.h"
26
David Brownella62114c2009-05-14 12:47:42 -070027
28/*
29 * NOTE: terminology here is confusing.
30 *
31 * - This driver supports the "Audio Serial Port" (ASP),
32 * found on dm6446, dm355, and other DaVinci chips.
33 *
34 * - But it labels it a "Multi-channel Buffered Serial Port"
35 * (McBSP) as on older chips like the dm642 ... which was
36 * backward-compatible, possibly explaining that confusion.
37 *
38 * - OMAP chips have a controller called McBSP, which is
39 * incompatible with the DaVinci flavor of McBSP.
40 *
41 * - Newer DaVinci chips have a controller called McASP,
42 * incompatible with ASP and with either McBSP.
43 *
44 * In short: this uses ASP to implement I2S, not McBSP.
45 * And it won't be the only DaVinci implemention of I2S.
46 */
Vladimir Barinov310355c2008-02-18 11:40:22 +010047#define DAVINCI_MCBSP_DRR_REG 0x00
48#define DAVINCI_MCBSP_DXR_REG 0x04
49#define DAVINCI_MCBSP_SPCR_REG 0x08
50#define DAVINCI_MCBSP_RCR_REG 0x0c
51#define DAVINCI_MCBSP_XCR_REG 0x10
52#define DAVINCI_MCBSP_SRGR_REG 0x14
53#define DAVINCI_MCBSP_PCR_REG 0x24
54
55#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
56#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
57#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
58#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
59#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
60#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
61#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
62
63#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
64#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
65#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
66#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
67
68#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
69#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
70#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
71#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
72#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
73
74#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
75#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
76#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
77
78#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
79#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
80#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
81#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
Hugo Villeneuveb402dff2008-11-08 13:26:09 -050082#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
Vladimir Barinov310355c2008-02-18 11:40:22 +010083#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
84#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
85#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
86#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
87
Vladimir Barinov310355c2008-02-18 11:40:22 +010088enum {
89 DAVINCI_MCBSP_WORD_8 = 0,
90 DAVINCI_MCBSP_WORD_12,
91 DAVINCI_MCBSP_WORD_16,
92 DAVINCI_MCBSP_WORD_20,
93 DAVINCI_MCBSP_WORD_24,
94 DAVINCI_MCBSP_WORD_32,
95};
96
97static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
98 .name = "I2S PCM Stereo out",
99};
100
101static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
102 .name = "I2S PCM Stereo in",
103};
104
105struct davinci_mcbsp_dev {
106 void __iomem *base;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700107 u32 pcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100108 struct clk *clk;
109 struct davinci_pcm_dma_params *dma_params[2];
110};
111
112static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
113 int reg, u32 val)
114{
115 __raw_writel(val, dev->base + reg);
116}
117
118static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
119{
120 return __raw_readl(dev->base + reg);
121}
122
Troy Kiskyc392bec2009-07-04 19:29:52 -0700123static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
124{
125 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
126 /* The clock needs to toggle to complete reset.
127 * So, fake it by toggling the clk polarity.
128 */
129 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
130 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
131}
132
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700133static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
134 struct snd_pcm_substream *substream)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100135{
136 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530137 struct snd_soc_device *socdev = rtd->socdev;
Mark Brown87689d52008-12-02 16:01:14 +0000138 struct snd_soc_platform *platform = socdev->card->platform;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700139 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
Troy Kisky35cf6352009-07-04 19:29:51 -0700140 u32 spcr;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700141 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
Troy Kisky35cf6352009-07-04 19:29:51 -0700142 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700143 if (spcr & mask) {
144 /* start off disabled */
145 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
146 spcr & ~mask);
147 toggle_clock(dev, playback);
148 }
149 /* Start the sample generator and enable transmitter/receiver */
Troy Kisky35cf6352009-07-04 19:29:51 -0700150 spcr |= DAVINCI_MCBSP_SPCR_GRST;
151 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100152
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530153 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
154 /* Stop the DMA to avoid data loss */
155 /* while the transmitter is out of reset to handle XSYNCERR */
156 if (platform->pcm_ops->trigger) {
Troy Kiskyeba575c2009-07-04 19:29:54 -0700157 int ret = platform->pcm_ops->trigger(substream,
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530158 SNDRV_PCM_TRIGGER_STOP);
159 if (ret < 0)
160 printk(KERN_DEBUG "Playback DMA stop failed\n");
161 }
162
163 /* Enable the transmitter */
Troy Kisky35cf6352009-07-04 19:29:51 -0700164 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
165 spcr |= DAVINCI_MCBSP_SPCR_XRST;
166 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530167
168 /* wait for any unexpected frame sync error to occur */
169 udelay(100);
170
171 /* Disable the transmitter to clear any outstanding XSYNCERR */
Troy Kisky35cf6352009-07-04 19:29:51 -0700172 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
173 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
174 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700175 toggle_clock(dev, playback);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530176
177 /* Restart the DMA */
178 if (platform->pcm_ops->trigger) {
Troy Kiskyeba575c2009-07-04 19:29:54 -0700179 int ret = platform->pcm_ops->trigger(substream,
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530180 SNDRV_PCM_TRIGGER_START);
181 if (ret < 0)
182 printk(KERN_DEBUG "Playback DMA start failed\n");
183 }
184 /* Enable the transmitter */
Troy Kisky35cf6352009-07-04 19:29:51 -0700185 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
186 spcr |= DAVINCI_MCBSP_SPCR_XRST;
187 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530188
189 } else {
190
191 /* Enable the reciever */
Troy Kisky35cf6352009-07-04 19:29:51 -0700192 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
193 spcr |= DAVINCI_MCBSP_SPCR_RRST;
194 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530195 }
196
197
Vladimir Barinov310355c2008-02-18 11:40:22 +0100198 /* Start frame sync */
Troy Kisky35cf6352009-07-04 19:29:51 -0700199 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
200 spcr |= DAVINCI_MCBSP_SPCR_FRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100202}
203
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700204static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100205{
Troy Kisky35cf6352009-07-04 19:29:51 -0700206 u32 spcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100207
208 /* Reset transmitter/receiver and sample rate/frame sync generators */
Troy Kisky35cf6352009-07-04 19:29:51 -0700209 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
210 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700211 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
Troy Kisky35cf6352009-07-04 19:29:51 -0700212 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700213 toggle_clock(dev, playback);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100214}
215
Mark Browndee89c42008-11-18 22:11:38 +0000216static int davinci_i2s_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100218{
219 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100220 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100221 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
222
223 cpu_dai->dma_data = dev->dma_params[substream->stream];
224
225 return 0;
226}
227
Troy Kisky21903c12008-12-18 12:36:43 -0700228#define DEFAULT_BITPERSAMPLE 16
229
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100230static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100231 unsigned int fmt)
232{
233 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
Troy Kisky21903c12008-12-18 12:36:43 -0700234 unsigned int pcr;
235 unsigned int srgr;
236 unsigned int rcr;
237 unsigned int xcr;
238 srgr = DAVINCI_MCBSP_SRGR_FSGM |
239 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
240 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100241
242 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
243 case SND_SOC_DAIFMT_CBS_CFS:
Troy Kisky21903c12008-12-18 12:36:43 -0700244 /* cpu is master */
245 pcr = DAVINCI_MCBSP_PCR_FSXM |
246 DAVINCI_MCBSP_PCR_FSRM |
247 DAVINCI_MCBSP_PCR_CLKXM |
248 DAVINCI_MCBSP_PCR_CLKRM;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100249 break;
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500250 case SND_SOC_DAIFMT_CBM_CFS:
251 /* McBSP CLKR pin is the input for the Sample Rate Generator.
252 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
Troy Kisky21903c12008-12-18 12:36:43 -0700253 pcr = DAVINCI_MCBSP_PCR_SCLKME |
254 DAVINCI_MCBSP_PCR_FSXM |
255 DAVINCI_MCBSP_PCR_FSRM;
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500256 break;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100257 case SND_SOC_DAIFMT_CBM_CFM:
Troy Kisky21903c12008-12-18 12:36:43 -0700258 /* codec is master */
259 pcr = 0;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100260 break;
261 default:
Troy Kisky21903c12008-12-18 12:36:43 -0700262 printk(KERN_ERR "%s:bad master\n", __func__);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100263 return -EINVAL;
264 }
265
Troy Kisky69ab8202008-12-18 12:36:44 -0700266 rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
267 xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
268 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Troy Kisky07d8d9d2008-12-19 13:05:24 -0700269 case SND_SOC_DAIFMT_DSP_B:
Troy Kisky69ab8202008-12-18 12:36:44 -0700270 break;
271 case SND_SOC_DAIFMT_I2S:
Troy Kisky07d8d9d2008-12-19 13:05:24 -0700272 /* Davinci doesn't support TRUE I2S, but some codecs will have
273 * the left and right channels contiguous. This allows
274 * dsp_a mode to be used with an inverted normal frame clk.
275 * If your codec is master and does not have contiguous
276 * channels, then you will have sound on only one channel.
277 * Try using a different mode, or codec as slave.
278 *
279 * The TLV320AIC33 is an example of a codec where this works.
280 * It has a variable bit clock frequency allowing it to have
281 * valid data on every bit clock.
282 *
283 * The TLV320AIC23 is an example of a codec where this does not
284 * work. It has a fixed bit clock frequency with progressively
285 * more empty bit clock slots between channels as the sample
286 * rate is lowered.
287 */
288 fmt ^= SND_SOC_DAIFMT_NB_IF;
289 case SND_SOC_DAIFMT_DSP_A:
Troy Kisky69ab8202008-12-18 12:36:44 -0700290 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
291 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
292 break;
293 default:
294 printk(KERN_ERR "%s:bad format\n", __func__);
295 return -EINVAL;
296 }
297
Vladimir Barinov310355c2008-02-18 11:40:22 +0100298 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
Troy Kisky9e031622008-12-19 13:05:23 -0700299 case SND_SOC_DAIFMT_NB_NF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700300 /* CLKRP Receive clock polarity,
301 * 1 - sampled on rising edge of CLKR
302 * valid on rising edge
303 * CLKXP Transmit clock polarity,
304 * 1 - clocked on falling edge of CLKX
305 * valid on rising edge
306 * FSRP Receive frame sync pol, 0 - active high
307 * FSXP Transmit frame sync pol, 0 - active high
308 */
Troy Kisky21903c12008-12-18 12:36:43 -0700309 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100310 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700311 case SND_SOC_DAIFMT_IB_IF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700312 /* CLKRP Receive clock polarity,
313 * 0 - sampled on falling edge of CLKR
314 * valid on falling edge
315 * CLKXP Transmit clock polarity,
316 * 0 - clocked on rising edge of CLKX
317 * valid on falling edge
318 * FSRP Receive frame sync pol, 1 - active low
319 * FSXP Transmit frame sync pol, 1 - active low
320 */
Troy Kisky21903c12008-12-18 12:36:43 -0700321 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100322 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700323 case SND_SOC_DAIFMT_NB_IF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700324 /* CLKRP Receive clock polarity,
325 * 1 - sampled on rising edge of CLKR
326 * valid on rising edge
327 * CLKXP Transmit clock polarity,
328 * 1 - clocked on falling edge of CLKX
329 * valid on rising edge
330 * FSRP Receive frame sync pol, 1 - active low
331 * FSXP Transmit frame sync pol, 1 - active low
332 */
Troy Kisky21903c12008-12-18 12:36:43 -0700333 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
334 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100335 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700336 case SND_SOC_DAIFMT_IB_NF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700337 /* CLKRP Receive clock polarity,
338 * 0 - sampled on falling edge of CLKR
339 * valid on falling edge
340 * CLKXP Transmit clock polarity,
341 * 0 - clocked on rising edge of CLKX
342 * valid on falling edge
343 * FSRP Receive frame sync pol, 0 - active high
344 * FSXP Transmit frame sync pol, 0 - active high
345 */
Vladimir Barinov310355c2008-02-18 11:40:22 +0100346 break;
347 default:
348 return -EINVAL;
349 }
Troy Kisky21903c12008-12-18 12:36:43 -0700350 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700351 dev->pcr = pcr;
Troy Kisky21903c12008-12-18 12:36:43 -0700352 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
353 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
354 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100355 return 0;
356}
357
358static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000359 struct snd_pcm_hw_params *params,
360 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100361{
362 struct snd_soc_pcm_runtime *rtd = substream->private_data;
363 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
364 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
365 struct snd_interval *i = NULL;
366 int mcbsp_word_length;
Troy Kisky35cf6352009-07-04 19:29:51 -0700367 unsigned int rcr, xcr, srgr;
368 u32 spcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100369
370 /* general line settings */
Troy Kisky35cf6352009-07-04 19:29:51 -0700371 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530372 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
Troy Kisky35cf6352009-07-04 19:29:51 -0700373 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
374 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530375 } else {
Troy Kisky35cf6352009-07-04 19:29:51 -0700376 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
377 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530378 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100379
380 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
Troy Kisky35cf6352009-07-04 19:29:51 -0700381 srgr = DAVINCI_MCBSP_SRGR_FSGM;
382 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100383
384 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
Troy Kisky35cf6352009-07-04 19:29:51 -0700385 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
386 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100387
388 /* Determine xfer data type */
389 switch (params_format(params)) {
390 case SNDRV_PCM_FORMAT_S8:
391 dma_params->data_type = 1;
392 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
393 break;
394 case SNDRV_PCM_FORMAT_S16_LE:
395 dma_params->data_type = 2;
396 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
397 break;
398 case SNDRV_PCM_FORMAT_S32_LE:
399 dma_params->data_type = 4;
400 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
401 break;
402 default:
Jean Delvare9b6e12e2008-08-26 15:47:55 +0200403 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
Vladimir Barinov310355c2008-02-18 11:40:22 +0100404 return -EINVAL;
405 }
406
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530407 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
Troy Kisky35cf6352009-07-04 19:29:51 -0700408 rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
409 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
410 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
411 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100412
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530413 } else {
Troy Kisky35cf6352009-07-04 19:29:51 -0700414 xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
415 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
416 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
417 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100418
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530419 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100420 return 0;
421}
422
Mark Browndee89c42008-11-18 22:11:38 +0000423static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
424 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100425{
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700426 struct snd_soc_pcm_runtime *rtd = substream->private_data;
427 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100428 int ret = 0;
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700429 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100430
431 switch (cmd) {
432 case SNDRV_PCM_TRIGGER_START:
433 case SNDRV_PCM_TRIGGER_RESUME:
434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700435 davinci_mcbsp_start(dev, substream);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100436 break;
437 case SNDRV_PCM_TRIGGER_STOP:
438 case SNDRV_PCM_TRIGGER_SUSPEND:
439 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700440 davinci_mcbsp_stop(dev, playback);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100441 break;
442 default:
443 ret = -EINVAL;
444 }
445
446 return ret;
447}
448
Mark Brownbdb92872008-06-11 13:47:10 +0100449static int davinci_i2s_probe(struct platform_device *pdev,
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100450 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100451{
452 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown87506542008-11-18 20:50:34 +0000453 struct snd_soc_card *card = socdev->card;
David Brownella62114c2009-05-14 12:47:42 -0700454 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100455 struct davinci_mcbsp_dev *dev;
456 struct resource *mem, *ioarea;
457 struct evm_snd_platform_data *pdata;
458 int ret;
459
460 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
461 if (!mem) {
462 dev_err(&pdev->dev, "no mem resource?\n");
463 return -ENODEV;
464 }
465
466 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
467 pdev->name);
468 if (!ioarea) {
469 dev_err(&pdev->dev, "McBSP region already claimed\n");
470 return -EBUSY;
471 }
472
473 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
474 if (!dev) {
475 ret = -ENOMEM;
476 goto err_release_region;
477 }
478
479 cpu_dai->private_data = dev;
480
David Brownella62114c2009-05-14 12:47:42 -0700481 dev->clk = clk_get(&pdev->dev, NULL);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100482 if (IS_ERR(dev->clk)) {
483 ret = -ENODEV;
484 goto err_free_mem;
485 }
486 clk_enable(dev->clk);
487
488 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
489 pdata = pdev->dev.platform_data;
490
491 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
492 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
493 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
494 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
495
496 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
497 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
498 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
499 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
500
501 return 0;
502
503err_free_mem:
504 kfree(dev);
505err_release_region:
506 release_mem_region(mem->start, (mem->end - mem->start) + 1);
507
508 return ret;
509}
510
Mark Brownbdb92872008-06-11 13:47:10 +0100511static void davinci_i2s_remove(struct platform_device *pdev,
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100512 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100513{
514 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown87506542008-11-18 20:50:34 +0000515 struct snd_soc_card *card = socdev->card;
David Brownella62114c2009-05-14 12:47:42 -0700516 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100517 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
518 struct resource *mem;
519
520 clk_disable(dev->clk);
521 clk_put(dev->clk);
522 dev->clk = NULL;
523
524 kfree(dev);
525
526 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
527 release_mem_region(mem->start, (mem->end - mem->start) + 1);
528}
529
530#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
531
Eric Miao6335d052009-03-03 09:41:00 +0800532static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
533 .startup = davinci_i2s_startup,
534 .trigger = davinci_i2s_trigger,
535 .hw_params = davinci_i2s_hw_params,
536 .set_fmt = davinci_i2s_set_dai_fmt,
537};
538
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100539struct snd_soc_dai davinci_i2s_dai = {
Vladimir Barinov310355c2008-02-18 11:40:22 +0100540 .name = "davinci-i2s",
541 .id = 0,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100542 .probe = davinci_i2s_probe,
543 .remove = davinci_i2s_remove,
544 .playback = {
545 .channels_min = 2,
546 .channels_max = 2,
547 .rates = DAVINCI_I2S_RATES,
548 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
549 .capture = {
550 .channels_min = 2,
551 .channels_max = 2,
552 .rates = DAVINCI_I2S_RATES,
553 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
Eric Miao6335d052009-03-03 09:41:00 +0800554 .ops = &davinci_i2s_dai_ops,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100555};
556EXPORT_SYMBOL_GPL(davinci_i2s_dai);
557
Takashi Iwaic9b3a402008-12-10 07:47:22 +0100558static int __init davinci_i2s_init(void)
Mark Brown3f4b7832008-12-03 19:26:35 +0000559{
560 return snd_soc_register_dai(&davinci_i2s_dai);
561}
562module_init(davinci_i2s_init);
563
564static void __exit davinci_i2s_exit(void)
565{
566 snd_soc_unregister_dai(&davinci_i2s_dai);
567}
568module_exit(davinci_i2s_exit);
569
Vladimir Barinov310355c2008-02-18 11:40:22 +0100570MODULE_AUTHOR("Vladimir Barinov");
571MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
572MODULE_LICENSE("GPL");