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review.evervolv.com / android_kernel_htc_msm8960 / ed14a3ce9878185ea8348cc2f2e9b53129f84dc7 / . / drivers / video / omap2 / dss / dispc.c
blob: fd8f68e616d0b7a1ff0f0dbd69d71cb41a1ca5ad [file] [log] [blame]
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
Tomi Valkeinenab83b142010-06-09 15:31:01 +0300[diff] [blame]34#include <linux/hardirq.h>
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]35#include <linux/interrupt.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]36
37#include <plat/sram.h>
38#include <plat/clock.h>
39
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +0300[diff] [blame]40#include <video/omapdss.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]41
42#include "dss.h"
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]43#include "dss_features.h"
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]44#include "dispc.h"
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]45
46/* DISPC */
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]47#define DISPC_SZ_REGS SZ_4K
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]48
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]64struct dispc_h_coef {
65 s8 hc4;
66 s8 hc3;
67 u8 hc2;
68 s8 hc1;
69 s8 hc0;
70};
71
72struct dispc_v_coef {
73 s8 vc22;
74 s8 vc2;
75 u8 vc1;
76 s8 vc0;
77 s8 vc00;
78};
79
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]80#define REG_GET(idx, start, end) \
81 FLD_GET(dispc_read_reg(idx), start, end)
82
83#define REG_FLD_MOD(idx, val, start, end) \
84 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
85
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]86struct dispc_irq_stats {
87 unsigned long last_reset;
88 unsigned irq_count;
89 unsigned irqs[32];
90};
91
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]92static struct {
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]93 struct platform_device *pdev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]94 void __iomem *base;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]95 int irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]96
97 u32 fifo_size[3];
98
99 spinlock_t irq_lock;
100 u32 irq_error_mask;
101 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
102 u32 error_irqs;
103 struct work_struct error_work;
104
105 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]106
107#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
108 spinlock_t irq_stats_lock;
109 struct dispc_irq_stats irq_stats;
110#endif
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]111} dispc;
112
113static void _omap_dispc_set_irqs(void);
114
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]115static inline void dispc_write_reg(const u16 idx, u32 val)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]116{
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]117 __raw_writel(val, dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]118}
119
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]120static inline u32 dispc_read_reg(const u16 idx)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]121{
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]122 return __raw_readl(dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]123}
124
125#define SR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]126 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]127#define RR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]128 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]129
130void dispc_save_context(void)
131{
132 if (cpu_is_omap24xx())
133 return;
134
135 SR(SYSCONFIG);
136 SR(IRQENABLE);
137 SR(CONTROL);
138 SR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]139 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
140 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
141 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
142 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]143 SR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]144 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
145 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
146 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
147 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]148 SR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]149 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
150 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]151 if (dss_has_feature(FEAT_MGR_LCD2)) {
152 SR(CONTROL2);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]153 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
154 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
155 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
156 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
157 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
158 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
159 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]160 SR(CONFIG2);
161 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]162
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]163 SR(OVL_BA0(OMAP_DSS_GFX));
164 SR(OVL_BA1(OMAP_DSS_GFX));
165 SR(OVL_POSITION(OMAP_DSS_GFX));
166 SR(OVL_SIZE(OMAP_DSS_GFX));
167 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
168 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
169 SR(OVL_ROW_INC(OMAP_DSS_GFX));
170 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
171 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
172 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]173
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]174 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
175 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
176 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]177
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]178 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
179 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
180 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]181 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]182 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
183 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
184 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]185
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]186 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
187 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
188 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]189 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]190
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]191 SR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]192
193 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]194 SR(OVL_BA0(OMAP_DSS_VIDEO1));
195 SR(OVL_BA1(OMAP_DSS_VIDEO1));
196 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
197 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
198 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
199 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
200 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
201 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
202 SR(OVL_FIR(OMAP_DSS_VIDEO1));
203 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
204 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
205 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]206
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]207 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
208 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
209 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
210 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
211 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
212 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
213 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
214 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]215
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]216 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
217 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
218 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
219 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
220 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
221 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
222 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
223 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]224
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]225 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
226 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
227 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
228 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
229 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]230
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]231 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
232 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
233 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
234 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
235 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
236 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
237 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
238 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]239
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]240 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]241
242 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]243 SR(OVL_BA0(OMAP_DSS_VIDEO2));
244 SR(OVL_BA1(OMAP_DSS_VIDEO2));
245 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
246 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
247 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
248 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
249 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
250 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
251 SR(OVL_FIR(OMAP_DSS_VIDEO2));
252 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
253 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
254 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]255
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]256 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
257 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
258 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
259 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
260 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
261 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
262 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
263 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]264
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]265 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
266 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
267 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
268 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
269 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
270 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
271 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
272 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]273
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]274 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
275 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
276 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
277 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
278 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]279
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]280 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
281 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
282 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
283 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
284 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
285 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
286 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
287 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]288
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]289 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]290
291 if (dss_has_feature(FEAT_CORE_CLK_DIV))
292 SR(DIVISOR);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]293}
294
295void dispc_restore_context(void)
296{
297 RR(SYSCONFIG);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200[diff] [blame]298 /*RR(IRQENABLE);*/
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]299 /*RR(CONTROL);*/
300 RR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]301 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
302 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
303 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
304 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]305 RR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]306 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
307 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
308 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
309 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]310 RR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]311 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
312 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]313 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]314 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
315 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
316 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
317 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
318 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
319 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
320 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]321 RR(CONFIG2);
322 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]323
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]324 RR(OVL_BA0(OMAP_DSS_GFX));
325 RR(OVL_BA1(OMAP_DSS_GFX));
326 RR(OVL_POSITION(OMAP_DSS_GFX));
327 RR(OVL_SIZE(OMAP_DSS_GFX));
328 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
329 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
330 RR(OVL_ROW_INC(OMAP_DSS_GFX));
331 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
332 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
333 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
334
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]335
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]336 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
337 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
338 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]339
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]340 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
341 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
342 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]343 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]344 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
345 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
346 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]347
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]348 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
349 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
350 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]351 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]352
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]353 RR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]354
355 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]356 RR(OVL_BA0(OMAP_DSS_VIDEO1));
357 RR(OVL_BA1(OMAP_DSS_VIDEO1));
358 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
359 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
360 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
361 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
362 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
363 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
364 RR(OVL_FIR(OMAP_DSS_VIDEO1));
365 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
366 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
367 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]368
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]369 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
370 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
371 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
372 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
373 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
374 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
375 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
376 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]377
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]378 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
379 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
380 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
381 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
382 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
383 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
384 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
385 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]386
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]387 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
388 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
389 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
390 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
391 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]392
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]393 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
394 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
395 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
396 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
397 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
398 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
399 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
400 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]401
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]402 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]403
404 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]405 RR(OVL_BA0(OMAP_DSS_VIDEO2));
406 RR(OVL_BA1(OMAP_DSS_VIDEO2));
407 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
408 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
409 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
410 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
411 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
412 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
413 RR(OVL_FIR(OMAP_DSS_VIDEO2));
414 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
415 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
416 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]417
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]418 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
419 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
420 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
421 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
422 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
423 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
424 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
425 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]426
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]427 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
428 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
429 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
430 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
431 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
432 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
433 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
434 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]435
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]436 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
437 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
438 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
439 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
440 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]441
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]442 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
443 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
444 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
445 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
446 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
447 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
448 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
449 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]450
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]451 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]452
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]453 if (dss_has_feature(FEAT_CORE_CLK_DIV))
454 RR(DIVISOR);
455
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]456 /* enable last, because LCD & DIGIT enable are here */
457 RR(CONTROL);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]458 if (dss_has_feature(FEAT_MGR_LCD2))
459 RR(CONTROL2);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200[diff] [blame]460 /* clear spurious SYNC_LOST_DIGIT interrupts */
461 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
462
463 /*
464 * enable last so IRQs won't trigger before
465 * the context is fully restored
466 */
467 RR(IRQENABLE);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]468}
469
470#undef SR
471#undef RR
472
473static inline void enable_clocks(bool enable)
474{
475 if (enable)
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]476 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]477 else
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]478 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]479}
480
481bool dispc_go_busy(enum omap_channel channel)
482{
483 int bit;
484
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]485 if (channel == OMAP_DSS_CHANNEL_LCD ||
486 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]487 bit = 5; /* GOLCD */
488 else
489 bit = 6; /* GODIGIT */
490
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]491 if (channel == OMAP_DSS_CHANNEL_LCD2)
492 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
493 else
494 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]495}
496
497void dispc_go(enum omap_channel channel)
498{
499 int bit;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]500 bool enable_bit, go_bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]501
502 enable_clocks(1);
503
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]504 if (channel == OMAP_DSS_CHANNEL_LCD ||
505 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]506 bit = 0; /* LCDENABLE */
507 else
508 bit = 1; /* DIGITALENABLE */
509
510 /* if the channel is not enabled, we don't need GO */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]511 if (channel == OMAP_DSS_CHANNEL_LCD2)
512 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
513 else
514 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
515
516 if (!enable_bit)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]517 goto end;
518
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]519 if (channel == OMAP_DSS_CHANNEL_LCD ||
520 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]521 bit = 5; /* GOLCD */
522 else
523 bit = 6; /* GODIGIT */
524
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]525 if (channel == OMAP_DSS_CHANNEL_LCD2)
526 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
527 else
528 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
529
530 if (go_bit) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]531 DSSERR("GO bit not down for channel %d\n", channel);
532 goto end;
533 }
534
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]535 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
536 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]537
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]538 if (channel == OMAP_DSS_CHANNEL_LCD2)
539 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
540 else
541 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]542end:
543 enable_clocks(0);
544}
545
546static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
547{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]548 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]549}
550
551static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
552{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]553 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]554}
555
556static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
557{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]558 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]559}
560
561static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
562 int vscaleup, int five_taps)
563{
564 /* Coefficients for horizontal up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]565 static const struct dispc_h_coef coef_hup[8] = {
566 { 0, 0, 128, 0, 0 },
567 { -1, 13, 124, -8, 0 },
568 { -2, 30, 112, -11, -1 },
569 { -5, 51, 95, -11, -2 },
570 { 0, -9, 73, 73, -9 },
571 { -2, -11, 95, 51, -5 },
572 { -1, -11, 112, 30, -2 },
573 { 0, -8, 124, 13, -1 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]574 };
575
576 /* Coefficients for vertical up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]577 static const struct dispc_v_coef coef_vup_3tap[8] = {
578 { 0, 0, 128, 0, 0 },
579 { 0, 3, 123, 2, 0 },
580 { 0, 12, 111, 5, 0 },
581 { 0, 32, 89, 7, 0 },
582 { 0, 0, 64, 64, 0 },
583 { 0, 7, 89, 32, 0 },
584 { 0, 5, 111, 12, 0 },
585 { 0, 2, 123, 3, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]586 };
587
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]588 static const struct dispc_v_coef coef_vup_5tap[8] = {
589 { 0, 0, 128, 0, 0 },
590 { -1, 13, 124, -8, 0 },
591 { -2, 30, 112, -11, -1 },
592 { -5, 51, 95, -11, -2 },
593 { 0, -9, 73, 73, -9 },
594 { -2, -11, 95, 51, -5 },
595 { -1, -11, 112, 30, -2 },
596 { 0, -8, 124, 13, -1 },
597 };
598
599 /* Coefficients for horizontal down-sampling */
600 static const struct dispc_h_coef coef_hdown[8] = {
601 { 0, 36, 56, 36, 0 },
602 { 4, 40, 55, 31, -2 },
603 { 8, 44, 54, 27, -5 },
604 { 12, 48, 53, 22, -7 },
605 { -9, 17, 52, 51, 17 },
606 { -7, 22, 53, 48, 12 },
607 { -5, 27, 54, 44, 8 },
608 { -2, 31, 55, 40, 4 },
609 };
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]610
611 /* Coefficients for vertical down-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]612 static const struct dispc_v_coef coef_vdown_3tap[8] = {
613 { 0, 36, 56, 36, 0 },
614 { 0, 40, 57, 31, 0 },
615 { 0, 45, 56, 27, 0 },
616 { 0, 50, 55, 23, 0 },
617 { 0, 18, 55, 55, 0 },
618 { 0, 23, 55, 50, 0 },
619 { 0, 27, 56, 45, 0 },
620 { 0, 31, 57, 40, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]621 };
622
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]623 static const struct dispc_v_coef coef_vdown_5tap[8] = {
624 { 0, 36, 56, 36, 0 },
625 { 4, 40, 55, 31, -2 },
626 { 8, 44, 54, 27, -5 },
627 { 12, 48, 53, 22, -7 },
628 { -9, 17, 52, 51, 17 },
629 { -7, 22, 53, 48, 12 },
630 { -5, 27, 54, 44, 8 },
631 { -2, 31, 55, 40, 4 },
632 };
633
634 const struct dispc_h_coef *h_coef;
635 const struct dispc_v_coef *v_coef;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]636 int i;
637
638 if (hscaleup)
639 h_coef = coef_hup;
640 else
641 h_coef = coef_hdown;
642
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]643 if (vscaleup)
644 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
645 else
646 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]647
648 for (i = 0; i < 8; i++) {
649 u32 h, hv;
650
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]651 h = FLD_VAL(h_coef[i].hc0, 7, 0)
652 | FLD_VAL(h_coef[i].hc1, 15, 8)
653 | FLD_VAL(h_coef[i].hc2, 23, 16)
654 | FLD_VAL(h_coef[i].hc3, 31, 24);
655 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
656 | FLD_VAL(v_coef[i].vc0, 15, 8)
657 | FLD_VAL(v_coef[i].vc1, 23, 16)
658 | FLD_VAL(v_coef[i].vc2, 31, 24);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]659
660 _dispc_write_firh_reg(plane, i, h);
661 _dispc_write_firhv_reg(plane, i, hv);
662 }
663
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]664 if (five_taps) {
665 for (i = 0; i < 8; i++) {
666 u32 v;
667 v = FLD_VAL(v_coef[i].vc00, 7, 0)
668 | FLD_VAL(v_coef[i].vc22, 15, 8);
669 _dispc_write_firv_reg(plane, i, v);
670 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]671 }
672}
673
674static void _dispc_setup_color_conv_coef(void)
675{
676 const struct color_conv_coef {
677 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
678 int full_range;
679 } ctbl_bt601_5 = {
680 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
681 };
682
683 const struct color_conv_coef *ct;
684
685#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
686
687 ct = &ctbl_bt601_5;
688
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]689 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
690 CVAL(ct->rcr, ct->ry));
691 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
692 CVAL(ct->gy, ct->rcb));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
694 CVAL(ct->gcb, ct->gcr));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
696 CVAL(ct->bcr, ct->by));
697 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
698 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]699
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]700 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
701 CVAL(ct->rcr, ct->ry));
702 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
703 CVAL(ct->gy, ct->rcb));
704 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
705 CVAL(ct->gcb, ct->gcr));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
707 CVAL(ct->bcr, ct->by));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
709 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]710
711#undef CVAL
712
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]713 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
714 ct->full_range, 11, 11);
715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
716 ct->full_range, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]717}
718
719
720static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
721{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]722 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]723}
724
725static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
726{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]727 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]728}
729
730static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
731{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]732 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]733
734 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]735}
736
737static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
738{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]739 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]740
741 if (plane == OMAP_DSS_GFX)
742 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
743 else
744 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]745}
746
747static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
748{
749 u32 val;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]750
751 BUG_ON(plane == OMAP_DSS_GFX);
752
753 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]754
755 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]756}
757
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]758static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
759{
760 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
761 return;
762
763 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
764 plane == OMAP_DSS_VIDEO1)
765 return;
766
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]767 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]768}
769
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]770static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
771{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]772 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]773 return;
774
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]775 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
776 plane == OMAP_DSS_VIDEO1)
777 return;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]778
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]779 if (plane == OMAP_DSS_GFX)
780 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
781 else if (plane == OMAP_DSS_VIDEO2)
782 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
783}
784
785static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
786{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]787 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]788}
789
790static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
791{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]792 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]793}
794
795static void _dispc_set_color_mode(enum omap_plane plane,
796 enum omap_color_mode color_mode)
797{
798 u32 m = 0;
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame]799 if (plane != OMAP_DSS_GFX) {
800 switch (color_mode) {
801 case OMAP_DSS_COLOR_NV12:
802 m = 0x0; break;
803 case OMAP_DSS_COLOR_RGB12U:
804 m = 0x1; break;
805 case OMAP_DSS_COLOR_RGBA16:
806 m = 0x2; break;
807 case OMAP_DSS_COLOR_RGBX16:
808 m = 0x4; break;
809 case OMAP_DSS_COLOR_ARGB16:
810 m = 0x5; break;
811 case OMAP_DSS_COLOR_RGB16:
812 m = 0x6; break;
813 case OMAP_DSS_COLOR_ARGB16_1555:
814 m = 0x7; break;
815 case OMAP_DSS_COLOR_RGB24U:
816 m = 0x8; break;
817 case OMAP_DSS_COLOR_RGB24P:
818 m = 0x9; break;
819 case OMAP_DSS_COLOR_YUV2:
820 m = 0xa; break;
821 case OMAP_DSS_COLOR_UYVY:
822 m = 0xb; break;
823 case OMAP_DSS_COLOR_ARGB32:
824 m = 0xc; break;
825 case OMAP_DSS_COLOR_RGBA32:
826 m = 0xd; break;
827 case OMAP_DSS_COLOR_RGBX32:
828 m = 0xe; break;
829 case OMAP_DSS_COLOR_XRGB16_1555:
830 m = 0xf; break;
831 default:
832 BUG(); break;
833 }
834 } else {
835 switch (color_mode) {
836 case OMAP_DSS_COLOR_CLUT1:
837 m = 0x0; break;
838 case OMAP_DSS_COLOR_CLUT2:
839 m = 0x1; break;
840 case OMAP_DSS_COLOR_CLUT4:
841 m = 0x2; break;
842 case OMAP_DSS_COLOR_CLUT8:
843 m = 0x3; break;
844 case OMAP_DSS_COLOR_RGB12U:
845 m = 0x4; break;
846 case OMAP_DSS_COLOR_ARGB16:
847 m = 0x5; break;
848 case OMAP_DSS_COLOR_RGB16:
849 m = 0x6; break;
850 case OMAP_DSS_COLOR_ARGB16_1555:
851 m = 0x7; break;
852 case OMAP_DSS_COLOR_RGB24U:
853 m = 0x8; break;
854 case OMAP_DSS_COLOR_RGB24P:
855 m = 0x9; break;
856 case OMAP_DSS_COLOR_YUV2:
857 m = 0xa; break;
858 case OMAP_DSS_COLOR_UYVY:
859 m = 0xb; break;
860 case OMAP_DSS_COLOR_ARGB32:
861 m = 0xc; break;
862 case OMAP_DSS_COLOR_RGBA32:
863 m = 0xd; break;
864 case OMAP_DSS_COLOR_RGBX32:
865 m = 0xe; break;
866 case OMAP_DSS_COLOR_XRGB16_1555:
867 m = 0xf; break;
868 default:
869 BUG(); break;
870 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]871 }
872
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]874}
875
876static void _dispc_set_channel_out(enum omap_plane plane,
877 enum omap_channel channel)
878{
879 int shift;
880 u32 val;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]881 int chan = 0, chan2 = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]882
883 switch (plane) {
884 case OMAP_DSS_GFX:
885 shift = 8;
886 break;
887 case OMAP_DSS_VIDEO1:
888 case OMAP_DSS_VIDEO2:
889 shift = 16;
890 break;
891 default:
892 BUG();
893 return;
894 }
895
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]896 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]897 if (dss_has_feature(FEAT_MGR_LCD2)) {
898 switch (channel) {
899 case OMAP_DSS_CHANNEL_LCD:
900 chan = 0;
901 chan2 = 0;
902 break;
903 case OMAP_DSS_CHANNEL_DIGIT:
904 chan = 1;
905 chan2 = 0;
906 break;
907 case OMAP_DSS_CHANNEL_LCD2:
908 chan = 0;
909 chan2 = 1;
910 break;
911 default:
912 BUG();
913 }
914
915 val = FLD_MOD(val, chan, shift, shift);
916 val = FLD_MOD(val, chan2, 31, 30);
917 } else {
918 val = FLD_MOD(val, channel, shift, shift);
919 }
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]920 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]921}
922
923void dispc_set_burst_size(enum omap_plane plane,
924 enum omap_burst_size burst_size)
925{
926 int shift;
927 u32 val;
928
929 enable_clocks(1);
930
931 switch (plane) {
932 case OMAP_DSS_GFX:
933 shift = 6;
934 break;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
937 shift = 14;
938 break;
939 default:
940 BUG();
941 return;
942 }
943
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]944 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]945 val = FLD_MOD(val, burst_size, shift+1, shift);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]946 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]947
948 enable_clocks(0);
949}
950
Mythri P Kd3862612011-03-11 18:02:49 +0530[diff] [blame]951void dispc_enable_gamma_table(bool enable)
952{
953 /*
954 * This is partially implemented to support only disabling of
955 * the gamma table.
956 */
957 if (enable) {
958 DSSWARN("Gamma table enabling for TV not yet supported");
959 return;
960 }
961
962 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
963}
964
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]965static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
966{
967 u32 val;
968
969 BUG_ON(plane == OMAP_DSS_GFX);
970
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]971 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]972 val = FLD_MOD(val, enable, 9, 9);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]973 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]974}
975
976void dispc_enable_replication(enum omap_plane plane, bool enable)
977{
978 int bit;
979
980 if (plane == OMAP_DSS_GFX)
981 bit = 5;
982 else
983 bit = 10;
984
985 enable_clocks(1);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]986 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]987 enable_clocks(0);
988}
989
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]990void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]991{
992 u32 val;
993 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
994 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
995 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]996 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]997 enable_clocks(0);
998}
999
1000void dispc_set_digit_size(u16 width, u16 height)
1001{
1002 u32 val;
1003 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1004 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1005 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]1006 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1007 enable_clocks(0);
1008}
1009
1010static void dispc_read_plane_fifo_sizes(void)
1011{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1012 u32 size;
1013 int plane;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1014 u8 start, end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1015
1016 enable_clocks(1);
1017
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1018 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1019
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1020 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1021 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
1022 start, end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1023 dispc.fifo_size[plane] = size;
1024 }
1025
1026 enable_clocks(0);
1027}
1028
1029u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1030{
1031 return dispc.fifo_size[plane];
1032}
1033
1034void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1035{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1036 u8 hi_start, hi_end, lo_start, lo_end;
1037
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1038 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1039 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1040
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1041 enable_clocks(1);
1042
1043 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1044 plane,
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1045 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1046 lo_start, lo_end),
1047 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1048 hi_start, hi_end),
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1049 low, high);
1050
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1051 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1052 FLD_VAL(high, hi_start, hi_end) |
1053 FLD_VAL(low, lo_start, lo_end));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1054
1055 enable_clocks(0);
1056}
1057
1058void dispc_enable_fifomerge(bool enable)
1059{
1060 enable_clocks(1);
1061
1062 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1063 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1064
1065 enable_clocks(0);
1066}
1067
1068static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1069{
1070 u32 val;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1071 u8 hinc_start, hinc_end, vinc_start, vinc_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1072
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1073 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1074 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1075
1076 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1077 FLD_VAL(hinc, hinc_start, hinc_end);
1078
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1079 dispc_write_reg(DISPC_OVL_FIR(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1080}
1081
1082static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1083{
1084 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1085 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1086
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1087 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1088 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1089
1090 val = FLD_VAL(vaccu, vert_start, vert_end) |
1091 FLD_VAL(haccu, hor_start, hor_end);
1092
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1093 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1094}
1095
1096static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1097{
1098 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1099 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1100
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1101 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1102 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1103
1104 val = FLD_VAL(vaccu, vert_start, vert_end) |
1105 FLD_VAL(haccu, hor_start, hor_end);
1106
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1107 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1108}
1109
1110
1111static void _dispc_set_scaling(enum omap_plane plane,
1112 u16 orig_width, u16 orig_height,
1113 u16 out_width, u16 out_height,
1114 bool ilace, bool five_taps,
1115 bool fieldmode)
1116{
1117 int fir_hinc;
1118 int fir_vinc;
1119 int hscaleup, vscaleup;
1120 int accu0 = 0;
1121 int accu1 = 0;
1122 u32 l;
1123
1124 BUG_ON(plane == OMAP_DSS_GFX);
1125
1126 hscaleup = orig_width <= out_width;
1127 vscaleup = orig_height <= out_height;
1128
1129 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1130
Amber Jained14a3c2011-05-19 19:47:51 +0530[diff] [blame^]1131 fir_hinc = 1024 * orig_width / out_width;
1132 fir_vinc = 1024 * orig_height / out_height;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1133
1134 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1135
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1136 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1137
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1138 /* RESIZEENABLE and VERTICALTAPS */
1139 l &= ~((0x3 << 5) | (0x1 << 21));
Amber Jained14a3c2011-05-19 19:47:51 +0530[diff] [blame^]1140 l |= (orig_width != out_width) ? (1 << 5) : 0;
1141 l |= (orig_height != out_height) ? (1 << 6) : 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1142 l |= five_taps ? (1 << 21) : 0;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1143
1144 /* VRESIZECONF and HRESIZECONF */
1145 if (dss_has_feature(FEAT_RESIZECONF)) {
1146 l &= ~(0x3 << 7);
1147 l |= hscaleup ? 0 : (1 << 7);
1148 l |= vscaleup ? 0 : (1 << 8);
1149 }
1150
1151 /* LINEBUFFERSPLIT */
1152 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1153 l &= ~(0x1 << 22);
1154 l |= five_taps ? (1 << 22) : 0;
1155 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1156
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1157 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1158
1159 /*
1160 * field 0 = even field = bottom field
1161 * field 1 = odd field = top field
1162 */
1163 if (ilace && !fieldmode) {
1164 accu1 = 0;
1165 accu0 = (fir_vinc / 2) & 0x3ff;
1166 if (accu0 >= 1024/2) {
1167 accu1 = 1024/2;
1168 accu0 -= accu1;
1169 }
1170 }
1171
1172 _dispc_set_vid_accu0(plane, 0, accu0);
1173 _dispc_set_vid_accu1(plane, 0, accu1);
1174}
1175
1176static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1177 bool mirroring, enum omap_color_mode color_mode)
1178{
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1179 bool row_repeat = false;
1180 int vidrot = 0;
1181
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1182 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1183 color_mode == OMAP_DSS_COLOR_UYVY) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1184
1185 if (mirroring) {
1186 switch (rotation) {
1187 case OMAP_DSS_ROT_0:
1188 vidrot = 2;
1189 break;
1190 case OMAP_DSS_ROT_90:
1191 vidrot = 1;
1192 break;
1193 case OMAP_DSS_ROT_180:
1194 vidrot = 0;
1195 break;
1196 case OMAP_DSS_ROT_270:
1197 vidrot = 3;
1198 break;
1199 }
1200 } else {
1201 switch (rotation) {
1202 case OMAP_DSS_ROT_0:
1203 vidrot = 0;
1204 break;
1205 case OMAP_DSS_ROT_90:
1206 vidrot = 1;
1207 break;
1208 case OMAP_DSS_ROT_180:
1209 vidrot = 2;
1210 break;
1211 case OMAP_DSS_ROT_270:
1212 vidrot = 3;
1213 break;
1214 }
1215 }
1216
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1217 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1218 row_repeat = true;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1219 else
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1220 row_repeat = false;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1221 }
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1222
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1223 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1224 if (dss_has_feature(FEAT_ROWREPEATENABLE))
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1225 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1226 row_repeat ? 1 : 0, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1227}
1228
1229static int color_mode_to_bpp(enum omap_color_mode color_mode)
1230{
1231 switch (color_mode) {
1232 case OMAP_DSS_COLOR_CLUT1:
1233 return 1;
1234 case OMAP_DSS_COLOR_CLUT2:
1235 return 2;
1236 case OMAP_DSS_COLOR_CLUT4:
1237 return 4;
1238 case OMAP_DSS_COLOR_CLUT8:
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame]1239 case OMAP_DSS_COLOR_NV12:
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1240 return 8;
1241 case OMAP_DSS_COLOR_RGB12U:
1242 case OMAP_DSS_COLOR_RGB16:
1243 case OMAP_DSS_COLOR_ARGB16:
1244 case OMAP_DSS_COLOR_YUV2:
1245 case OMAP_DSS_COLOR_UYVY:
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame]1246 case OMAP_DSS_COLOR_RGBA16:
1247 case OMAP_DSS_COLOR_RGBX16:
1248 case OMAP_DSS_COLOR_ARGB16_1555:
1249 case OMAP_DSS_COLOR_XRGB16_1555:
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1250 return 16;
1251 case OMAP_DSS_COLOR_RGB24P:
1252 return 24;
1253 case OMAP_DSS_COLOR_RGB24U:
1254 case OMAP_DSS_COLOR_ARGB32:
1255 case OMAP_DSS_COLOR_RGBA32:
1256 case OMAP_DSS_COLOR_RGBX32:
1257 return 32;
1258 default:
1259 BUG();
1260 }
1261}
1262
1263static s32 pixinc(int pixels, u8 ps)
1264{
1265 if (pixels == 1)
1266 return 1;
1267 else if (pixels > 1)
1268 return 1 + (pixels - 1) * ps;
1269 else if (pixels < 0)
1270 return 1 - (-pixels + 1) * ps;
1271 else
1272 BUG();
1273}
1274
1275static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1276 u16 screen_width,
1277 u16 width, u16 height,
1278 enum omap_color_mode color_mode, bool fieldmode,
1279 unsigned int field_offset,
1280 unsigned *offset0, unsigned *offset1,
1281 s32 *row_inc, s32 *pix_inc)
1282{
1283 u8 ps;
1284
1285 /* FIXME CLUT formats */
1286 switch (color_mode) {
1287 case OMAP_DSS_COLOR_CLUT1:
1288 case OMAP_DSS_COLOR_CLUT2:
1289 case OMAP_DSS_COLOR_CLUT4:
1290 case OMAP_DSS_COLOR_CLUT8:
1291 BUG();
1292 return;
1293 case OMAP_DSS_COLOR_YUV2:
1294 case OMAP_DSS_COLOR_UYVY:
1295 ps = 4;
1296 break;
1297 default:
1298 ps = color_mode_to_bpp(color_mode) / 8;
1299 break;
1300 }
1301
1302 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1303 width, height);
1304
1305 /*
1306 * field 0 = even field = bottom field
1307 * field 1 = odd field = top field
1308 */
1309 switch (rotation + mirror * 4) {
1310 case OMAP_DSS_ROT_0:
1311 case OMAP_DSS_ROT_180:
1312 /*
1313 * If the pixel format is YUV or UYVY divide the width
1314 * of the image by 2 for 0 and 180 degree rotation.
1315 */
1316 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1317 color_mode == OMAP_DSS_COLOR_UYVY)
1318 width = width >> 1;
1319 case OMAP_DSS_ROT_90:
1320 case OMAP_DSS_ROT_270:
1321 *offset1 = 0;
1322 if (field_offset)
1323 *offset0 = field_offset * screen_width * ps;
1324 else
1325 *offset0 = 0;
1326
1327 *row_inc = pixinc(1 + (screen_width - width) +
1328 (fieldmode ? screen_width : 0),
1329 ps);
1330 *pix_inc = pixinc(1, ps);
1331 break;
1332
1333 case OMAP_DSS_ROT_0 + 4:
1334 case OMAP_DSS_ROT_180 + 4:
1335 /* If the pixel format is YUV or UYVY divide the width
1336 * of the image by 2 for 0 degree and 180 degree
1337 */
1338 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1339 color_mode == OMAP_DSS_COLOR_UYVY)
1340 width = width >> 1;
1341 case OMAP_DSS_ROT_90 + 4:
1342 case OMAP_DSS_ROT_270 + 4:
1343 *offset1 = 0;
1344 if (field_offset)
1345 *offset0 = field_offset * screen_width * ps;
1346 else
1347 *offset0 = 0;
1348 *row_inc = pixinc(1 - (screen_width + width) -
1349 (fieldmode ? screen_width : 0),
1350 ps);
1351 *pix_inc = pixinc(1, ps);
1352 break;
1353
1354 default:
1355 BUG();
1356 }
1357}
1358
1359static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1360 u16 screen_width,
1361 u16 width, u16 height,
1362 enum omap_color_mode color_mode, bool fieldmode,
1363 unsigned int field_offset,
1364 unsigned *offset0, unsigned *offset1,
1365 s32 *row_inc, s32 *pix_inc)
1366{
1367 u8 ps;
1368 u16 fbw, fbh;
1369
1370 /* FIXME CLUT formats */
1371 switch (color_mode) {
1372 case OMAP_DSS_COLOR_CLUT1:
1373 case OMAP_DSS_COLOR_CLUT2:
1374 case OMAP_DSS_COLOR_CLUT4:
1375 case OMAP_DSS_COLOR_CLUT8:
1376 BUG();
1377 return;
1378 default:
1379 ps = color_mode_to_bpp(color_mode) / 8;
1380 break;
1381 }
1382
1383 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1384 width, height);
1385
1386 /* width & height are overlay sizes, convert to fb sizes */
1387
1388 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1389 fbw = width;
1390 fbh = height;
1391 } else {
1392 fbw = height;
1393 fbh = width;
1394 }
1395
1396 /*
1397 * field 0 = even field = bottom field
1398 * field 1 = odd field = top field
1399 */
1400 switch (rotation + mirror * 4) {
1401 case OMAP_DSS_ROT_0:
1402 *offset1 = 0;
1403 if (field_offset)
1404 *offset0 = *offset1 + field_offset * screen_width * ps;
1405 else
1406 *offset0 = *offset1;
1407 *row_inc = pixinc(1 + (screen_width - fbw) +
1408 (fieldmode ? screen_width : 0),
1409 ps);
1410 *pix_inc = pixinc(1, ps);
1411 break;
1412 case OMAP_DSS_ROT_90:
1413 *offset1 = screen_width * (fbh - 1) * ps;
1414 if (field_offset)
1415 *offset0 = *offset1 + field_offset * ps;
1416 else
1417 *offset0 = *offset1;
1418 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1419 (fieldmode ? 1 : 0), ps);
1420 *pix_inc = pixinc(-screen_width, ps);
1421 break;
1422 case OMAP_DSS_ROT_180:
1423 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1424 if (field_offset)
1425 *offset0 = *offset1 - field_offset * screen_width * ps;
1426 else
1427 *offset0 = *offset1;
1428 *row_inc = pixinc(-1 -
1429 (screen_width - fbw) -
1430 (fieldmode ? screen_width : 0),
1431 ps);
1432 *pix_inc = pixinc(-1, ps);
1433 break;
1434 case OMAP_DSS_ROT_270:
1435 *offset1 = (fbw - 1) * ps;
1436 if (field_offset)
1437 *offset0 = *offset1 - field_offset * ps;
1438 else
1439 *offset0 = *offset1;
1440 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1441 (fieldmode ? 1 : 0), ps);
1442 *pix_inc = pixinc(screen_width, ps);
1443 break;
1444
1445 /* mirroring */
1446 case OMAP_DSS_ROT_0 + 4:
1447 *offset1 = (fbw - 1) * ps;
1448 if (field_offset)
1449 *offset0 = *offset1 + field_offset * screen_width * ps;
1450 else
1451 *offset0 = *offset1;
1452 *row_inc = pixinc(screen_width * 2 - 1 +
1453 (fieldmode ? screen_width : 0),
1454 ps);
1455 *pix_inc = pixinc(-1, ps);
1456 break;
1457
1458 case OMAP_DSS_ROT_90 + 4:
1459 *offset1 = 0;
1460 if (field_offset)
1461 *offset0 = *offset1 + field_offset * ps;
1462 else
1463 *offset0 = *offset1;
1464 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1465 (fieldmode ? 1 : 0),
1466 ps);
1467 *pix_inc = pixinc(screen_width, ps);
1468 break;
1469
1470 case OMAP_DSS_ROT_180 + 4:
1471 *offset1 = screen_width * (fbh - 1) * ps;
1472 if (field_offset)
1473 *offset0 = *offset1 - field_offset * screen_width * ps;
1474 else
1475 *offset0 = *offset1;
1476 *row_inc = pixinc(1 - screen_width * 2 -
1477 (fieldmode ? screen_width : 0),
1478 ps);
1479 *pix_inc = pixinc(1, ps);
1480 break;
1481
1482 case OMAP_DSS_ROT_270 + 4:
1483 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1484 if (field_offset)
1485 *offset0 = *offset1 - field_offset * ps;
1486 else
1487 *offset0 = *offset1;
1488 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1489 (fieldmode ? 1 : 0),
1490 ps);
1491 *pix_inc = pixinc(-screen_width, ps);
1492 break;
1493
1494 default:
1495 BUG();
1496 }
1497}
1498
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1499static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1500 u16 height, u16 out_width, u16 out_height,
1501 enum omap_color_mode color_mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1502{
1503 u32 fclk = 0;
1504 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1505 u64 tmp, pclk = dispc_pclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1506
1507 if (height > out_height) {
1508 /* FIXME get real display PPL */
1509 unsigned int ppl = 800;
1510
1511 tmp = pclk * height * out_width;
1512 do_div(tmp, 2 * out_height * ppl);
1513 fclk = tmp;
1514
Ville Syrjälä2d9c5592010-01-08 11:56:41 +0200[diff] [blame]1515 if (height > 2 * out_height) {
1516 if (ppl == out_width)
1517 return 0;
1518
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1519 tmp = pclk * (height - 2 * out_height) * out_width;
1520 do_div(tmp, 2 * out_height * (ppl - out_width));
1521 fclk = max(fclk, (u32) tmp);
1522 }
1523 }
1524
1525 if (width > out_width) {
1526 tmp = pclk * width;
1527 do_div(tmp, out_width);
1528 fclk = max(fclk, (u32) tmp);
1529
1530 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1531 fclk <<= 1;
1532 }
1533
1534 return fclk;
1535}
1536
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1537static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1538 u16 height, u16 out_width, u16 out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1539{
1540 unsigned int hf, vf;
1541
1542 /*
1543 * FIXME how to determine the 'A' factor
1544 * for the no downscaling case ?
1545 */
1546
1547 if (width > 3 * out_width)
1548 hf = 4;
1549 else if (width > 2 * out_width)
1550 hf = 3;
1551 else if (width > out_width)
1552 hf = 2;
1553 else
1554 hf = 1;
1555
1556 if (height > out_height)
1557 vf = 2;
1558 else
1559 vf = 1;
1560
1561 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1562 return dispc_pclk_rate(channel) * vf * hf;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1563}
1564
1565void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1566{
1567 enable_clocks(1);
1568 _dispc_set_channel_out(plane, channel_out);
1569 enable_clocks(0);
1570}
1571
1572static int _dispc_setup_plane(enum omap_plane plane,
1573 u32 paddr, u16 screen_width,
1574 u16 pos_x, u16 pos_y,
1575 u16 width, u16 height,
1576 u16 out_width, u16 out_height,
1577 enum omap_color_mode color_mode,
1578 bool ilace,
1579 enum omap_dss_rotation_type rotation_type,
1580 u8 rotation, int mirror,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1581 u8 global_alpha, u8 pre_mult_alpha,
1582 enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1583{
1584 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1585 bool five_taps = 0;
1586 bool fieldmode = 0;
1587 int cconv = 0;
1588 unsigned offset0, offset1;
1589 s32 row_inc;
1590 s32 pix_inc;
1591 u16 frame_height = height;
1592 unsigned int field_offset = 0;
1593
1594 if (paddr == 0)
1595 return -EINVAL;
1596
1597 if (ilace && height == out_height)
1598 fieldmode = 1;
1599
1600 if (ilace) {
1601 if (fieldmode)
1602 height /= 2;
1603 pos_y /= 2;
1604 out_height /= 2;
1605
1606 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1607 "out_height %d\n",
1608 height, pos_y, out_height);
1609 }
1610
Archit Taneja8dad2ab2010-11-25 17:58:10 +0530[diff] [blame]1611 if (!dss_feat_color_mode_supported(plane, color_mode))
1612 return -EINVAL;
1613
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1614 if (plane == OMAP_DSS_GFX) {
1615 if (width != out_width || height != out_height)
1616 return -EINVAL;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1617 } else {
1618 /* video plane */
1619
1620 unsigned long fclk = 0;
1621
1622 if (out_width < width / maxdownscale ||
1623 out_width > width * 8)
1624 return -EINVAL;
1625
1626 if (out_height < height / maxdownscale ||
1627 out_height > height * 8)
1628 return -EINVAL;
1629
Archit Taneja8dad2ab2010-11-25 17:58:10 +0530[diff] [blame]1630 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1631 color_mode == OMAP_DSS_COLOR_UYVY)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1632 cconv = 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1633
1634 /* Must use 5-tap filter? */
1635 five_taps = height > out_height * 2;
1636
1637 if (!five_taps) {
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1638 fclk = calc_fclk(channel, width, height, out_width,
1639 out_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1640
1641 /* Try 5-tap filter if 3-tap fclk is too high */
1642 if (cpu_is_omap34xx() && height > out_height &&
1643 fclk > dispc_fclk_rate())
1644 five_taps = true;
1645 }
1646
1647 if (width > (2048 >> five_taps)) {
1648 DSSERR("failed to set up scaling, fclk too low\n");
1649 return -EINVAL;
1650 }
1651
1652 if (five_taps)
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1653 fclk = calc_fclk_five_taps(channel, width, height,
1654 out_width, out_height, color_mode);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1655
1656 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1657 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1658
Ville Syrjälä2d9c5592010-01-08 11:56:41 +0200[diff] [blame]1659 if (!fclk || fclk > dispc_fclk_rate()) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1660 DSSERR("failed to set up scaling, "
1661 "required fclk rate = %lu Hz, "
1662 "current fclk rate = %lu Hz\n",
1663 fclk, dispc_fclk_rate());
1664 return -EINVAL;
1665 }
1666 }
1667
1668 if (ilace && !fieldmode) {
1669 /*
1670 * when downscaling the bottom field may have to start several
1671 * source lines below the top field. Unfortunately ACCUI
1672 * registers will only hold the fractional part of the offset
1673 * so the integer part must be added to the base address of the
1674 * bottom field.
1675 */
1676 if (!height || height == out_height)
1677 field_offset = 0;
1678 else
1679 field_offset = height / out_height / 2;
1680 }
1681
1682 /* Fields are independent but interleaved in memory. */
1683 if (fieldmode)
1684 field_offset = 1;
1685
1686 if (rotation_type == OMAP_DSS_ROT_DMA)
1687 calc_dma_rotation_offset(rotation, mirror,
1688 screen_width, width, frame_height, color_mode,
1689 fieldmode, field_offset,
1690 &offset0, &offset1, &row_inc, &pix_inc);
1691 else
1692 calc_vrfb_rotation_offset(rotation, mirror,
1693 screen_width, width, frame_height, color_mode,
1694 fieldmode, field_offset,
1695 &offset0, &offset1, &row_inc, &pix_inc);
1696
1697 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1698 offset0, offset1, row_inc, pix_inc);
1699
1700 _dispc_set_color_mode(plane, color_mode);
1701
1702 _dispc_set_plane_ba0(plane, paddr + offset0);
1703 _dispc_set_plane_ba1(plane, paddr + offset1);
1704
1705 _dispc_set_row_inc(plane, row_inc);
1706 _dispc_set_pix_inc(plane, pix_inc);
1707
1708 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1709 out_width, out_height);
1710
1711 _dispc_set_plane_pos(plane, pos_x, pos_y);
1712
1713 _dispc_set_pic_size(plane, width, height);
1714
1715 if (plane != OMAP_DSS_GFX) {
1716 _dispc_set_scaling(plane, width, height,
1717 out_width, out_height,
1718 ilace, five_taps, fieldmode);
1719 _dispc_set_vid_size(plane, out_width, out_height);
1720 _dispc_set_vid_color_conv(plane, cconv);
1721 }
1722
1723 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1724
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]1725 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1726 _dispc_setup_global_alpha(plane, global_alpha);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1727
1728 return 0;
1729}
1730
1731static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1732{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1733 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1734}
1735
1736static void dispc_disable_isr(void *data, u32 mask)
1737{
1738 struct completion *compl = data;
1739 complete(compl);
1740}
1741
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1742static void _enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1743{
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1744 if (channel == OMAP_DSS_CHANNEL_LCD2)
1745 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1746 else
1747 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1748}
1749
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1750static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1751{
1752 struct completion frame_done_completion;
1753 bool is_on;
1754 int r;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1755 u32 irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1756
1757 enable_clocks(1);
1758
1759 /* When we disable LCD output, we need to wait until frame is done.
1760 * Otherwise the DSS is still working, and turning off the clocks
1761 * prevents DSS from going to OFF mode */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1762 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1763 REG_GET(DISPC_CONTROL2, 0, 0) :
1764 REG_GET(DISPC_CONTROL, 0, 0);
1765
1766 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1767 DISPC_IRQ_FRAMEDONE;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1768
1769 if (!enable && is_on) {
1770 init_completion(&frame_done_completion);
1771
1772 r = omap_dispc_register_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1773 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1774
1775 if (r)
1776 DSSERR("failed to register FRAMEDONE isr\n");
1777 }
1778
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1779 _enable_lcd_out(channel, enable);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1780
1781 if (!enable && is_on) {
1782 if (!wait_for_completion_timeout(&frame_done_completion,
1783 msecs_to_jiffies(100)))
1784 DSSERR("timeout waiting for FRAME DONE\n");
1785
1786 r = omap_dispc_unregister_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1787 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1788
1789 if (r)
1790 DSSERR("failed to unregister FRAMEDONE isr\n");
1791 }
1792
1793 enable_clocks(0);
1794}
1795
1796static void _enable_digit_out(bool enable)
1797{
1798 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1799}
1800
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1801static void dispc_enable_digit_out(bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1802{
1803 struct completion frame_done_completion;
1804 int r;
1805
1806 enable_clocks(1);
1807
1808 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1809 enable_clocks(0);
1810 return;
1811 }
1812
1813 if (enable) {
1814 unsigned long flags;
1815 /* When we enable digit output, we'll get an extra digit
1816 * sync lost interrupt, that we need to ignore */
1817 spin_lock_irqsave(&dispc.irq_lock, flags);
1818 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1819 _omap_dispc_set_irqs();
1820 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1821 }
1822
1823 /* When we disable digit output, we need to wait until fields are done.
1824 * Otherwise the DSS is still working, and turning off the clocks
1825 * prevents DSS from going to OFF mode. And when enabling, we need to
1826 * wait for the extra sync losts */
1827 init_completion(&frame_done_completion);
1828
1829 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1830 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1831 if (r)
1832 DSSERR("failed to register EVSYNC isr\n");
1833
1834 _enable_digit_out(enable);
1835
1836 /* XXX I understand from TRM that we should only wait for the
1837 * current field to complete. But it seems we have to wait
1838 * for both fields */
1839 if (!wait_for_completion_timeout(&frame_done_completion,
1840 msecs_to_jiffies(100)))
1841 DSSERR("timeout waiting for EVSYNC\n");
1842
1843 if (!wait_for_completion_timeout(&frame_done_completion,
1844 msecs_to_jiffies(100)))
1845 DSSERR("timeout waiting for EVSYNC\n");
1846
1847 r = omap_dispc_unregister_isr(dispc_disable_isr,
1848 &frame_done_completion,
1849 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1850 if (r)
1851 DSSERR("failed to unregister EVSYNC isr\n");
1852
1853 if (enable) {
1854 unsigned long flags;
1855 spin_lock_irqsave(&dispc.irq_lock, flags);
1856 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1857 if (dss_has_feature(FEAT_MGR_LCD2))
1858 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1859 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1860 _omap_dispc_set_irqs();
1861 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1862 }
1863
1864 enable_clocks(0);
1865}
1866
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1867bool dispc_is_channel_enabled(enum omap_channel channel)
1868{
1869 if (channel == OMAP_DSS_CHANNEL_LCD)
1870 return !!REG_GET(DISPC_CONTROL, 0, 0);
1871 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1872 return !!REG_GET(DISPC_CONTROL, 1, 1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1873 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1874 return !!REG_GET(DISPC_CONTROL2, 0, 0);
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1875 else
1876 BUG();
1877}
1878
1879void dispc_enable_channel(enum omap_channel channel, bool enable)
1880{
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1881 if (channel == OMAP_DSS_CHANNEL_LCD ||
1882 channel == OMAP_DSS_CHANNEL_LCD2)
1883 dispc_enable_lcd_out(channel, enable);
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1884 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1885 dispc_enable_digit_out(enable);
1886 else
1887 BUG();
1888}
1889
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1890void dispc_lcd_enable_signal_polarity(bool act_high)
1891{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1892 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1893 return;
1894
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1895 enable_clocks(1);
1896 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1897 enable_clocks(0);
1898}
1899
1900void dispc_lcd_enable_signal(bool enable)
1901{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1902 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1903 return;
1904
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1905 enable_clocks(1);
1906 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1907 enable_clocks(0);
1908}
1909
1910void dispc_pck_free_enable(bool enable)
1911{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1912 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1913 return;
1914
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1915 enable_clocks(1);
1916 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1917 enable_clocks(0);
1918}
1919
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]1920void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1921{
1922 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1923 if (channel == OMAP_DSS_CHANNEL_LCD2)
1924 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1925 else
1926 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1927 enable_clocks(0);
1928}
1929
1930
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]1931void dispc_set_lcd_display_type(enum omap_channel channel,
1932 enum omap_lcd_display_type type)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1933{
1934 int mode;
1935
1936 switch (type) {
1937 case OMAP_DSS_LCD_DISPLAY_STN:
1938 mode = 0;
1939 break;
1940
1941 case OMAP_DSS_LCD_DISPLAY_TFT:
1942 mode = 1;
1943 break;
1944
1945 default:
1946 BUG();
1947 return;
1948 }
1949
1950 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1951 if (channel == OMAP_DSS_CHANNEL_LCD2)
1952 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1953 else
1954 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1955 enable_clocks(0);
1956}
1957
1958void dispc_set_loadmode(enum omap_dss_load_mode mode)
1959{
1960 enable_clocks(1);
1961 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1962 enable_clocks(0);
1963}
1964
1965
1966void dispc_set_default_color(enum omap_channel channel, u32 color)
1967{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1968 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]1969 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1970 enable_clocks(0);
1971}
1972
1973u32 dispc_get_default_color(enum omap_channel channel)
1974{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1975 u32 l;
1976
1977 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1978 channel != OMAP_DSS_CHANNEL_LCD &&
1979 channel != OMAP_DSS_CHANNEL_LCD2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1980
1981 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]1982 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1983 enable_clocks(0);
1984
1985 return l;
1986}
1987
1988void dispc_set_trans_key(enum omap_channel ch,
1989 enum omap_dss_trans_key_type type,
1990 u32 trans_key)
1991{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1992 enable_clocks(1);
1993 if (ch == OMAP_DSS_CHANNEL_LCD)
1994 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1995 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1996 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1997 else /* OMAP_DSS_CHANNEL_LCD2 */
1998 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1999
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]2000 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2001 enable_clocks(0);
2002}
2003
2004void dispc_get_trans_key(enum omap_channel ch,
2005 enum omap_dss_trans_key_type *type,
2006 u32 *trans_key)
2007{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2008 enable_clocks(1);
2009 if (type) {
2010 if (ch == OMAP_DSS_CHANNEL_LCD)
2011 *type = REG_GET(DISPC_CONFIG, 11, 11);
2012 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2013 *type = REG_GET(DISPC_CONFIG, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2014 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2015 *type = REG_GET(DISPC_CONFIG2, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2016 else
2017 BUG();
2018 }
2019
2020 if (trans_key)
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]2021 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2022 enable_clocks(0);
2023}
2024
2025void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2026{
2027 enable_clocks(1);
2028 if (ch == OMAP_DSS_CHANNEL_LCD)
2029 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2030 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2031 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2032 else /* OMAP_DSS_CHANNEL_LCD2 */
2033 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2034 enable_clocks(0);
2035}
2036void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2037{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]2038 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2039 return;
2040
2041 enable_clocks(1);
2042 if (ch == OMAP_DSS_CHANNEL_LCD)
2043 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2044 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2045 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2046 else /* OMAP_DSS_CHANNEL_LCD2 */
2047 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2048 enable_clocks(0);
2049}
2050bool dispc_alpha_blending_enabled(enum omap_channel ch)
2051{
2052 bool enabled;
2053
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]2054 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2055 return false;
2056
2057 enable_clocks(1);
2058 if (ch == OMAP_DSS_CHANNEL_LCD)
2059 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2060 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Archit Taneja712247a2010-11-08 12:56:21 +0100[diff] [blame]2061 enabled = REG_GET(DISPC_CONFIG, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2062 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2063 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2064 else
2065 BUG();
2066 enable_clocks(0);
2067
2068 return enabled;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2069}
2070
2071
2072bool dispc_trans_key_enabled(enum omap_channel ch)
2073{
2074 bool enabled;
2075
2076 enable_clocks(1);
2077 if (ch == OMAP_DSS_CHANNEL_LCD)
2078 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2079 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2080 enabled = REG_GET(DISPC_CONFIG, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2081 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2082 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2083 else
2084 BUG();
2085 enable_clocks(0);
2086
2087 return enabled;
2088}
2089
2090
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2091void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2092{
2093 int code;
2094
2095 switch (data_lines) {
2096 case 12:
2097 code = 0;
2098 break;
2099 case 16:
2100 code = 1;
2101 break;
2102 case 18:
2103 code = 2;
2104 break;
2105 case 24:
2106 code = 3;
2107 break;
2108 default:
2109 BUG();
2110 return;
2111 }
2112
2113 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2114 if (channel == OMAP_DSS_CHANNEL_LCD2)
2115 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2116 else
2117 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2118 enable_clocks(0);
2119}
2120
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2121void dispc_set_parallel_interface_mode(enum omap_channel channel,
2122 enum omap_parallel_interface_mode mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2123{
2124 u32 l;
2125 int stallmode;
2126 int gpout0 = 1;
2127 int gpout1;
2128
2129 switch (mode) {
2130 case OMAP_DSS_PARALLELMODE_BYPASS:
2131 stallmode = 0;
2132 gpout1 = 1;
2133 break;
2134
2135 case OMAP_DSS_PARALLELMODE_RFBI:
2136 stallmode = 1;
2137 gpout1 = 0;
2138 break;
2139
2140 case OMAP_DSS_PARALLELMODE_DSI:
2141 stallmode = 1;
2142 gpout1 = 1;
2143 break;
2144
2145 default:
2146 BUG();
2147 return;
2148 }
2149
2150 enable_clocks(1);
2151
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2152 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2153 l = dispc_read_reg(DISPC_CONTROL2);
2154 l = FLD_MOD(l, stallmode, 11, 11);
2155 dispc_write_reg(DISPC_CONTROL2, l);
2156 } else {
2157 l = dispc_read_reg(DISPC_CONTROL);
2158 l = FLD_MOD(l, stallmode, 11, 11);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2159 l = FLD_MOD(l, gpout0, 15, 15);
2160 l = FLD_MOD(l, gpout1, 16, 16);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2161 dispc_write_reg(DISPC_CONTROL, l);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2162 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2163
2164 enable_clocks(0);
2165}
2166
2167static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2168 int vsw, int vfp, int vbp)
2169{
2170 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2171 if (hsw < 1 || hsw > 64 ||
2172 hfp < 1 || hfp > 256 ||
2173 hbp < 1 || hbp > 256 ||
2174 vsw < 1 || vsw > 64 ||
2175 vfp < 0 || vfp > 255 ||
2176 vbp < 0 || vbp > 255)
2177 return false;
2178 } else {
2179 if (hsw < 1 || hsw > 256 ||
2180 hfp < 1 || hfp > 4096 ||
2181 hbp < 1 || hbp > 4096 ||
2182 vsw < 1 || vsw > 256 ||
2183 vfp < 0 || vfp > 4095 ||
2184 vbp < 0 || vbp > 4095)
2185 return false;
2186 }
2187
2188 return true;
2189}
2190
2191bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2192{
2193 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2194 timings->hbp, timings->vsw,
2195 timings->vfp, timings->vbp);
2196}
2197
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2198static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2199 int hfp, int hbp, int vsw, int vfp, int vbp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2200{
2201 u32 timing_h, timing_v;
2202
2203 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2204 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2205 FLD_VAL(hbp-1, 27, 20);
2206
2207 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2208 FLD_VAL(vbp, 27, 20);
2209 } else {
2210 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2211 FLD_VAL(hbp-1, 31, 20);
2212
2213 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2214 FLD_VAL(vbp, 31, 20);
2215 }
2216
2217 enable_clocks(1);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2218 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2219 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2220 enable_clocks(0);
2221}
2222
2223/* change name to mode? */
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2224void dispc_set_lcd_timings(enum omap_channel channel,
2225 struct omap_video_timings *timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2226{
2227 unsigned xtot, ytot;
2228 unsigned long ht, vt;
2229
2230 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2231 timings->hbp, timings->vsw,
2232 timings->vfp, timings->vbp))
2233 BUG();
2234
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2235 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2236 timings->hbp, timings->vsw, timings->vfp,
2237 timings->vbp);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2238
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2239 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2240
2241 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2242 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2243
2244 ht = (timings->pixel_clock * 1000) / xtot;
2245 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2246
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2247 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2248 timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2249 DSSDBG("pck %u\n", timings->pixel_clock);
2250 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2251 timings->hsw, timings->hfp, timings->hbp,
2252 timings->vsw, timings->vfp, timings->vbp);
2253
2254 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2255}
2256
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2257static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2258 u16 pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2259{
2260 BUG_ON(lck_div < 1);
2261 BUG_ON(pck_div < 2);
2262
2263 enable_clocks(1);
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2264 dispc_write_reg(DISPC_DIVISORo(channel),
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2265 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2266 enable_clocks(0);
2267}
2268
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2269static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2270 int *pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2271{
2272 u32 l;
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2273 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2274 *lck_div = FLD_GET(l, 23, 16);
2275 *pck_div = FLD_GET(l, 7, 0);
2276}
2277
2278unsigned long dispc_fclk_rate(void)
2279{
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2280 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2281 unsigned long r = 0;
2282
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2283 switch (dss_get_dispc_clk_source()) {
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2284 case OMAP_DSS_CLK_SRC_FCK:
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2285 r = dss_clk_get_rate(DSS_CLK_FCK);
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2286 break;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2287 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2288 dsidev = dsi_get_dsidev_from_id(0);
2289 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2290 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +0530[diff] [blame]2291 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2292 dsidev = dsi_get_dsidev_from_id(1);
2293 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2294 break;
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2295 default:
2296 BUG();
2297 }
2298
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2299 return r;
2300}
2301
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2302unsigned long dispc_lclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2303{
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2304 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2305 int lcd;
2306 unsigned long r;
2307 u32 l;
2308
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2309 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2310
2311 lcd = FLD_GET(l, 23, 16);
2312
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2313 switch (dss_get_lcd_clk_source(channel)) {
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2314 case OMAP_DSS_CLK_SRC_FCK:
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2315 r = dss_clk_get_rate(DSS_CLK_FCK);
2316 break;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2317 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2318 dsidev = dsi_get_dsidev_from_id(0);
2319 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2320 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +0530[diff] [blame]2321 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2322 dsidev = dsi_get_dsidev_from_id(1);
2323 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2324 break;
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2325 default:
2326 BUG();
2327 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2328
2329 return r / lcd;
2330}
2331
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2332unsigned long dispc_pclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2333{
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2334 int pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2335 unsigned long r;
2336 u32 l;
2337
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2338 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2339
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2340 pcd = FLD_GET(l, 7, 0);
2341
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2342 r = dispc_lclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2343
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2344 return r / pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2345}
2346
2347void dispc_dump_clocks(struct seq_file *s)
2348{
2349 int lcd, pcd;
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]2350 u32 l;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2351 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2352 enum omap_dss_clk_source lcd_clk_src;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2353
2354 enable_clocks(1);
2355
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2356 seq_printf(s, "- DISPC -\n");
2357
Archit Taneja067a57e2011-03-02 11:57:25 +0530[diff] [blame]2358 seq_printf(s, "dispc fclk source = %s (%s)\n",
2359 dss_get_generic_clk_source_name(dispc_clk_src),
2360 dss_feat_get_clk_source_name(dispc_clk_src));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2361
2362 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2363
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]2364 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2365 seq_printf(s, "- DISPC-CORE-CLK -\n");
2366 l = dispc_read_reg(DISPC_DIVISOR);
2367 lcd = FLD_GET(l, 23, 16);
2368
2369 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2370 (dispc_fclk_rate()/lcd), lcd);
2371 }
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2372 seq_printf(s, "- LCD1 -\n");
2373
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2374 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2375
2376 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2377 dss_get_generic_clk_source_name(lcd_clk_src),
2378 dss_feat_get_clk_source_name(lcd_clk_src));
2379
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2380 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2381
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2382 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2383 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2384 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2385 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2386 if (dss_has_feature(FEAT_MGR_LCD2)) {
2387 seq_printf(s, "- LCD2 -\n");
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2388
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2389 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2390
2391 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2392 dss_get_generic_clk_source_name(lcd_clk_src),
2393 dss_feat_get_clk_source_name(lcd_clk_src));
2394
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2395 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2396
2397 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2398 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2399 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2400 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2401 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2402 enable_clocks(0);
2403}
2404
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2405#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2406void dispc_dump_irqs(struct seq_file *s)
2407{
2408 unsigned long flags;
2409 struct dispc_irq_stats stats;
2410
2411 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2412
2413 stats = dispc.irq_stats;
2414 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2415 dispc.irq_stats.last_reset = jiffies;
2416
2417 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2418
2419 seq_printf(s, "period %u ms\n",
2420 jiffies_to_msecs(jiffies - stats.last_reset));
2421
2422 seq_printf(s, "irqs %d\n", stats.irq_count);
2423#define PIS(x) \
2424 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2425
2426 PIS(FRAMEDONE);
2427 PIS(VSYNC);
2428 PIS(EVSYNC_EVEN);
2429 PIS(EVSYNC_ODD);
2430 PIS(ACBIAS_COUNT_STAT);
2431 PIS(PROG_LINE_NUM);
2432 PIS(GFX_FIFO_UNDERFLOW);
2433 PIS(GFX_END_WIN);
2434 PIS(PAL_GAMMA_MASK);
2435 PIS(OCP_ERR);
2436 PIS(VID1_FIFO_UNDERFLOW);
2437 PIS(VID1_END_WIN);
2438 PIS(VID2_FIFO_UNDERFLOW);
2439 PIS(VID2_END_WIN);
2440 PIS(SYNC_LOST);
2441 PIS(SYNC_LOST_DIGIT);
2442 PIS(WAKEUP);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2443 if (dss_has_feature(FEAT_MGR_LCD2)) {
2444 PIS(FRAMEDONE2);
2445 PIS(VSYNC2);
2446 PIS(ACBIAS_COUNT_STAT2);
2447 PIS(SYNC_LOST2);
2448 }
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2449#undef PIS
2450}
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2451#endif
2452
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2453void dispc_dump_regs(struct seq_file *s)
2454{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2455#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2456
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2457 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2458
2459 DUMPREG(DISPC_REVISION);
2460 DUMPREG(DISPC_SYSCONFIG);
2461 DUMPREG(DISPC_SYSSTATUS);
2462 DUMPREG(DISPC_IRQSTATUS);
2463 DUMPREG(DISPC_IRQENABLE);
2464 DUMPREG(DISPC_CONTROL);
2465 DUMPREG(DISPC_CONFIG);
2466 DUMPREG(DISPC_CAPABLE);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2467 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2468 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2469 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2470 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2471 DUMPREG(DISPC_LINE_STATUS);
2472 DUMPREG(DISPC_LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2473 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2474 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2475 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2476 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2477 DUMPREG(DISPC_GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2478 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2479 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2480 if (dss_has_feature(FEAT_MGR_LCD2)) {
2481 DUMPREG(DISPC_CONTROL2);
2482 DUMPREG(DISPC_CONFIG2);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2483 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2484 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2485 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2486 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2487 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2488 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2489 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2490 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2491
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2492 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2493 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2494 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2495 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2496 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2497 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2498 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2499 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2500 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2501 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2502 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2503
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2504 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2505 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2506 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2507
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2508 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2509 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2510 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2511 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2512 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2513 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2514 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2515
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2516 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2517 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2518 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2519 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2520
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2521 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2522
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2523 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2524 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2525 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2526 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2527 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2528 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2529 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2530 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2531 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2532 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2533 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2534 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2535 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2536
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2537 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2538 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2539 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2540 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2541 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2542 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2543 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2544 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2545 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2546 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2547 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2548 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2549 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2550
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2551 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2552 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2553 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2554 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2555 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2556 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2557 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2558 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2559 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2560 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2561 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2562 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2563 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2564 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2565 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2566 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2567 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2568 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2569 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2570 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2571 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2572 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2573 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2574 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2575 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2576 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2577 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2578 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2579 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2580
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2581 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2582 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2583 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2584 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2585 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2586 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2587 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2588 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2589 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2590 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2591 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2592 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2593 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2594 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2595 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2596 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2597 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2598 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2599 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2600 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2601 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2602 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2603 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2604 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2605 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2606 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2607 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2608 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2609 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2610
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2611 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2612 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2613
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2614 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2615#undef DUMPREG
2616}
2617
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2618static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2619 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2620{
2621 u32 l = 0;
2622
2623 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2624 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2625
2626 l |= FLD_VAL(onoff, 17, 17);
2627 l |= FLD_VAL(rf, 16, 16);
2628 l |= FLD_VAL(ieo, 15, 15);
2629 l |= FLD_VAL(ipc, 14, 14);
2630 l |= FLD_VAL(ihs, 13, 13);
2631 l |= FLD_VAL(ivs, 12, 12);
2632 l |= FLD_VAL(acbi, 11, 8);
2633 l |= FLD_VAL(acb, 7, 0);
2634
2635 enable_clocks(1);
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2636 dispc_write_reg(DISPC_POL_FREQ(channel), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2637 enable_clocks(0);
2638}
2639
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2640void dispc_set_pol_freq(enum omap_channel channel,
2641 enum omap_panel_config config, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2642{
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2643 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2644 (config & OMAP_DSS_LCD_RF) != 0,
2645 (config & OMAP_DSS_LCD_IEO) != 0,
2646 (config & OMAP_DSS_LCD_IPC) != 0,
2647 (config & OMAP_DSS_LCD_IHS) != 0,
2648 (config & OMAP_DSS_LCD_IVS) != 0,
2649 acbi, acb);
2650}
2651
2652/* with fck as input clock rate, find dispc dividers that produce req_pck */
2653void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2654 struct dispc_clock_info *cinfo)
2655{
2656 u16 pcd_min = is_tft ? 2 : 3;
2657 unsigned long best_pck;
2658 u16 best_ld, cur_ld;
2659 u16 best_pd, cur_pd;
2660
2661 best_pck = 0;
2662 best_ld = 0;
2663 best_pd = 0;
2664
2665 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2666 unsigned long lck = fck / cur_ld;
2667
2668 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2669 unsigned long pck = lck / cur_pd;
2670 long old_delta = abs(best_pck - req_pck);
2671 long new_delta = abs(pck - req_pck);
2672
2673 if (best_pck == 0 || new_delta < old_delta) {
2674 best_pck = pck;
2675 best_ld = cur_ld;
2676 best_pd = cur_pd;
2677
2678 if (pck == req_pck)
2679 goto found;
2680 }
2681
2682 if (pck < req_pck)
2683 break;
2684 }
2685
2686 if (lck / pcd_min < req_pck)
2687 break;
2688 }
2689
2690found:
2691 cinfo->lck_div = best_ld;
2692 cinfo->pck_div = best_pd;
2693 cinfo->lck = fck / cinfo->lck_div;
2694 cinfo->pck = cinfo->lck / cinfo->pck_div;
2695}
2696
2697/* calculate clock rates using dividers in cinfo */
2698int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2699 struct dispc_clock_info *cinfo)
2700{
2701 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2702 return -EINVAL;
2703 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2704 return -EINVAL;
2705
2706 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2707 cinfo->pck = cinfo->lck / cinfo->pck_div;
2708
2709 return 0;
2710}
2711
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2712int dispc_set_clock_div(enum omap_channel channel,
2713 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2714{
2715 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2716 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2717
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2718 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2719
2720 return 0;
2721}
2722
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2723int dispc_get_clock_div(enum omap_channel channel,
2724 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2725{
2726 unsigned long fck;
2727
2728 fck = dispc_fclk_rate();
2729
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2730 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2731 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2732
2733 cinfo->lck = fck / cinfo->lck_div;
2734 cinfo->pck = cinfo->lck / cinfo->pck_div;
2735
2736 return 0;
2737}
2738
2739/* dispc.irq_lock has to be locked by the caller */
2740static void _omap_dispc_set_irqs(void)
2741{
2742 u32 mask;
2743 u32 old_mask;
2744 int i;
2745 struct omap_dispc_isr_data *isr_data;
2746
2747 mask = dispc.irq_error_mask;
2748
2749 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2750 isr_data = &dispc.registered_isr[i];
2751
2752 if (isr_data->isr == NULL)
2753 continue;
2754
2755 mask |= isr_data->mask;
2756 }
2757
2758 enable_clocks(1);
2759
2760 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2761 /* clear the irqstatus for newly enabled irqs */
2762 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2763
2764 dispc_write_reg(DISPC_IRQENABLE, mask);
2765
2766 enable_clocks(0);
2767}
2768
2769int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2770{
2771 int i;
2772 int ret;
2773 unsigned long flags;
2774 struct omap_dispc_isr_data *isr_data;
2775
2776 if (isr == NULL)
2777 return -EINVAL;
2778
2779 spin_lock_irqsave(&dispc.irq_lock, flags);
2780
2781 /* check for duplicate entry */
2782 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2783 isr_data = &dispc.registered_isr[i];
2784 if (isr_data->isr == isr && isr_data->arg == arg &&
2785 isr_data->mask == mask) {
2786 ret = -EINVAL;
2787 goto err;
2788 }
2789 }
2790
2791 isr_data = NULL;
2792 ret = -EBUSY;
2793
2794 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2795 isr_data = &dispc.registered_isr[i];
2796
2797 if (isr_data->isr != NULL)
2798 continue;
2799
2800 isr_data->isr = isr;
2801 isr_data->arg = arg;
2802 isr_data->mask = mask;
2803 ret = 0;
2804
2805 break;
2806 }
2807
Tomi Valkeinenb9cb0982011-03-04 18:19:54 +0200[diff] [blame]2808 if (ret)
2809 goto err;
2810
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2811 _omap_dispc_set_irqs();
2812
2813 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2814
2815 return 0;
2816err:
2817 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2818
2819 return ret;
2820}
2821EXPORT_SYMBOL(omap_dispc_register_isr);
2822
2823int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2824{
2825 int i;
2826 unsigned long flags;
2827 int ret = -EINVAL;
2828 struct omap_dispc_isr_data *isr_data;
2829
2830 spin_lock_irqsave(&dispc.irq_lock, flags);
2831
2832 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2833 isr_data = &dispc.registered_isr[i];
2834 if (isr_data->isr != isr || isr_data->arg != arg ||
2835 isr_data->mask != mask)
2836 continue;
2837
2838 /* found the correct isr */
2839
2840 isr_data->isr = NULL;
2841 isr_data->arg = NULL;
2842 isr_data->mask = 0;
2843
2844 ret = 0;
2845 break;
2846 }
2847
2848 if (ret == 0)
2849 _omap_dispc_set_irqs();
2850
2851 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2852
2853 return ret;
2854}
2855EXPORT_SYMBOL(omap_dispc_unregister_isr);
2856
2857#ifdef DEBUG
2858static void print_irq_status(u32 status)
2859{
2860 if ((status & dispc.irq_error_mask) == 0)
2861 return;
2862
2863 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2864
2865#define PIS(x) \
2866 if (status & DISPC_IRQ_##x) \
2867 printk(#x " ");
2868 PIS(GFX_FIFO_UNDERFLOW);
2869 PIS(OCP_ERR);
2870 PIS(VID1_FIFO_UNDERFLOW);
2871 PIS(VID2_FIFO_UNDERFLOW);
2872 PIS(SYNC_LOST);
2873 PIS(SYNC_LOST_DIGIT);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2874 if (dss_has_feature(FEAT_MGR_LCD2))
2875 PIS(SYNC_LOST2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2876#undef PIS
2877
2878 printk("\n");
2879}
2880#endif
2881
2882/* Called from dss.c. Note that we don't touch clocks here,
2883 * but we presume they are on because we got an IRQ. However,
2884 * an irq handler may turn the clocks off, so we may not have
2885 * clock later in the function. */
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2886static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2887{
2888 int i;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2889 u32 irqstatus, irqenable;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2890 u32 handledirqs = 0;
2891 u32 unhandled_errors;
2892 struct omap_dispc_isr_data *isr_data;
2893 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2894
2895 spin_lock(&dispc.irq_lock);
2896
2897 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2898 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2899
2900 /* IRQ is not for us */
2901 if (!(irqstatus & irqenable)) {
2902 spin_unlock(&dispc.irq_lock);
2903 return IRQ_NONE;
2904 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2905
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2906#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2907 spin_lock(&dispc.irq_stats_lock);
2908 dispc.irq_stats.irq_count++;
2909 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2910 spin_unlock(&dispc.irq_stats_lock);
2911#endif
2912
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2913#ifdef DEBUG
2914 if (dss_debug)
2915 print_irq_status(irqstatus);
2916#endif
2917 /* Ack the interrupt. Do it here before clocks are possibly turned
2918 * off */
2919 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2920 /* flush posted write */
2921 dispc_read_reg(DISPC_IRQSTATUS);
2922
2923 /* make a copy and unlock, so that isrs can unregister
2924 * themselves */
2925 memcpy(registered_isr, dispc.registered_isr,
2926 sizeof(registered_isr));
2927
2928 spin_unlock(&dispc.irq_lock);
2929
2930 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2931 isr_data = &registered_isr[i];
2932
2933 if (!isr_data->isr)
2934 continue;
2935
2936 if (isr_data->mask & irqstatus) {
2937 isr_data->isr(isr_data->arg, irqstatus);
2938 handledirqs |= isr_data->mask;
2939 }
2940 }
2941
2942 spin_lock(&dispc.irq_lock);
2943
2944 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2945
2946 if (unhandled_errors) {
2947 dispc.error_irqs |= unhandled_errors;
2948
2949 dispc.irq_error_mask &= ~unhandled_errors;
2950 _omap_dispc_set_irqs();
2951
2952 schedule_work(&dispc.error_work);
2953 }
2954
2955 spin_unlock(&dispc.irq_lock);
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2956
2957 return IRQ_HANDLED;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2958}
2959
2960static void dispc_error_worker(struct work_struct *work)
2961{
2962 int i;
2963 u32 errors;
2964 unsigned long flags;
2965
2966 spin_lock_irqsave(&dispc.irq_lock, flags);
2967 errors = dispc.error_irqs;
2968 dispc.error_irqs = 0;
2969 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2970
2971 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2972 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2973 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2974 struct omap_overlay *ovl;
2975 ovl = omap_dss_get_overlay(i);
2976
2977 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2978 continue;
2979
2980 if (ovl->id == 0) {
2981 dispc_enable_plane(ovl->id, 0);
2982 dispc_go(ovl->manager->id);
2983 mdelay(50);
2984 break;
2985 }
2986 }
2987 }
2988
2989 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2990 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2991 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2992 struct omap_overlay *ovl;
2993 ovl = omap_dss_get_overlay(i);
2994
2995 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2996 continue;
2997
2998 if (ovl->id == 1) {
2999 dispc_enable_plane(ovl->id, 0);
3000 dispc_go(ovl->manager->id);
3001 mdelay(50);
3002 break;
3003 }
3004 }
3005 }
3006
3007 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3008 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3009 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3010 struct omap_overlay *ovl;
3011 ovl = omap_dss_get_overlay(i);
3012
3013 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3014 continue;
3015
3016 if (ovl->id == 2) {
3017 dispc_enable_plane(ovl->id, 0);
3018 dispc_go(ovl->manager->id);
3019 mdelay(50);
3020 break;
3021 }
3022 }
3023 }
3024
3025 if (errors & DISPC_IRQ_SYNC_LOST) {
3026 struct omap_overlay_manager *manager = NULL;
3027 bool enable = false;
3028
3029 DSSERR("SYNC_LOST, disabling LCD\n");
3030
3031 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3032 struct omap_overlay_manager *mgr;
3033 mgr = omap_dss_get_overlay_manager(i);
3034
3035 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3036 manager = mgr;
3037 enable = mgr->device->state ==
3038 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3039 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3040 break;
3041 }
3042 }
3043
3044 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3045 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3046 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3047 struct omap_overlay *ovl;
3048 ovl = omap_dss_get_overlay(i);
3049
3050 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3051 continue;
3052
3053 if (ovl->id != 0 && ovl->manager == manager)
3054 dispc_enable_plane(ovl->id, 0);
3055 }
3056
3057 dispc_go(manager->id);
3058 mdelay(50);
3059 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3060 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3061 }
3062 }
3063
3064 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3065 struct omap_overlay_manager *manager = NULL;
3066 bool enable = false;
3067
3068 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3069
3070 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3071 struct omap_overlay_manager *mgr;
3072 mgr = omap_dss_get_overlay_manager(i);
3073
3074 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3075 manager = mgr;
3076 enable = mgr->device->state ==
3077 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3078 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3079 break;
3080 }
3081 }
3082
3083 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3084 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3085 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3086 struct omap_overlay *ovl;
3087 ovl = omap_dss_get_overlay(i);
3088
3089 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3090 continue;
3091
3092 if (ovl->id != 0 && ovl->manager == manager)
3093 dispc_enable_plane(ovl->id, 0);
3094 }
3095
3096 dispc_go(manager->id);
3097 mdelay(50);
3098 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3099 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3100 }
3101 }
3102
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]3103 if (errors & DISPC_IRQ_SYNC_LOST2) {
3104 struct omap_overlay_manager *manager = NULL;
3105 bool enable = false;
3106
3107 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3108
3109 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3110 struct omap_overlay_manager *mgr;
3111 mgr = omap_dss_get_overlay_manager(i);
3112
3113 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3114 manager = mgr;
3115 enable = mgr->device->state ==
3116 OMAP_DSS_DISPLAY_ACTIVE;
3117 mgr->device->driver->disable(mgr->device);
3118 break;
3119 }
3120 }
3121
3122 if (manager) {
3123 struct omap_dss_device *dssdev = manager->device;
3124 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3125 struct omap_overlay *ovl;
3126 ovl = omap_dss_get_overlay(i);
3127
3128 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3129 continue;
3130
3131 if (ovl->id != 0 && ovl->manager == manager)
3132 dispc_enable_plane(ovl->id, 0);
3133 }
3134
3135 dispc_go(manager->id);
3136 mdelay(50);
3137 if (enable)
3138 dssdev->driver->enable(dssdev);
3139 }
3140 }
3141
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3142 if (errors & DISPC_IRQ_OCP_ERR) {
3143 DSSERR("OCP_ERR\n");
3144 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3145 struct omap_overlay_manager *mgr;
3146 mgr = omap_dss_get_overlay_manager(i);
3147
3148 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3149 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3150 }
3151 }
3152
3153 spin_lock_irqsave(&dispc.irq_lock, flags);
3154 dispc.irq_error_mask |= errors;
3155 _omap_dispc_set_irqs();
3156 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3157}
3158
3159int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3160{
3161 void dispc_irq_wait_handler(void *data, u32 mask)
3162 {
3163 complete((struct completion *)data);
3164 }
3165
3166 int r;
3167 DECLARE_COMPLETION_ONSTACK(completion);
3168
3169 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3170 irqmask);
3171
3172 if (r)
3173 return r;
3174
3175 timeout = wait_for_completion_timeout(&completion, timeout);
3176
3177 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3178
3179 if (timeout == 0)
3180 return -ETIMEDOUT;
3181
3182 if (timeout == -ERESTARTSYS)
3183 return -ERESTARTSYS;
3184
3185 return 0;
3186}
3187
3188int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3189 unsigned long timeout)
3190{
3191 void dispc_irq_wait_handler(void *data, u32 mask)
3192 {
3193 complete((struct completion *)data);
3194 }
3195
3196 int r;
3197 DECLARE_COMPLETION_ONSTACK(completion);
3198
3199 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3200 irqmask);
3201
3202 if (r)
3203 return r;
3204
3205 timeout = wait_for_completion_interruptible_timeout(&completion,
3206 timeout);
3207
3208 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3209
3210 if (timeout == 0)
3211 return -ETIMEDOUT;
3212
3213 if (timeout == -ERESTARTSYS)
3214 return -ERESTARTSYS;
3215
3216 return 0;
3217}
3218
3219#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3220void dispc_fake_vsync_irq(void)
3221{
3222 u32 irqstatus = DISPC_IRQ_VSYNC;
3223 int i;
3224
Tomi Valkeinenab83b142010-06-09 15:31:01 +0300[diff] [blame]3225 WARN_ON(!in_interrupt());
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3226
3227 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3228 struct omap_dispc_isr_data *isr_data;
3229 isr_data = &dispc.registered_isr[i];
3230
3231 if (!isr_data->isr)
3232 continue;
3233
3234 if (isr_data->mask & irqstatus)
3235 isr_data->isr(isr_data->arg, irqstatus);
3236 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3237}
3238#endif
3239
3240static void _omap_dispc_initialize_irq(void)
3241{
3242 unsigned long flags;
3243
3244 spin_lock_irqsave(&dispc.irq_lock, flags);
3245
3246 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3247
3248 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]3249 if (dss_has_feature(FEAT_MGR_LCD2))
3250 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3251
3252 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3253 * so clear it */
3254 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3255
3256 _omap_dispc_set_irqs();
3257
3258 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3259}
3260
3261void dispc_enable_sidle(void)
3262{
3263 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3264}
3265
3266void dispc_disable_sidle(void)
3267{
3268 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3269}
3270
3271static void _omap_dispc_initial_config(void)
3272{
3273 u32 l;
3274
3275 l = dispc_read_reg(DISPC_SYSCONFIG);
3276 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3277 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3278 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3279 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3280 dispc_write_reg(DISPC_SYSCONFIG, l);
3281
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]3282 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3283 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3284 l = dispc_read_reg(DISPC_DIVISOR);
3285 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3286 l = FLD_MOD(l, 1, 0, 0);
3287 l = FLD_MOD(l, 1, 23, 16);
3288 dispc_write_reg(DISPC_DIVISOR, l);
3289 }
3290
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3291 /* FUNCGATED */
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]3292 if (dss_has_feature(FEAT_FUNCGATED))
3293 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3294
3295 /* L3 firewall setting: enable access to OCM RAM */
3296 /* XXX this should be somewhere in plat-omap */
3297 if (cpu_is_omap24xx())
3298 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3299
3300 _dispc_setup_color_conv_coef();
3301
3302 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3303
3304 dispc_read_plane_fifo_sizes();
3305}
3306
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3307int dispc_enable_plane(enum omap_plane plane, bool enable)
3308{
3309 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3310
3311 enable_clocks(1);
3312 _dispc_enable_plane(plane, enable);
3313 enable_clocks(0);
3314
3315 return 0;
3316}
3317
3318int dispc_setup_plane(enum omap_plane plane,
3319 u32 paddr, u16 screen_width,
3320 u16 pos_x, u16 pos_y,
3321 u16 width, u16 height,
3322 u16 out_width, u16 out_height,
3323 enum omap_color_mode color_mode,
3324 bool ilace,
3325 enum omap_dss_rotation_type rotation_type,
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]3326 u8 rotation, bool mirror, u8 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3327 u8 pre_mult_alpha, enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3328{
3329 int r = 0;
3330
3331 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3332 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3333 plane, paddr, screen_width, pos_x, pos_y,
3334 width, height,
3335 out_width, out_height,
3336 ilace, color_mode,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3337 rotation, mirror, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3338
3339 enable_clocks(1);
3340
3341 r = _dispc_setup_plane(plane,
3342 paddr, screen_width,
3343 pos_x, pos_y,
3344 width, height,
3345 out_width, out_height,
3346 color_mode, ilace,
3347 rotation_type,
3348 rotation, mirror,
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]3349 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3350 pre_mult_alpha, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3351
3352 enable_clocks(0);
3353
3354 return r;
3355}
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3356
3357/* DISPC HW IP initialisation */
3358static int omap_dispchw_probe(struct platform_device *pdev)
3359{
3360 u32 rev;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3361 int r = 0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3362 struct resource *dispc_mem;
3363
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3364 dispc.pdev = pdev;
3365
3366 spin_lock_init(&dispc.irq_lock);
3367
3368#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3369 spin_lock_init(&dispc.irq_stats_lock);
3370 dispc.irq_stats.last_reset = jiffies;
3371#endif
3372
3373 INIT_WORK(&dispc.error_work, dispc_error_worker);
3374
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3375 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3376 if (!dispc_mem) {
3377 DSSERR("can't get IORESOURCE_MEM DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3378 r = -EINVAL;
3379 goto fail0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3380 }
3381 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3382 if (!dispc.base) {
3383 DSSERR("can't ioremap DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3384 r = -ENOMEM;
3385 goto fail0;
3386 }
3387 dispc.irq = platform_get_irq(dispc.pdev, 0);
3388 if (dispc.irq < 0) {
3389 DSSERR("platform_get_irq failed\n");
3390 r = -ENODEV;
3391 goto fail1;
3392 }
3393
3394 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3395 "OMAP DISPC", dispc.pdev);
3396 if (r < 0) {
3397 DSSERR("request_irq failed\n");
3398 goto fail1;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3399 }
3400
3401 enable_clocks(1);
3402
3403 _omap_dispc_initial_config();
3404
3405 _omap_dispc_initialize_irq();
3406
3407 dispc_save_context();
3408
3409 rev = dispc_read_reg(DISPC_REVISION);
Sumit Semwala06b62f2011-01-24 06:22:03 +0000[diff] [blame]3410 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3411 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3412
3413 enable_clocks(0);
3414
3415 return 0;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3416fail1:
3417 iounmap(dispc.base);
3418fail0:
3419 return r;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3420}
3421
3422static int omap_dispchw_remove(struct platform_device *pdev)
3423{
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3424 free_irq(dispc.irq, dispc.pdev);
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3425 iounmap(dispc.base);
3426 return 0;
3427}
3428
3429static struct platform_driver omap_dispchw_driver = {
3430 .probe = omap_dispchw_probe,
3431 .remove = omap_dispchw_remove,
3432 .driver = {
3433 .name = "omapdss_dispc",
3434 .owner = THIS_MODULE,
3435 },
3436};
3437
3438int dispc_init_platform_driver(void)
3439{
3440 return platform_driver_register(&omap_dispchw_driver);
3441}
3442
3443void dispc_uninit_platform_driver(void)
3444{
3445 return platform_driver_unregister(&omap_dispchw_driver);
3446}