blob: 04fa5fc9226d77f8b75853a41141c2f85d5d46ed [file] [log] [blame]
Jiri Slaby037ad482006-12-08 02:38:11 -08001#ifndef _MXSER_H
2#define _MXSER_H
3
4/*
5 * Semi-public control interfaces
6 */
7
8/*
9 * MOXA ioctls
10 */
11
12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_GET_CONF (MOXA + 35)
15#define MOXA_DIAGNOSE (MOXA + 50)
16#define MOXA_CHKPORTENABLE (MOXA + 60)
17#define MOXA_HighSpeedOn (MOXA + 61)
18#define MOXA_GET_MAJOR (MOXA + 63)
19#define MOXA_GET_CUMAJOR (MOXA + 64)
20#define MOXA_GETMSTATUS (MOXA + 65)
21#define MOXA_SET_OP_MODE (MOXA + 66)
22#define MOXA_GET_OP_MODE (MOXA + 67)
23
24#define RS232_MODE 0
25#define RS485_2WIRE_MODE 1
26#define RS422_MODE 2
27#define RS485_4WIRE_MODE 3
28#define OP_MODE_MASK 3
Jiri Slaby037ad482006-12-08 02:38:11 -080029
Jiri Slabyed79ba12007-02-10 01:45:18 -080030#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
Jiri Slaby037ad482006-12-08 02:38:11 -080031#define MOXA_ASPP_OQUEUE (MOXA + 70)
32#define MOXA_ASPP_SETBAUD (MOXA + 71)
33#define MOXA_ASPP_GETBAUD (MOXA + 72)
34#define MOXA_ASPP_MON (MOXA + 73)
35#define MOXA_ASPP_LSTATUS (MOXA + 74)
36#define MOXA_ASPP_MON_EXT (MOXA + 75)
37#define MOXA_SET_BAUD_METHOD (MOXA + 76)
38
Jiri Slaby037ad482006-12-08 02:38:11 -080039/* --------------------------------------------------- */
40
41#define NPPI_NOTIFY_PARITY 0x01
42#define NPPI_NOTIFY_FRAMING 0x02
43#define NPPI_NOTIFY_HW_OVERRUN 0x04
44#define NPPI_NOTIFY_SW_OVERRUN 0x08
45#define NPPI_NOTIFY_BREAK 0x10
46
Jiri Slabyed79ba12007-02-10 01:45:18 -080047#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
48#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
49#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
50#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
Jiri Slaby037ad482006-12-08 02:38:11 -080051
Jiri Slabyed79ba12007-02-10 01:45:18 -080052/* follow just for Moxa Must chip define. */
53/* */
54/* when LCR register (offset 0x03) write following value, */
55/* the Must chip will enter enchance mode. And write value */
56/* on EFR (offset 0x02) bit 6,7 to change bank. */
Jiri Slaby037ad482006-12-08 02:38:11 -080057#define MOXA_MUST_ENTER_ENCHANCE 0xBF
58
Jiri Slabyed79ba12007-02-10 01:45:18 -080059/* when enhance mode enable, access on general bank register */
Jiri Slaby037ad482006-12-08 02:38:11 -080060#define MOXA_MUST_GDL_REGISTER 0x07
61#define MOXA_MUST_GDL_MASK 0x7F
62#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
63
Jiri Slabyed79ba12007-02-10 01:45:18 -080064#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
65/* enchance register bank select and enchance mode setting register */
66/* when LCR register equal to 0xBF */
Jiri Slaby037ad482006-12-08 02:38:11 -080067#define MOXA_MUST_EFR_REGISTER 0x02
Jiri Slabyed79ba12007-02-10 01:45:18 -080068/* enchance mode enable */
Jiri Slaby037ad482006-12-08 02:38:11 -080069#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
Jiri Slabyed79ba12007-02-10 01:45:18 -080070/* enchance reister bank set 0, 1, 2 */
Jiri Slaby037ad482006-12-08 02:38:11 -080071#define MOXA_MUST_EFR_BANK0 0x00
72#define MOXA_MUST_EFR_BANK1 0x40
73#define MOXA_MUST_EFR_BANK2 0x80
74#define MOXA_MUST_EFR_BANK3 0xC0
75#define MOXA_MUST_EFR_BANK_MASK 0xC0
76
Jiri Slabyed79ba12007-02-10 01:45:18 -080077/* set XON1 value register, when LCR=0xBF and change to bank0 */
Jiri Slaby037ad482006-12-08 02:38:11 -080078#define MOXA_MUST_XON1_REGISTER 0x04
79
Jiri Slabyed79ba12007-02-10 01:45:18 -080080/* set XON2 value register, when LCR=0xBF and change to bank0 */
Jiri Slaby037ad482006-12-08 02:38:11 -080081#define MOXA_MUST_XON2_REGISTER 0x05
82
Jiri Slabyed79ba12007-02-10 01:45:18 -080083/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
Jiri Slaby037ad482006-12-08 02:38:11 -080084#define MOXA_MUST_XOFF1_REGISTER 0x06
85
Jiri Slabyed79ba12007-02-10 01:45:18 -080086/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
Jiri Slaby037ad482006-12-08 02:38:11 -080087#define MOXA_MUST_XOFF2_REGISTER 0x07
88
89#define MOXA_MUST_RBRTL_REGISTER 0x04
90#define MOXA_MUST_RBRTH_REGISTER 0x05
91#define MOXA_MUST_RBRTI_REGISTER 0x06
92#define MOXA_MUST_THRTL_REGISTER 0x07
93#define MOXA_MUST_ENUM_REGISTER 0x04
94#define MOXA_MUST_HWID_REGISTER 0x05
95#define MOXA_MUST_ECR_REGISTER 0x06
96#define MOXA_MUST_CSR_REGISTER 0x07
97
Jiri Slabyed79ba12007-02-10 01:45:18 -080098/* good data mode enable */
Jiri Slaby037ad482006-12-08 02:38:11 -080099#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
Jiri Slabyed79ba12007-02-10 01:45:18 -0800100/* only good data put into RxFIFO */
Jiri Slaby037ad482006-12-08 02:38:11 -0800101#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
102
Jiri Slabyed79ba12007-02-10 01:45:18 -0800103/* enable CTS interrupt */
Jiri Slaby037ad482006-12-08 02:38:11 -0800104#define MOXA_MUST_IER_ECTSI 0x80
Jiri Slabyed79ba12007-02-10 01:45:18 -0800105/* enable RTS interrupt */
Jiri Slaby037ad482006-12-08 02:38:11 -0800106#define MOXA_MUST_IER_ERTSI 0x40
Jiri Slabyed79ba12007-02-10 01:45:18 -0800107/* enable Xon/Xoff interrupt */
Jiri Slaby037ad482006-12-08 02:38:11 -0800108#define MOXA_MUST_IER_XINT 0x20
Jiri Slabyed79ba12007-02-10 01:45:18 -0800109/* enable GDA interrupt */
Jiri Slaby037ad482006-12-08 02:38:11 -0800110#define MOXA_MUST_IER_EGDAI 0x10
111
112#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
113
Jiri Slabyed79ba12007-02-10 01:45:18 -0800114/* GDA interrupt pending */
Jiri Slaby037ad482006-12-08 02:38:11 -0800115#define MOXA_MUST_IIR_GDA 0x1C
116#define MOXA_MUST_IIR_RDA 0x04
117#define MOXA_MUST_IIR_RTO 0x0C
118#define MOXA_MUST_IIR_LSR 0x06
119
Jiri Slabyed79ba12007-02-10 01:45:18 -0800120/* recieved Xon/Xoff or specical interrupt pending */
Jiri Slaby037ad482006-12-08 02:38:11 -0800121#define MOXA_MUST_IIR_XSC 0x10
122
Jiri Slabyed79ba12007-02-10 01:45:18 -0800123/* RTS/CTS change state interrupt pending */
Jiri Slaby037ad482006-12-08 02:38:11 -0800124#define MOXA_MUST_IIR_RTSCTS 0x20
125#define MOXA_MUST_IIR_MASK 0x3E
126
127#define MOXA_MUST_MCR_XON_FLAG 0x40
128#define MOXA_MUST_MCR_XON_ANY 0x80
129#define MOXA_MUST_MCR_TX_XON 0x08
130
Jiri Slabyed79ba12007-02-10 01:45:18 -0800131/* software flow control on chip mask value */
Jiri Slaby037ad482006-12-08 02:38:11 -0800132#define MOXA_MUST_EFR_SF_MASK 0x0F
Jiri Slabyed79ba12007-02-10 01:45:18 -0800133/* send Xon1/Xoff1 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800134#define MOXA_MUST_EFR_SF_TX1 0x08
Jiri Slabyed79ba12007-02-10 01:45:18 -0800135/* send Xon2/Xoff2 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800136#define MOXA_MUST_EFR_SF_TX2 0x04
Jiri Slabyed79ba12007-02-10 01:45:18 -0800137/* send Xon1,Xon2/Xoff1,Xoff2 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800138#define MOXA_MUST_EFR_SF_TX12 0x0C
Jiri Slabyed79ba12007-02-10 01:45:18 -0800139/* don't send Xon/Xoff */
Jiri Slaby037ad482006-12-08 02:38:11 -0800140#define MOXA_MUST_EFR_SF_TX_NO 0x00
Jiri Slabyed79ba12007-02-10 01:45:18 -0800141/* Tx software flow control mask */
Jiri Slaby037ad482006-12-08 02:38:11 -0800142#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
Jiri Slabyed79ba12007-02-10 01:45:18 -0800143/* don't receive Xon/Xoff */
Jiri Slaby037ad482006-12-08 02:38:11 -0800144#define MOXA_MUST_EFR_SF_RX_NO 0x00
Jiri Slabyed79ba12007-02-10 01:45:18 -0800145/* receive Xon1/Xoff1 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800146#define MOXA_MUST_EFR_SF_RX1 0x02
Jiri Slabyed79ba12007-02-10 01:45:18 -0800147/* receive Xon2/Xoff2 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800148#define MOXA_MUST_EFR_SF_RX2 0x01
Jiri Slabyed79ba12007-02-10 01:45:18 -0800149/* receive Xon1,Xon2/Xoff1,Xoff2 */
Jiri Slaby037ad482006-12-08 02:38:11 -0800150#define MOXA_MUST_EFR_SF_RX12 0x03
Jiri Slabyed79ba12007-02-10 01:45:18 -0800151/* Rx software flow control mask */
Jiri Slaby037ad482006-12-08 02:38:11 -0800152#define MOXA_MUST_EFR_SF_RX_MASK 0x03
153
Jiri Slabyed79ba12007-02-10 01:45:18 -0800154#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
155 u8 __oldlcr, __efr; \
156 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800157 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800158 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
159 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
160 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
161 outb(__oldlcr, (baseio)+UART_LCR); \
162} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800163
Jiri Slabyed79ba12007-02-10 01:45:18 -0800164#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
165 u8 __oldlcr, __efr; \
166 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800167 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800168 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
169 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
170 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
171 outb(__oldlcr, (baseio)+UART_LCR); \
172} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800173
Jiri Slabyed79ba12007-02-10 01:45:18 -0800174#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
175 u8 __oldlcr, __efr; \
176 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800177 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800178 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
179 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
180 __efr |= MOXA_MUST_EFR_BANK0; \
181 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800182 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800183 outb(__oldlcr, (baseio)+UART_LCR); \
184} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800185
Jiri Slabyed79ba12007-02-10 01:45:18 -0800186#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
187 u8 __oldlcr, __efr; \
188 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800189 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800190 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
191 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
192 __efr |= MOXA_MUST_EFR_BANK0; \
193 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800194 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800195 outb(__oldlcr, (baseio)+UART_LCR); \
196} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800197
Jiri Slabyed79ba12007-02-10 01:45:18 -0800198#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
199 u8 __oldlcr, __efr; \
200 __oldlcr = inb((info)->ioaddr+UART_LCR); \
201 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
Jiri Slaby55b307d2006-12-08 02:38:14 -0800202 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800203 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
204 __efr |= MOXA_MUST_EFR_BANK1; \
Jiri Slaby55b307d2006-12-08 02:38:14 -0800205 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800206 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
207 MOXA_MUST_RBRTH_REGISTER); \
208 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
209 MOXA_MUST_RBRTI_REGISTER); \
210 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
211 MOXA_MUST_RBRTL_REGISTER); \
212 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
213} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800214
Jiri Slabyed79ba12007-02-10 01:45:18 -0800215#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
216 u8 __oldlcr, __efr; \
217 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800218 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800219 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
220 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
221 __efr |= MOXA_MUST_EFR_BANK2; \
222 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
223 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
224 outb(__oldlcr, (baseio)+UART_LCR); \
225} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800226
Jiri Slabyed79ba12007-02-10 01:45:18 -0800227#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
228 u8 __oldlcr, __efr; \
229 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800230 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800231 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
232 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
233 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
234 outb(__oldlcr, (baseio)+UART_LCR); \
235} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800236
Jiri Slabyed79ba12007-02-10 01:45:18 -0800237#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
238 u8 __oldlcr, __efr; \
239 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800240 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800241 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
242 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
243 __efr |= MOXA_MUST_EFR_SF_TX1; \
244 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
245 outb(__oldlcr, (baseio)+UART_LCR); \
246} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800247
Jiri Slabyed79ba12007-02-10 01:45:18 -0800248#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
249 u8 __oldlcr, __efr; \
250 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800251 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800252 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
253 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
254 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
255 outb(__oldlcr, (baseio)+UART_LCR); \
256} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800257
Jiri Slabyed79ba12007-02-10 01:45:18 -0800258#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
259 u8 __oldlcr, __efr; \
260 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800261 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800262 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
263 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
264 __efr |= MOXA_MUST_EFR_SF_RX1; \
265 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
266 outb(__oldlcr, (baseio)+UART_LCR); \
267} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800268
Jiri Slabyed79ba12007-02-10 01:45:18 -0800269#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
270 u8 __oldlcr, __efr; \
271 __oldlcr = inb((baseio)+UART_LCR); \
Jiri Slaby037ad482006-12-08 02:38:11 -0800272 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
Jiri Slabyed79ba12007-02-10 01:45:18 -0800273 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
274 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
275 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
276 outb(__oldlcr, (baseio)+UART_LCR); \
277} while (0)
Jiri Slaby037ad482006-12-08 02:38:11 -0800278
Jiri Slaby037ad482006-12-08 02:38:11 -0800279#endif