| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | Kernel driver i2c-piix4 | 
|  | 2 |  | 
|  | 3 | Supported adapters: | 
|  | 4 | * Intel 82371AB PIIX4 and PIIX4E | 
|  | 5 | * Intel 82443MX (440MX) | 
|  | 6 | Datasheet: Publicly available at the Intel website | 
| Flavio Leitner | 506a8b6 | 2009-03-28 21:34:46 +0100 | [diff] [blame] | 7 | * ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | Datasheet: Only available via NDA from ServerWorks | 
| Shane Huang | 60693e5 | 2007-08-30 23:56:38 -0700 | [diff] [blame] | 9 | * ATI IXP200, IXP300, IXP400, SB600, SB700 and SB800 southbridges | 
| Rudolf Marek | 02e0c5d | 2006-03-23 16:48:09 +0100 | [diff] [blame] | 10 | Datasheet: Not publicly available | 
| Crane Cai | 3806e94 | 2009-11-07 13:10:46 +0100 | [diff] [blame] | 11 | * AMD Hudson-2 | 
| Crane Cai | 76b3e28 | 2009-09-18 22:45:50 +0200 | [diff] [blame] | 12 | Datasheet: Not publicly available | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge | 
|  | 14 | Datasheet: Publicly available at the SMSC website http://www.smsc.com | 
|  | 15 |  | 
|  | 16 | Authors: | 
|  | 17 | Frodo Looijaard <frodol@dds.nl> | 
|  | 18 | Philip Edelbrock <phil@netroedge.com> | 
|  | 19 |  | 
|  | 20 |  | 
|  | 21 | Module Parameters | 
|  | 22 | ----------------- | 
|  | 23 |  | 
|  | 24 | * force: int | 
|  | 25 | Forcibly enable the PIIX4. DANGEROUS! | 
|  | 26 | * force_addr: int | 
|  | 27 | Forcibly enable the PIIX4 at the given address. EXTREMELY DANGEROUS! | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 |  | 
|  | 29 |  | 
|  | 30 | Description | 
|  | 31 | ----------- | 
|  | 32 |  | 
|  | 33 | The PIIX4 (properly known as the 82371AB) is an Intel chip with a lot of | 
|  | 34 | functionality. Among other things, it implements the PCI bus. One of its | 
|  | 35 | minor functions is implementing a System Management Bus. This is a true | 
|  | 36 | SMBus - you can not access it on I2C levels. The good news is that it | 
|  | 37 | natively understands SMBus commands and you do not have to worry about | 
|  | 38 | timing problems. The bad news is that non-SMBus devices connected to it can | 
|  | 39 | confuse it mightily. Yes, this is known to happen... | 
|  | 40 |  | 
|  | 41 | Do 'lspci -v' and see whether it contains an entry like this: | 
|  | 42 |  | 
|  | 43 | 0000:00:02.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02) | 
|  | 44 | Flags: medium devsel, IRQ 9 | 
|  | 45 |  | 
|  | 46 | Bus and device numbers may differ, but the function number must be | 
|  | 47 | identical (like many PCI devices, the PIIX4 incorporates a number of | 
|  | 48 | different 'functions', which can be considered as separate devices). If you | 
|  | 49 | find such an entry, you have a PIIX4 SMBus controller. | 
|  | 50 |  | 
|  | 51 | On some computers (most notably, some Dells), the SMBus is disabled by | 
|  | 52 | default. If you use the insmod parameter 'force=1', the kernel module will | 
|  | 53 | try to enable it. THIS IS VERY DANGEROUS! If the BIOS did not set up a | 
|  | 54 | correct address for this module, you could get in big trouble (read: | 
|  | 55 | crashes, data corruption, etc.). Try this only as a last resort (try BIOS | 
|  | 56 | updates first, for example), and backup first! An even more dangerous | 
|  | 57 | option is 'force_addr=<IOPORT>'. This will not only enable the PIIX4 like | 
|  | 58 | 'force' foes, but it will also set a new base I/O port address. The SMBus | 
|  | 59 | parts of the PIIX4 needs a range of 8 of these addresses to function | 
|  | 60 | correctly. If these addresses are already reserved by some other device, | 
|  | 61 | you will get into big trouble! DON'T USE THIS IF YOU ARE NOT VERY SURE | 
|  | 62 | ABOUT WHAT YOU ARE DOING! | 
|  | 63 |  | 
|  | 64 | The PIIX4E is just an new version of the PIIX4; it is supported as well. | 
|  | 65 | The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use | 
|  | 66 | this driver on those mainboards. | 
|  | 67 |  | 
| Jean Delvare | 7aadb8f | 2006-04-25 13:29:26 +0200 | [diff] [blame] | 68 | The ServerWorks Southbridges, the Intel 440MX, and the Victory66 are | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | identical to the PIIX4 in I2C/SMBus support. | 
|  | 70 |  | 
| Rudolf Marek | 54aaa1c | 2006-04-25 13:06:41 +0200 | [diff] [blame] | 71 | If you own Force CPCI735 motherboard or other OSB4 based systems you may need | 
|  | 72 | to change the SMBus Interrupt Select register so the SMBus controller uses | 
|  | 73 | the SMI mode. | 
|  | 74 |  | 
|  | 75 | 1) Use lspci command and locate the PCI device with the SMBus controller: | 
|  | 76 | 00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f) | 
|  | 77 | The line may vary for different chipsets. Please consult the driver source | 
|  | 78 | for all possible PCI ids (and lspci -n to match them). Lets assume the | 
|  | 79 | device is located at 00:0f.0. | 
|  | 80 | 2) Now you just need to change the value in 0xD2 register. Get it first with | 
|  | 81 | command: lspci -xxx -s 00:0f.0 | 
|  | 82 | If the value is 0x3 then you need to change it to 0x1 | 
|  | 83 | setpci  -s 00:0f.0 d2.b=1 | 
|  | 84 |  | 
|  | 85 | Please note that you don't need to do that in all cases, just when the SMBus is | 
|  | 86 | not working properly. | 
| Jean Delvare | f9ba6c0 | 2006-04-25 13:37:25 +0200 | [diff] [blame] | 87 |  | 
|  | 88 |  | 
|  | 89 | Hardware-specific issues | 
|  | 90 | ------------------------ | 
|  | 91 |  | 
|  | 92 | This driver will refuse to load on IBM systems with an Intel PIIX4 SMBus. | 
|  | 93 | Some of these machines have an RFID EEPROM (24RF08) connected to the SMBus, | 
|  | 94 | which can easily get corrupted due to a state machine bug. These are mostly | 
|  | 95 | Thinkpad laptops, but desktop systems may also be affected. We have no list | 
|  | 96 | of all affected systems, so the only safe solution was to prevent access to | 
|  | 97 | the SMBus on all IBM systems (detected using DMI data.) | 
|  | 98 |  | 
|  | 99 | For additional information, read: | 
| Jean Delvare | ec1d86c | 2007-11-18 23:46:10 +0100 | [diff] [blame] | 100 | http://www.lm-sensors.org/browser/lm-sensors/trunk/README.thinkpad |