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Felipe Balbi72246da2011-08-19 18:10:58 +03001/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
Felipe Balbi72246da2011-08-19 18:10:58 +03005 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/interrupt.h>
45#include <linux/io.h>
46#include <linux/list.h>
47#include <linux/dma-mapping.h>
48
49#include <linux/usb/ch9.h>
50#include <linux/usb/gadget.h>
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +010051#include <linux/usb/composite.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030052
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +010057static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
58
Felipe Balbi72246da2011-08-19 18:10:58 +030059static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
60{
61 switch (state) {
62 case EP0_UNCONNECTED:
63 return "Unconnected";
Felipe Balbic7fcdeb2011-08-27 22:28:36 +030064 case EP0_SETUP_PHASE:
65 return "Setup Phase";
66 case EP0_DATA_PHASE:
67 return "Data Phase";
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
Felipe Balbi72246da2011-08-19 18:10:58 +030070 default:
71 return "UNKNOWN";
72 }
73}
74
75static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
Felipe Balbic7fcdeb2011-08-27 22:28:36 +030076 u32 len, u32 type)
Felipe Balbi72246da2011-08-19 18:10:58 +030077{
78 struct dwc3_gadget_ep_cmd_params params;
Felipe Balbif6bafc62012-02-06 11:04:53 +020079 struct dwc3_trb *trb;
Felipe Balbi72246da2011-08-19 18:10:58 +030080 struct dwc3_ep *dep;
81
82 int ret;
83
84 dep = dwc->eps[epnum];
Felipe Balbic7fcdeb2011-08-27 22:28:36 +030085 if (dep->flags & DWC3_EP_BUSY) {
86 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
87 return 0;
88 }
Felipe Balbi72246da2011-08-19 18:10:58 +030089
Felipe Balbif6bafc62012-02-06 11:04:53 +020090 trb = dwc->ep0_trb;
Felipe Balbi72246da2011-08-19 18:10:58 +030091
Felipe Balbif6bafc62012-02-06 11:04:53 +020092 trb->bpl = lower_32_bits(buf_dma);
93 trb->bph = upper_32_bits(buf_dma);
94 trb->size = len;
95 trb->ctrl = type;
Felipe Balbi72246da2011-08-19 18:10:58 +030096
Felipe Balbif6bafc62012-02-06 11:04:53 +020097 trb->ctrl |= (DWC3_TRB_CTRL_HWO
98 | DWC3_TRB_CTRL_LST
99 | DWC3_TRB_CTRL_IOC
100 | DWC3_TRB_CTRL_ISP_IMI);
Felipe Balbi72246da2011-08-19 18:10:58 +0300101
102 memset(&params, 0, sizeof(params));
Felipe Balbidc1c70a2011-09-30 10:58:51 +0300103 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
104 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
Felipe Balbi72246da2011-08-19 18:10:58 +0300105
106 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
107 DWC3_DEPCMD_STARTTRANSFER, &params);
108 if (ret < 0) {
109 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
110 return ret;
111 }
112
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300113 dep->flags |= DWC3_EP_BUSY;
Felipe Balbi72246da2011-08-19 18:10:58 +0300114 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
115 dep->number);
116
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300117 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118
Felipe Balbi72246da2011-08-19 18:10:58 +0300119 return 0;
120}
121
122static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
123 struct dwc3_request *req)
124{
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100125 struct dwc3 *dwc = dep->dwc;
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300126 int ret = 0;
Felipe Balbi72246da2011-08-19 18:10:58 +0300127
128 req->request.actual = 0;
129 req->request.status = -EINPROGRESS;
Felipe Balbi72246da2011-08-19 18:10:58 +0300130 req->epnum = dep->number;
131
132 list_add_tail(&req->list, &dep->request_list);
Felipe Balbi72246da2011-08-19 18:10:58 +0300133
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300134 /*
135 * Gadget driver might not be quick enough to queue a request
136 * before we get a Transfer Not Ready event on this endpoint.
137 *
138 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
139 * flag is set, it's telling us that as soon as Gadget queues the
140 * required request, we should kick the transfer here because the
141 * IRQ we were waiting for is long gone.
142 */
143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300144 unsigned direction;
Felipe Balbia6829702011-08-27 22:18:09 +0300145
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300146 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
Felipe Balbia6829702011-08-27 22:18:09 +0300147
Felipe Balbi68d8a782011-12-29 06:32:29 +0200148 if (dwc->ep0state != EP0_DATA_PHASE) {
149 dev_WARN(dwc->dev, "Unexpected pending request\n");
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300150 return 0;
151 }
Felipe Balbia6829702011-08-27 22:18:09 +0300152
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300153 ret = dwc3_ep0_start_trans(dwc, direction,
Felipe Balbi68d8a782011-12-29 06:32:29 +0200154 req->request.dma, req->request.length,
155 DWC3_TRBCTL_CONTROL_DATA);
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300156 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 DWC3_EP0_DIR_IN);
Felipe Balbi68d3e662011-12-08 13:56:27 +0200158 } else if (dwc->delayed_status) {
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100159 dwc->delayed_status = false;
Felipe Balbi68d3e662011-12-08 13:56:27 +0200160
161 if (dwc->ep0state == EP0_STATUS_PHASE)
162 dwc3_ep0_do_control_status(dwc, 1);
163 else
164 dev_dbg(dwc->dev, "too early for delayed status\n");
Felipe Balbi72246da2011-08-19 18:10:58 +0300165 }
166
167 return ret;
168}
169
170int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
171 gfp_t gfp_flags)
172{
173 struct dwc3_request *req = to_dwc3_request(request);
174 struct dwc3_ep *dep = to_dwc3_ep(ep);
175 struct dwc3 *dwc = dep->dwc;
176
177 unsigned long flags;
178
179 int ret;
180
Felipe Balbi72246da2011-08-19 18:10:58 +0300181 spin_lock_irqsave(&dwc->lock, flags);
182 if (!dep->desc) {
183 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
184 request, dep->name);
185 ret = -ESHUTDOWN;
186 goto out;
187 }
188
189 /* we share one TRB for ep0/1 */
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200190 if (!list_empty(&dep->request_list)) {
Felipe Balbi72246da2011-08-19 18:10:58 +0300191 ret = -EBUSY;
192 goto out;
193 }
194
195 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
196 request, dep->name, request->length,
197 dwc3_ep0_state_string(dwc->ep0state));
198
199 ret = __dwc3_gadget_ep0_queue(dep, req);
200
201out:
202 spin_unlock_irqrestore(&dwc->lock, flags);
203
204 return ret;
205}
206
207static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
208{
Felipe Balbid7422202011-09-08 18:17:12 +0300209 struct dwc3_ep *dep = dwc->eps[0];
210
Felipe Balbi72246da2011-08-19 18:10:58 +0300211 /* stall is always issued on EP0 */
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200212 __dwc3_gadget_ep_set_halt(dep, 1);
213 dep->flags = DWC3_EP_ENABLED;
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100214 dwc->delayed_status = false;
Felipe Balbid7422202011-09-08 18:17:12 +0300215
216 if (!list_empty(&dep->request_list)) {
217 struct dwc3_request *req;
218
219 req = next_request(&dep->request_list);
220 dwc3_gadget_giveback(dep, req, -ECONNRESET);
221 }
222
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300223 dwc->ep0state = EP0_SETUP_PHASE;
Felipe Balbi72246da2011-08-19 18:10:58 +0300224 dwc3_ep0_out_start(dwc);
225}
226
227void dwc3_ep0_out_start(struct dwc3 *dwc)
228{
Felipe Balbi72246da2011-08-19 18:10:58 +0300229 int ret;
230
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300231 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
232 DWC3_TRBCTL_CONTROL_SETUP);
Felipe Balbi72246da2011-08-19 18:10:58 +0300233 WARN_ON(ret < 0);
234}
235
Felipe Balbi72246da2011-08-19 18:10:58 +0300236static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
237{
238 struct dwc3_ep *dep;
239 u32 windex = le16_to_cpu(wIndex_le);
240 u32 epnum;
241
242 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
243 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
244 epnum |= 1;
245
246 dep = dwc->eps[epnum];
247 if (dep->flags & DWC3_EP_ENABLED)
248 return dep;
249
250 return NULL;
251}
252
Sebastian Andrzej Siewior8ee62702011-10-18 19:13:29 +0200253static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
Felipe Balbi72246da2011-08-19 18:10:58 +0300254{
Felipe Balbi72246da2011-08-19 18:10:58 +0300255}
Felipe Balbi72246da2011-08-19 18:10:58 +0300256/*
257 * ch 9.4.5
258 */
Felipe Balbi25b8ff62011-11-04 12:32:47 +0200259static int dwc3_ep0_handle_status(struct dwc3 *dwc,
260 struct usb_ctrlrequest *ctrl)
Felipe Balbi72246da2011-08-19 18:10:58 +0300261{
262 struct dwc3_ep *dep;
263 u32 recip;
264 u16 usb_status = 0;
265 __le16 *response_pkt;
266
267 recip = ctrl->bRequestType & USB_RECIP_MASK;
268 switch (recip) {
269 case USB_RECIP_DEVICE:
270 /*
271 * We are self-powered. U1/U2/LTM will be set later
272 * once we handle this states. RemoteWakeup is 0 on SS
273 */
274 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
275 break;
276
277 case USB_RECIP_INTERFACE:
278 /*
279 * Function Remote Wake Capable D0
280 * Function Remote Wakeup D1
281 */
282 break;
283
284 case USB_RECIP_ENDPOINT:
285 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
286 if (!dep)
Felipe Balbi25b8ff62011-11-04 12:32:47 +0200287 return -EINVAL;
Felipe Balbi72246da2011-08-19 18:10:58 +0300288
289 if (dep->flags & DWC3_EP_STALL)
290 usb_status = 1 << USB_ENDPOINT_HALT;
291 break;
292 default:
293 return -EINVAL;
294 };
295
296 response_pkt = (__le16 *) dwc->setup_buf;
297 *response_pkt = cpu_to_le16(usb_status);
Felipe Balbie2617792011-11-29 10:35:47 +0200298
299 dep = dwc->eps[0];
300 dwc->ep0_usb_req.dep = dep;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100301 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
Felipe Balbi0fc9a1b2011-12-19 11:32:34 +0200302 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100303 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
Felipe Balbie2617792011-11-29 10:35:47 +0200304
305 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
Felipe Balbi72246da2011-08-19 18:10:58 +0300306}
307
308static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
309 struct usb_ctrlrequest *ctrl, int set)
310{
311 struct dwc3_ep *dep;
312 u32 recip;
313 u32 wValue;
314 u32 wIndex;
Felipe Balbi72246da2011-08-19 18:10:58 +0300315 int ret;
Felipe Balbi72246da2011-08-19 18:10:58 +0300316
317 wValue = le16_to_cpu(ctrl->wValue);
318 wIndex = le16_to_cpu(ctrl->wIndex);
319 recip = ctrl->bRequestType & USB_RECIP_MASK;
320 switch (recip) {
321 case USB_RECIP_DEVICE:
322
323 /*
324 * 9.4.1 says only only for SS, in AddressState only for
325 * default control pipe
326 */
327 switch (wValue) {
328 case USB_DEVICE_U1_ENABLE:
329 case USB_DEVICE_U2_ENABLE:
330 case USB_DEVICE_LTM_ENABLE:
331 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
332 return -EINVAL;
333 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
334 return -EINVAL;
335 }
336
337 /* XXX add U[12] & LTM */
338 switch (wValue) {
339 case USB_DEVICE_REMOTE_WAKEUP:
340 break;
341 case USB_DEVICE_U1_ENABLE:
342 break;
343 case USB_DEVICE_U2_ENABLE:
344 break;
345 case USB_DEVICE_LTM_ENABLE:
346 break;
347
348 case USB_DEVICE_TEST_MODE:
349 if ((wIndex & 0xff) != 0)
350 return -EINVAL;
351 if (!set)
352 return -EINVAL;
353
Gerard Cauvy3b637362012-02-10 12:21:18 +0200354 dwc->test_mode_nr = wIndex >> 8;
355 dwc->test_mode = true;
Gerard Cauvyecb07792012-03-16 16:20:10 +0200356 break;
357 default:
358 return -EINVAL;
Felipe Balbi72246da2011-08-19 18:10:58 +0300359 }
360 break;
361
362 case USB_RECIP_INTERFACE:
363 switch (wValue) {
364 case USB_INTRF_FUNC_SUSPEND:
365 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
366 /* XXX enable Low power suspend */
367 ;
368 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
369 /* XXX enable remote wakeup */
370 ;
371 break;
372 default:
373 return -EINVAL;
374 }
375 break;
376
377 case USB_RECIP_ENDPOINT:
378 switch (wValue) {
379 case USB_ENDPOINT_HALT:
Paul Zimmerman1d046792012-02-15 18:56:56 -0800380 dep = dwc3_wIndex_to_dep(dwc, wIndex);
Felipe Balbi72246da2011-08-19 18:10:58 +0300381 if (!dep)
382 return -EINVAL;
Alan Sternf7557c72013-11-01 12:05:12 -0400383 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
384 break;
Felipe Balbi72246da2011-08-19 18:10:58 +0300385 ret = __dwc3_gadget_ep_set_halt(dep, set);
386 if (ret)
387 return -EINVAL;
388 break;
389 default:
390 return -EINVAL;
391 }
392 break;
393
394 default:
395 return -EINVAL;
396 };
397
Felipe Balbi72246da2011-08-19 18:10:58 +0300398 return 0;
399}
400
401static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
402{
Felipe Balbi72246da2011-08-19 18:10:58 +0300403 u32 addr;
404 u32 reg;
405
406 addr = le16_to_cpu(ctrl->wValue);
Felipe Balbif96a6ec2011-10-15 21:37:35 +0300407 if (addr > 127) {
408 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
Felipe Balbi72246da2011-08-19 18:10:58 +0300409 return -EINVAL;
Felipe Balbif96a6ec2011-10-15 21:37:35 +0300410 }
411
412 if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
413 dev_dbg(dwc->dev, "trying to set address when configured\n");
414 return -EINVAL;
415 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300416
Felipe Balbi26460212011-09-30 10:58:36 +0300417 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
418 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
419 reg |= DWC3_DCFG_DEVADDR(addr);
420 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
Felipe Balbi72246da2011-08-19 18:10:58 +0300421
Felipe Balbi26460212011-09-30 10:58:36 +0300422 if (addr)
423 dwc->dev_state = DWC3_ADDRESS_STATE;
424 else
425 dwc->dev_state = DWC3_DEFAULT_STATE;
Felipe Balbi72246da2011-08-19 18:10:58 +0300426
Felipe Balbi26460212011-09-30 10:58:36 +0300427 return 0;
Felipe Balbi72246da2011-08-19 18:10:58 +0300428}
429
430static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
431{
432 int ret;
433
434 spin_unlock(&dwc->lock);
435 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
436 spin_lock(&dwc->lock);
437 return ret;
438}
439
440static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
441{
442 u32 cfg;
443 int ret;
444
Paul Zimmermanb23c8432011-09-30 10:58:42 +0300445 dwc->start_config_issued = false;
Felipe Balbi72246da2011-08-19 18:10:58 +0300446 cfg = le16_to_cpu(ctrl->wValue);
447
448 switch (dwc->dev_state) {
449 case DWC3_DEFAULT_STATE:
450 return -EINVAL;
451 break;
452
453 case DWC3_ADDRESS_STATE:
454 ret = dwc3_ep0_delegate_req(dwc, ctrl);
455 /* if the cfg matches and the cfg is non zero */
Felipe Balbi457e84b2012-01-18 18:04:09 +0200456 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
Felipe Balbi72246da2011-08-19 18:10:58 +0300457 dwc->dev_state = DWC3_CONFIGURED_STATE;
Felipe Balbi457e84b2012-01-18 18:04:09 +0200458 dwc->resize_fifos = true;
459 dev_dbg(dwc->dev, "resize fifos flag SET\n");
460 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300461 break;
462
463 case DWC3_CONFIGURED_STATE:
464 ret = dwc3_ep0_delegate_req(dwc, ctrl);
465 if (!cfg)
466 dwc->dev_state = DWC3_ADDRESS_STATE;
467 break;
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100468 default:
469 ret = -EINVAL;
Felipe Balbi72246da2011-08-19 18:10:58 +0300470 }
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100471 return ret;
Felipe Balbi72246da2011-08-19 18:10:58 +0300472}
473
474static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
475{
476 int ret;
477
478 switch (ctrl->bRequest) {
479 case USB_REQ_GET_STATUS:
480 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
481 ret = dwc3_ep0_handle_status(dwc, ctrl);
482 break;
483 case USB_REQ_CLEAR_FEATURE:
484 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
485 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
486 break;
487 case USB_REQ_SET_FEATURE:
488 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
489 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
490 break;
491 case USB_REQ_SET_ADDRESS:
492 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
493 ret = dwc3_ep0_set_address(dwc, ctrl);
494 break;
495 case USB_REQ_SET_CONFIGURATION:
496 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
497 ret = dwc3_ep0_set_config(dwc, ctrl);
498 break;
499 default:
500 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
501 ret = dwc3_ep0_delegate_req(dwc, ctrl);
502 break;
503 };
504
505 return ret;
506}
507
508static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
509 const struct dwc3_event_depevt *event)
510{
511 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
512 int ret;
513 u32 len;
514
515 if (!dwc->gadget_driver)
516 goto err;
517
518 len = le16_to_cpu(ctrl->wLength);
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300519 if (!len) {
Felipe Balbid95b09b2011-09-30 10:58:37 +0300520 dwc->three_stage_setup = false;
521 dwc->ep0_expect_in = false;
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300522 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
523 } else {
Felipe Balbid95b09b2011-09-30 10:58:37 +0300524 dwc->three_stage_setup = true;
525 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300526 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
527 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300528
529 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
530 ret = dwc3_ep0_std_request(dwc, ctrl);
531 else
532 ret = dwc3_ep0_delegate_req(dwc, ctrl);
533
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100534 if (ret == USB_GADGET_DELAYED_STATUS)
535 dwc->delayed_status = true;
536
Felipe Balbi72246da2011-08-19 18:10:58 +0300537 if (ret >= 0)
538 return;
539
540err:
541 dwc3_ep0_stall_and_restart(dwc);
542}
543
544static void dwc3_ep0_complete_data(struct dwc3 *dwc,
545 const struct dwc3_event_depevt *event)
546{
547 struct dwc3_request *r = NULL;
548 struct usb_request *ur;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200549 struct dwc3_trb *trb;
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200550 struct dwc3_ep *ep0;
Felipe Balbic611ccb2011-08-27 02:30:33 +0300551 u32 transferred;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200552 u32 length;
Felipe Balbi72246da2011-08-19 18:10:58 +0300553 u8 epnum;
554
555 epnum = event->endpoint_number;
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200556 ep0 = dwc->eps[0];
Felipe Balbi72246da2011-08-19 18:10:58 +0300557
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300558 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
559
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200560 r = next_request(&ep0->request_list);
Sebastian Andrzej Siewior8ee62702011-10-18 19:13:29 +0200561 ur = &r->request;
Felipe Balbi72246da2011-08-19 18:10:58 +0300562
Felipe Balbif6bafc62012-02-06 11:04:53 +0200563 trb = dwc->ep0_trb;
564 length = trb->size & DWC3_TRB_SIZE_MASK;
Felipe Balbi72246da2011-08-19 18:10:58 +0300565
Felipe Balbia6829702011-08-27 22:18:09 +0300566 if (dwc->ep0_bounced) {
Moiz Sonasath566ccdd2012-03-14 00:44:56 -0500567 unsigned transfer_size = ur->length;
568 unsigned maxp = ep0->endpoint.maxpacket;
569
570 transfer_size += (maxp - (transfer_size % maxp));
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300571 transferred = min_t(u32, ur->length,
Moiz Sonasath566ccdd2012-03-14 00:44:56 -0500572 transfer_size - length);
Felipe Balbia6829702011-08-27 22:18:09 +0300573 memcpy(ur->buf, dwc->ep0_bounce, transferred);
Felipe Balbia6829702011-08-27 22:18:09 +0300574 } else {
Felipe Balbif6bafc62012-02-06 11:04:53 +0200575 transferred = ur->length - length;
Felipe Balbia6829702011-08-27 22:18:09 +0300576 }
Felipe Balbi72246da2011-08-19 18:10:58 +0300577
Felipe Balbicd423dd2012-03-21 11:44:00 +0200578 ur->actual += transferred;
579
Felipe Balbi72246da2011-08-19 18:10:58 +0300580 if ((epnum & 1) && ur->actual < ur->length) {
581 /* for some reason we did not get everything out */
582
583 dwc3_ep0_stall_and_restart(dwc);
Felipe Balbi72246da2011-08-19 18:10:58 +0300584 } else {
585 /*
586 * handle the case where we have to send a zero packet. This
587 * seems to be case when req.length > maxpacket. Could it be?
588 */
Felipe Balbi72246da2011-08-19 18:10:58 +0300589 if (r)
Sebastian Andrzej Siewiorc2da2ff2011-10-20 19:04:16 +0200590 dwc3_gadget_giveback(ep0, r, 0);
Felipe Balbi72246da2011-08-19 18:10:58 +0300591 }
592}
593
594static void dwc3_ep0_complete_req(struct dwc3 *dwc,
595 const struct dwc3_event_depevt *event)
596{
597 struct dwc3_request *r;
598 struct dwc3_ep *dep;
Felipe Balbi72246da2011-08-19 18:10:58 +0300599
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300600 dep = dwc->eps[0];
Felipe Balbi72246da2011-08-19 18:10:58 +0300601
602 if (!list_empty(&dep->request_list)) {
603 r = next_request(&dep->request_list);
604
605 dwc3_gadget_giveback(dep, r, 0);
606 }
607
Gerard Cauvy3b637362012-02-10 12:21:18 +0200608 if (dwc->test_mode) {
609 int ret;
610
611 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
612 if (ret < 0) {
613 dev_dbg(dwc->dev, "Invalid Test #%d\n",
614 dwc->test_mode_nr);
615 dwc3_ep0_stall_and_restart(dwc);
616 }
617 }
618
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300619 dwc->ep0state = EP0_SETUP_PHASE;
Felipe Balbi72246da2011-08-19 18:10:58 +0300620 dwc3_ep0_out_start(dwc);
621}
622
623static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
624 const struct dwc3_event_depevt *event)
625{
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300626 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
627
628 dep->flags &= ~DWC3_EP_BUSY;
Paul Zimmermanc2df85c2012-02-24 17:32:18 -0800629 dep->res_trans_idx = 0;
Felipe Balbidf62df52011-10-14 15:11:49 +0300630 dwc->setup_packet_pending = false;
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300631
Felipe Balbi72246da2011-08-19 18:10:58 +0300632 switch (dwc->ep0state) {
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300633 case EP0_SETUP_PHASE:
634 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
Felipe Balbi72246da2011-08-19 18:10:58 +0300635 dwc3_ep0_inspect_setup(dwc, event);
636 break;
637
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300638 case EP0_DATA_PHASE:
639 dev_vdbg(dwc->dev, "Data Phase\n");
Felipe Balbi72246da2011-08-19 18:10:58 +0300640 dwc3_ep0_complete_data(dwc, event);
641 break;
642
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300643 case EP0_STATUS_PHASE:
644 dev_vdbg(dwc->dev, "Status Phase\n");
Felipe Balbi72246da2011-08-19 18:10:58 +0300645 dwc3_ep0_complete_req(dwc, event);
646 break;
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300647 default:
648 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
Felipe Balbi72246da2011-08-19 18:10:58 +0300649 }
650}
651
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300652static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
653 const struct dwc3_event_depevt *event)
654{
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300655 dwc3_ep0_out_start(dwc);
656}
657
658static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
659 const struct dwc3_event_depevt *event)
660{
661 struct dwc3_ep *dep;
662 struct dwc3_request *req;
663 int ret;
664
665 dep = dwc->eps[0];
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300666
667 if (list_empty(&dep->request_list)) {
668 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
669 dep->flags |= DWC3_EP_PENDING_REQUEST;
670
671 if (event->endpoint_number)
672 dep->flags |= DWC3_EP0_DIR_IN;
673 return;
674 }
675
676 req = next_request(&dep->request_list);
677 req->direction = !!event->endpoint_number;
678
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300679 if (req->request.length == 0) {
680 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
681 dwc->ctrl_req_addr, 0,
682 DWC3_TRBCTL_CONTROL_DATA);
683 } else if ((req->request.length % dep->endpoint.maxpacket)
684 && (event->endpoint_number == 0)) {
Felipe Balbi0fc9a1b2011-12-19 11:32:34 +0200685 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
686 event->endpoint_number);
687 if (ret) {
688 dev_dbg(dwc->dev, "failed to map request\n");
689 return;
690 }
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300691
692 WARN_ON(req->request.length > dep->endpoint.maxpacket);
693
694 dwc->ep0_bounced = true;
695
696 /*
697 * REVISIT in case request length is bigger than EP0
698 * wMaxPacketSize, we will need two chained TRBs to handle
699 * the transfer.
700 */
701 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
702 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
703 DWC3_TRBCTL_CONTROL_DATA);
704 } else {
Felipe Balbi0fc9a1b2011-12-19 11:32:34 +0200705 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
706 event->endpoint_number);
707 if (ret) {
708 dev_dbg(dwc->dev, "failed to map request\n");
709 return;
710 }
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300711
712 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
713 req->request.dma, req->request.length,
714 DWC3_TRBCTL_CONTROL_DATA);
715 }
716
717 WARN_ON(ret < 0);
718}
719
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100720static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300721{
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100722 struct dwc3 *dwc = dep->dwc;
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300723 u32 type;
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300724
725 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
726 : DWC3_TRBCTL_CONTROL_STATUS2;
727
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100728 return dwc3_ep0_start_trans(dwc, dep->number,
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300729 dwc->ctrl_req_addr, 0, type);
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100730}
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300731
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100732static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
733{
734 struct dwc3_ep *dep = dwc->eps[epnum];
735
Felipe Balbi457e84b2012-01-18 18:04:09 +0200736 if (dwc->resize_fifos) {
737 dev_dbg(dwc->dev, "starting to resize fifos\n");
738 dwc3_gadget_resize_tx_fifos(dwc);
739 dwc->resize_fifos = 0;
740 }
741
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100742 WARN_ON(dwc3_ep0_start_control_status(dep));
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300743}
744
Felipe Balbi72246da2011-08-19 18:10:58 +0300745static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
746 const struct dwc3_event_depevt *event)
747{
Felipe Balbidf62df52011-10-14 15:11:49 +0300748 dwc->setup_packet_pending = true;
749
Felipe Balbi9cc9bcd2011-10-18 18:00:26 +0300750 /*
751 * This part is very tricky: If we has just handled
752 * XferNotReady(Setup) and we're now expecting a
753 * XferComplete but, instead, we receive another
754 * XferNotReady(Setup), we should STALL and restart
755 * the state machine.
756 *
757 * In all other cases, we just continue waiting
758 * for the XferComplete event.
759 *
760 * We are a little bit unsafe here because we're
761 * not trying to ensure that last event was, indeed,
762 * XferNotReady(Setup).
763 *
764 * Still, we don't expect any condition where that
765 * should happen and, even if it does, it would be
766 * another error condition.
767 */
768 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
769 switch (event->status) {
770 case DEPEVT_STATUS_CONTROL_SETUP:
771 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
772 dwc3_ep0_stall_and_restart(dwc);
773 break;
774 case DEPEVT_STATUS_CONTROL_DATA:
775 /* FALLTHROUGH */
776 case DEPEVT_STATUS_CONTROL_STATUS:
777 /* FALLTHROUGH */
778 default:
779 dev_vdbg(dwc->dev, "waiting for XferComplete\n");
780 }
781
782 return;
783 }
784
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300785 switch (event->status) {
786 case DEPEVT_STATUS_CONTROL_SETUP:
787 dev_vdbg(dwc->dev, "Control Setup\n");
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100788
789 dwc->ep0state = EP0_SETUP_PHASE;
790
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300791 dwc3_ep0_do_control_setup(dwc, event);
Felipe Balbi72246da2011-08-19 18:10:58 +0300792 break;
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300793
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300794 case DEPEVT_STATUS_CONTROL_DATA:
795 dev_vdbg(dwc->dev, "Control Data\n");
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300796
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100797 dwc->ep0state = EP0_DATA_PHASE;
798
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300799 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
800 dev_vdbg(dwc->dev, "Expected %d got %d\n",
Felipe Balbi25355be2011-09-30 10:58:38 +0300801 dwc->ep0_next_event,
802 DWC3_EP0_NRDY_DATA);
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300803
804 dwc3_ep0_stall_and_restart(dwc);
805 return;
806 }
807
Felipe Balbi55f3fba2011-09-08 18:27:33 +0300808 /*
809 * One of the possible error cases is when Host _does_
810 * request for Data Phase, but it does so on the wrong
811 * direction.
812 *
813 * Here, we already know ep0_next_event is DATA (see above),
814 * so we only need to check for direction.
815 */
816 if (dwc->ep0_expect_in != event->endpoint_number) {
817 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
818 dwc3_ep0_stall_and_restart(dwc);
819 return;
820 }
821
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300822 dwc3_ep0_do_control_data(dwc, event);
Felipe Balbi72246da2011-08-19 18:10:58 +0300823 break;
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300824
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300825 case DEPEVT_STATUS_CONTROL_STATUS:
826 dev_vdbg(dwc->dev, "Control Status\n");
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300827
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100828 dwc->ep0state = EP0_STATUS_PHASE;
829
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300830 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
831 dev_vdbg(dwc->dev, "Expected %d got %d\n",
Felipe Balbi25355be2011-09-30 10:58:38 +0300832 dwc->ep0_next_event,
833 DWC3_EP0_NRDY_STATUS);
Felipe Balbi1ddcb212011-08-30 15:52:17 +0300834
835 dwc3_ep0_stall_and_restart(dwc);
836 return;
837 }
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100838
839 if (dwc->delayed_status) {
840 WARN_ON_ONCE(event->endpoint_number != 1);
841 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
842 return;
843 }
844
Sebastian Andrzej Siewiorf0f2b2a2011-11-02 13:30:44 +0100845 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
Felipe Balbi72246da2011-08-19 18:10:58 +0300846 }
847}
848
849void dwc3_ep0_interrupt(struct dwc3 *dwc,
Felipe Balbi8becf272011-11-04 12:40:05 +0200850 const struct dwc3_event_depevt *event)
Felipe Balbi72246da2011-08-19 18:10:58 +0300851{
852 u8 epnum = event->endpoint_number;
853
854 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
855 dwc3_ep_event_string(event->endpoint_event),
Sebastian Andrzej Siewiorb147f352011-09-30 10:58:40 +0300856 epnum >> 1, (epnum & 1) ? "in" : "out",
Felipe Balbi72246da2011-08-19 18:10:58 +0300857 dwc3_ep0_state_string(dwc->ep0state));
858
859 switch (event->endpoint_event) {
860 case DWC3_DEPEVT_XFERCOMPLETE:
861 dwc3_ep0_xfer_complete(dwc, event);
862 break;
863
864 case DWC3_DEPEVT_XFERNOTREADY:
865 dwc3_ep0_xfernotready(dwc, event);
866 break;
867
868 case DWC3_DEPEVT_XFERINPROGRESS:
869 case DWC3_DEPEVT_RXTXFIFOEVT:
870 case DWC3_DEPEVT_STREAMEVT:
871 case DWC3_DEPEVT_EPCMDCMPLT:
872 break;
873 }
874}