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Sathish Ambley9d69ac32012-03-21 10:28:26 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -070012
13/include/ "skeleton.dtsi"
David Collins153d45a2012-03-26 11:57:50 -070014/include/ "msm-pm8841.dtsi"
15/include/ "msm-pm8941.dtsi"
16/include/ "msmcopper-regulator.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -070017
18/ {
19 model = "Qualcomm MSM Copper";
Sathish Ambley9d69ac32012-03-21 10:28:26 -070020 compatible = "qcom,msmcopper";
Sathish Ambley4df614c2011-10-07 16:30:46 -070021 interrupt-parent = <&intc>;
22
23 intc: interrupt-controller@F9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -080026 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -070027 reg = <0xF9000000 0x1000>,
28 <0xF9002000 0x1000>;
29 };
Sathish Ambley3d50c762011-10-25 15:26:00 -070030
Michael Bohan0425f6f2012-01-17 14:36:39 -080031 msmgpio: gpio@fd400000 {
32 compatible = "qcom,msm-gpio";
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 reg = <0xfd400000 0x4000>;
36 };
37
Sathish Ambley098f9bd2011-11-09 16:32:53 -080038 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -070039 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Michael Bohanc7224532012-01-06 16:02:52 -080040 interrupts = <1 2 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -070041 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -080042 };
43
David Brown225abee2012-02-09 22:28:50 -080044 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -070045 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -080046 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080047 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -070048 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053049
Sathish Ambley9d69ac32012-03-21 10:28:26 -070050 serial@f995e000 {
51 compatible = "qcom,msm-lsuart-v14";
52 reg = <0xf995e000 0x1000>;
53 interrupts = <0 114 0>;
54 };
55
David Brown225abee2012-02-09 22:28:50 -080056 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053057 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -080058 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -080059 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -070060 HSUSB_VDDCX-supply = <&pm8841_s2>;
61 HSUSB_1p8-supply = <&pm8941_l6>;
62 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053063
64 qcom,hsusb-otg-phy-type = <2>;
65 qcom,hsusb-otg-mode = <1>;
66 qcom,hsusb-otg-otg-control = <1>;
67 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053068
David Brown225abee2012-02-09 22:28:50 -080069 qcom,sdcc@f980b000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053070 cell-index = <1>;
71 compatible = "qcom,msm-sdcc";
David Brown225abee2012-02-09 22:28:50 -080072 reg = <0xf980b000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080073 interrupts = <0 123 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053074
Subhash Jadavani56e0eaa2012-03-13 18:06:04 +053075 qcom,sdcc-clk-rates = <400000 24000000 48000000 96000000 192000000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053076 qcom,sdcc-sup-voltages = <3300 3300>;
77 qcom,sdcc-bus-width = <8>;
Subhash Jadavani56e0eaa2012-03-13 18:06:04 +053078 qcom,sdcc-hs200;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053079 qcom,sdcc-nonremovable;
80 qcom,sdcc-disable_cmd23;
81 };
82
David Brown225abee2012-02-09 22:28:50 -080083 qcom,sdcc@f984b000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053084 cell-index = <3>;
85 compatible = "qcom,msm-sdcc";
David Brown225abee2012-02-09 22:28:50 -080086 reg = <0xf984b000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080087 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053088
89 qcom,sdcc-clk-rates = <400000 24000000 48000000>;
90 qcom,sdcc-sup-voltages = <3300 3300>;
91 qcom,sdcc-bus-width = <4>;
92 qcom,sdcc-disable_cmd23;
93 };
Yan He1466daa2011-11-30 17:25:38 -080094
David Brown225abee2012-02-09 22:28:50 -080095 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -080096 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -080097 reg = <0xf9984000 0x15000>,
98 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -080099 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800100
101 qcom,bam-dma-res-pipes = <6>;
102 };
103
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700104 spi@f9924000 {
105 compatible = "qcom,spi-qup-v2";
106 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800107 interrupts = <0 96 0>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700108 spi-max-frequency = <24000000>;
109 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700110
Sagar Dhariaa316a962012-03-21 16:13:22 -0600111 slim@fe12f000 {
112 cell-index = <1>;
113 compatible = "qcom,slim-msm";
114 reg = <0xfe12f000 0x35000>,
115 <0xfe104000 0x20000>;
116 reg-names = "slimbus_physical", "slimbus_bam_physical";
117 interrupts = <0 163 0 0 164 0>;
118 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
119 qcom,min-clk-gear = <10>;
120 };
121
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700122 qcom,spmi@fc4c0000 {
123 cell-index = <0>;
124 compatible = "qcom,spmi-pmic-arb";
125 reg = <0xfc4cf000 0x1000>,
126 <0Xfc4cb000 0x1000>;
127 /* 190,ee0_krait_hlos_spmi_periph_irq */
128 /* 187,channel_0_krait_hlos_trans_done_irq */
129 interrupts = <0 190 0 0 187 0>;
130 qcom,pmic-arb-ee = <0>;
131 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700132 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
133 <0x13100001>, /* PM8941_LDO2 */
134 <0x13200002>, /* PM8941_LDO3 */
135 <0x13300003>, /* PM8941_LDO4 */
136 <0x13400004>, /* PM8941_LDO5 */
137 <0x13500005>, /* PM8941_LDO6 */
138 <0x13600006>, /* PM8941_LDO7 */
139 <0x13700007>, /* PM8941_LDO8 */
140 <0x13800008>, /* PM8941_LDO9 */
141 <0x13900009>, /* PM8941_LDO10 */
142 <0x13a0000a>, /* PM8941_LDO11 */
143 <0x13b0000b>, /* PM8941_LDO12 */
144 <0x13c0000c>, /* PM8941_LDO13 */
145 <0x13d0000d>, /* PM8941_LDO14 */
146 <0x13e0000e>, /* PM8941_LDO15 */
147 <0x13f0000f>, /* PM8941_LDO16 */
148 <0x14000010>, /* PM8941_LDO17 */
149 <0x14100011>, /* PM8941_LDO18 */
150 <0x14200012>, /* PM8941_LDO19 */
151 <0x14300013>, /* PM8941_LDO20 */
152 <0x14400014>, /* PM8941_LDO21 */
153 <0x14500015>, /* PM8941_LDO22 */
154 <0x14600016>, /* PM8941_LDO23 */
155 <0x14700017>, /* PM8941_LDO24 */
156 <0x14800018>, /* PM8941_LDO25 */
157 <0x14900019>, /* PM8941_LDO26 */
158 <0x0c00001a>, /* PM8941_GPIO1 */
159 <0x0c10001b>, /* PM8941_GPIO2 */
160 <0x0c20001c>, /* PM8941_GPIO3 */
161 <0x0c30001d>, /* PM8941_GPIO4 */
162 <0x0c40001e>, /* PM8941_GPIO5 */
163 <0x0c50001f>, /* PM8941_GPIO6 */
164 <0x0c600020>, /* PM8941_GPIO7 */
165 <0x0c700021>, /* PM8941_GPIO8 */
166 <0x0c800022>, /* PM8941_GPIO9 */
167 <0x0c900023>, /* PM8941_GPIO10 */
168 <0x0ca00024>, /* PM8941_GPIO11 */
169 <0x0cb00025>, /* PM8941_GPIO12 */
170 <0x0cc00026>, /* PM8941_GPIO13 */
171 <0x0cd00027>, /* PM8941_GPIO14 */
172 <0x0ce00028>, /* PM8941_GPIO15 */
173 <0x0cf00029>, /* PM8941_GPIO16 */
174 <0x0d00002a>, /* PM8941_GPIO17 */
175 <0x0d10002b>, /* PM8941_GPIO18 */
176 <0x0d20002c>, /* PM8941_GPIO19 */
177 <0x0d30002d>, /* PM8941_GPIO20 */
178 <0x0d40002e>, /* PM8941_GPIO21 */
179 <0x0d50002f>, /* PM8941_GPIO22 */
180 <0x0d600030>, /* PM8941_GPIO23 */
181 <0x0d700031>, /* PM8941_GPIO24 */
182 <0x0d800032>, /* PM8941_GPIO25 */
183 <0x0d900033>, /* PM8941_GPIO26 */
184 <0x0da00034>, /* PM8941_GPIO27 */
185 <0x0db00035>, /* PM8941_GPIO28 */
186 <0x0dc00036>, /* PM8941_GPIO29 */
187 <0x0dd00037>, /* PM8941_GPIO30 */
188 <0x0de00038>, /* PM8941_GPIO31 */
189 <0x0df00039>, /* PM8941_GPIO32 */
190 <0x0e00003a>, /* PM8941_GPIO33 */
191 <0x0e10003b>, /* PM8941_GPIO34 */
192 <0x0e20003c>, /* PM8941_GPIO35 */
193 <0x0e30003d>, /* PM8941_GPIO36 */
194 <0x0280003e>, /* COINCELL */
195 <0x0100003f>, /* SMBC_OVP */
196 <0x01100040>, /* SMBC_CHG */
197 <0x01200041>, /* SMBC_BIF */
198 <0x00500042>, /* INTERRUPT */
199 <0x00100043>, /* PM8941_0 */
200 <0x20100044>, /* PM8841_0 */
201 <0x10100045>, /* PM8941_1 */
202 <0x30100046>, /* PM8841_1 */
203 <0x00800047>, /* PON0 */
204 <0x20800048>, /* PON1 */
205 <0x11000049>, /* PM8941_SMPS1 */
206 <0x1110004a>, /* PM8941_SMPS2 */
207 <0x1120004b>, /* PM8941_SMPS3 */
208 <0x3100004c>, /* PM8841_SMPS1 */
209 <0x3110004d>, /* PM8841_SMPS2 */
210 <0x3120004e>, /* PM8841_SMPS3 */
211 <0x3130004f>, /* PM8841_SMPS4 */
212 <0x31400050>, /* PM8841_SMPS5 */
213 <0x31500051>, /* PM8841_SMPS6 */
214 <0x31600052>, /* PM8841_SMPS7 */
215 <0x31700053>, /* PM8841_SMPS8 */
216 <0x05000054>, /* SHARED_XO */
217 <0x05100055>, /* BB_CLK1 */
218 <0x05200056>, /* BB_CLK2 */
219 <0x05900057>, /* SLEEP_CLK */
220 <0x07000058>, /* PBS_CORE */
221 <0x07100059>, /* PBS_CLIENT1 */
222 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700223 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700224
225 i2c@f9966000 {
226 cell-index = <0>;
227 compatible = "qcom,i2c-qup";
228 reg = <0Xf9966000 0x1000>;
229 reg-names = "qup_phys_addr";
230 interrupts = <0 104 0>;
231 interrupt-names = "qup_err_intr";
232 qcom,i2c-bus-freq = <100000>;
233 qcom,i2c-src-freq = <24000000>;
234 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800235
236 qcom,acpuclk@0xf900000 {
237 compatible = "qcom,acpuclk-copper";
238 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200239
240 qcom,ssusb@F9200000 {
241 compatible = "qcom,dwc-usb3-msm";
242 reg = <0xF9200000 0xCCFF>;
243 interrupts = <0 131 0>;
244 qcom,dwc-usb3-msm-dbm-eps = <4>;
245 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700246};