| Jordan Crouse | 156cfbc | 2012-01-24 09:32:04 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2002,2007-2012, Code Aurora Forum. All rights reserved. |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __A200_REG_H |
| 14 | #define __A200_REG_H |
| 15 | |
| 16 | enum VGT_EVENT_TYPE { |
| 17 | VS_DEALLOC = 0, |
| 18 | PS_DEALLOC = 1, |
| 19 | VS_DONE_TS = 2, |
| 20 | PS_DONE_TS = 3, |
| 21 | CACHE_FLUSH_TS = 4, |
| 22 | CONTEXT_DONE = 5, |
| 23 | CACHE_FLUSH = 6, |
| 24 | VIZQUERY_START = 7, |
| 25 | VIZQUERY_END = 8, |
| 26 | SC_WAIT_WC = 9, |
| 27 | RST_PIX_CNT = 13, |
| 28 | RST_VTX_CNT = 14, |
| 29 | TILE_FLUSH = 15, |
| 30 | CACHE_FLUSH_AND_INV_TS_EVENT = 20, |
| 31 | ZPASS_DONE = 21, |
| 32 | CACHE_FLUSH_AND_INV_EVENT = 22, |
| 33 | PERFCOUNTER_START = 23, |
| 34 | PERFCOUNTER_STOP = 24, |
| 35 | VS_FETCH_DONE = 27, |
| 36 | FACENESS_FLUSH = 28, |
| 37 | }; |
| 38 | |
| 39 | enum COLORFORMATX { |
| 40 | COLORX_4_4_4_4 = 0, |
| 41 | COLORX_1_5_5_5 = 1, |
| 42 | COLORX_5_6_5 = 2, |
| 43 | COLORX_8 = 3, |
| 44 | COLORX_8_8 = 4, |
| 45 | COLORX_8_8_8_8 = 5, |
| 46 | COLORX_S8_8_8_8 = 6, |
| 47 | COLORX_16_FLOAT = 7, |
| 48 | COLORX_16_16_FLOAT = 8, |
| 49 | COLORX_16_16_16_16_FLOAT = 9, |
| 50 | COLORX_32_FLOAT = 10, |
| 51 | COLORX_32_32_FLOAT = 11, |
| 52 | COLORX_32_32_32_32_FLOAT = 12, |
| 53 | COLORX_2_3_3 = 13, |
| 54 | COLORX_8_8_8 = 14, |
| 55 | }; |
| 56 | |
| 57 | enum SURFACEFORMAT { |
| 58 | FMT_1_REVERSE = 0, |
| 59 | FMT_1 = 1, |
| 60 | FMT_8 = 2, |
| 61 | FMT_1_5_5_5 = 3, |
| 62 | FMT_5_6_5 = 4, |
| 63 | FMT_6_5_5 = 5, |
| 64 | FMT_8_8_8_8 = 6, |
| 65 | FMT_2_10_10_10 = 7, |
| 66 | FMT_8_A = 8, |
| 67 | FMT_8_B = 9, |
| 68 | FMT_8_8 = 10, |
| 69 | FMT_Cr_Y1_Cb_Y0 = 11, |
| 70 | FMT_Y1_Cr_Y0_Cb = 12, |
| 71 | FMT_5_5_5_1 = 13, |
| 72 | FMT_8_8_8_8_A = 14, |
| 73 | FMT_4_4_4_4 = 15, |
| 74 | FMT_10_11_11 = 16, |
| 75 | FMT_11_11_10 = 17, |
| 76 | FMT_DXT1 = 18, |
| 77 | FMT_DXT2_3 = 19, |
| 78 | FMT_DXT4_5 = 20, |
| 79 | FMT_24_8 = 22, |
| 80 | FMT_24_8_FLOAT = 23, |
| 81 | FMT_16 = 24, |
| 82 | FMT_16_16 = 25, |
| 83 | FMT_16_16_16_16 = 26, |
| 84 | FMT_16_EXPAND = 27, |
| 85 | FMT_16_16_EXPAND = 28, |
| 86 | FMT_16_16_16_16_EXPAND = 29, |
| 87 | FMT_16_FLOAT = 30, |
| 88 | FMT_16_16_FLOAT = 31, |
| 89 | FMT_16_16_16_16_FLOAT = 32, |
| 90 | FMT_32 = 33, |
| 91 | FMT_32_32 = 34, |
| 92 | FMT_32_32_32_32 = 35, |
| 93 | FMT_32_FLOAT = 36, |
| 94 | FMT_32_32_FLOAT = 37, |
| 95 | FMT_32_32_32_32_FLOAT = 38, |
| 96 | FMT_32_AS_8 = 39, |
| 97 | FMT_32_AS_8_8 = 40, |
| 98 | FMT_16_MPEG = 41, |
| 99 | FMT_16_16_MPEG = 42, |
| 100 | FMT_8_INTERLACED = 43, |
| 101 | FMT_32_AS_8_INTERLACED = 44, |
| 102 | FMT_32_AS_8_8_INTERLACED = 45, |
| 103 | FMT_16_INTERLACED = 46, |
| 104 | FMT_16_MPEG_INTERLACED = 47, |
| 105 | FMT_16_16_MPEG_INTERLACED = 48, |
| 106 | FMT_DXN = 49, |
| 107 | FMT_8_8_8_8_AS_16_16_16_16 = 50, |
| 108 | FMT_DXT1_AS_16_16_16_16 = 51, |
| 109 | FMT_DXT2_3_AS_16_16_16_16 = 52, |
| 110 | FMT_DXT4_5_AS_16_16_16_16 = 53, |
| 111 | FMT_2_10_10_10_AS_16_16_16_16 = 54, |
| 112 | FMT_10_11_11_AS_16_16_16_16 = 55, |
| 113 | FMT_11_11_10_AS_16_16_16_16 = 56, |
| 114 | FMT_32_32_32_FLOAT = 57, |
| 115 | FMT_DXT3A = 58, |
| 116 | FMT_DXT5A = 59, |
| 117 | FMT_CTX1 = 60, |
| 118 | FMT_DXT3A_AS_1_1_1_1 = 61 |
| 119 | }; |
| 120 | |
| 121 | #define REG_PERF_MODE_CNT 0x0 |
| 122 | #define REG_PERF_STATE_RESET 0x0 |
| 123 | #define REG_PERF_STATE_ENABLE 0x1 |
| 124 | #define REG_PERF_STATE_FREEZE 0x2 |
| 125 | |
| 126 | #define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 |
| 127 | #define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 |
| 128 | #define RB_EDRAM_INFO_UNUSED0_SIZE 8 |
| 129 | #define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 |
| 130 | |
| 131 | struct rb_edram_info_t { |
| 132 | unsigned int edram_size:RB_EDRAM_INFO_EDRAM_SIZE_SIZE; |
| 133 | unsigned int edram_mapping_mode:RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; |
| 134 | unsigned int unused0:RB_EDRAM_INFO_UNUSED0_SIZE; |
| 135 | unsigned int edram_range:RB_EDRAM_INFO_EDRAM_RANGE_SIZE; |
| 136 | }; |
| 137 | |
| 138 | union reg_rb_edram_info { |
| 139 | unsigned int val; |
| 140 | struct rb_edram_info_t f; |
| 141 | }; |
| 142 | |
| Jeremy Gebben | 22784c2 | 2012-03-07 16:02:08 -0700 | [diff] [blame] | 143 | #define RBBM_READ_ERROR_ADDRESS_MASK 0x0001fffc |
| 144 | #define RBBM_READ_ERROR_REQUESTER (1<<30) |
| 145 | #define RBBM_READ_ERROR_ERROR (1<<31) |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 146 | |
| 147 | #define CP_RB_CNTL_RB_BUFSZ_SIZE 6 |
| 148 | #define CP_RB_CNTL_UNUSED0_SIZE 2 |
| 149 | #define CP_RB_CNTL_RB_BLKSZ_SIZE 6 |
| 150 | #define CP_RB_CNTL_UNUSED1_SIZE 2 |
| 151 | #define CP_RB_CNTL_BUF_SWAP_SIZE 2 |
| 152 | #define CP_RB_CNTL_UNUSED2_SIZE 2 |
| 153 | #define CP_RB_CNTL_RB_POLL_EN_SIZE 1 |
| 154 | #define CP_RB_CNTL_UNUSED3_SIZE 6 |
| 155 | #define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 |
| 156 | #define CP_RB_CNTL_UNUSED4_SIZE 3 |
| 157 | #define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 |
| 158 | |
| 159 | struct cp_rb_cntl_t { |
| 160 | unsigned int rb_bufsz:CP_RB_CNTL_RB_BUFSZ_SIZE; |
| 161 | unsigned int unused0:CP_RB_CNTL_UNUSED0_SIZE; |
| 162 | unsigned int rb_blksz:CP_RB_CNTL_RB_BLKSZ_SIZE; |
| 163 | unsigned int unused1:CP_RB_CNTL_UNUSED1_SIZE; |
| 164 | unsigned int buf_swap:CP_RB_CNTL_BUF_SWAP_SIZE; |
| 165 | unsigned int unused2:CP_RB_CNTL_UNUSED2_SIZE; |
| 166 | unsigned int rb_poll_en:CP_RB_CNTL_RB_POLL_EN_SIZE; |
| 167 | unsigned int unused3:CP_RB_CNTL_UNUSED3_SIZE; |
| 168 | unsigned int rb_no_update:CP_RB_CNTL_RB_NO_UPDATE_SIZE; |
| 169 | unsigned int unused4:CP_RB_CNTL_UNUSED4_SIZE; |
| 170 | unsigned int rb_rptr_wr_ena:CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; |
| 171 | }; |
| 172 | |
| 173 | union reg_cp_rb_cntl { |
| 174 | unsigned int val:32; |
| 175 | struct cp_rb_cntl_t f; |
| 176 | }; |
| 177 | |
| 178 | #define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL |
| 179 | #define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 |
| 180 | |
| 181 | |
| 182 | #define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L |
| 183 | #define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L |
| 184 | |
| 185 | #define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L |
| 186 | #define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L |
| 187 | #define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L |
| 188 | |
| 189 | #define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL |
| 190 | #define RBBM_STATUS__TC_BUSY_MASK 0x00000020L |
| 191 | #define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L |
| 192 | #define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L |
| 193 | #define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L |
| 194 | #define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L |
| 195 | #define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L |
| 196 | #define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L |
| 197 | #define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L |
| 198 | #define RBBM_STATUS__MH_BUSY_MASK 0x00040000L |
| 199 | #define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L |
| 200 | #define RBBM_STATUS__SX_BUSY_MASK 0x00200000L |
| 201 | #define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L |
| 202 | #define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L |
| 203 | #define RBBM_STATUS__PA_BUSY_MASK 0x02000000L |
| 204 | #define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L |
| 205 | #define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L |
| 206 | #define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L |
| 207 | #define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L |
| 208 | #define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
| 209 | |
| 210 | #define CP_INT_CNTL__SW_INT_MASK 0x00080000L |
| 211 | #define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L |
| 212 | #define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L |
| 213 | #define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L |
| 214 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L |
| 215 | #define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L |
| 216 | #define CP_INT_CNTL__IB2_INT_MASK 0x20000000L |
| 217 | #define CP_INT_CNTL__IB1_INT_MASK 0x40000000L |
| 218 | #define CP_INT_CNTL__RB_INT_MASK 0x80000000L |
| 219 | |
| 220 | #define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L |
| 221 | #define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L |
| 222 | #define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L |
| 223 | #define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L |
| 224 | |
| 225 | #define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL |
| 226 | #define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L |
| 227 | |
| 228 | #define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 |
| 229 | #define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 |
| 230 | #define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 |
| 231 | #define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 |
| 232 | #define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a |
| 233 | #define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d |
| 234 | #define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e |
| 235 | #define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f |
| 236 | #define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 |
| 237 | #define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 |
| 238 | #define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 |
| 239 | #define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 |
| 240 | #define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 |
| 241 | #define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a |
| 242 | |
| 243 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 |
| 244 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 |
| 245 | #define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 |
| 246 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b |
| 247 | |
| 248 | #define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 |
| 249 | #define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 |
| 250 | #define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e |
| 251 | |
| 252 | #define REG_CP_CSQ_IB1_STAT 0x01FE |
| 253 | #define REG_CP_CSQ_IB2_STAT 0x01FF |
| 254 | #define REG_CP_CSQ_RB_STAT 0x01FD |
| 255 | #define REG_CP_DEBUG 0x01FC |
| 256 | #define REG_CP_IB1_BASE 0x0458 |
| 257 | #define REG_CP_IB1_BUFSZ 0x0459 |
| 258 | #define REG_CP_IB2_BASE 0x045A |
| 259 | #define REG_CP_IB2_BUFSZ 0x045B |
| 260 | #define REG_CP_INT_ACK 0x01F4 |
| 261 | #define REG_CP_INT_CNTL 0x01F2 |
| 262 | #define REG_CP_INT_STATUS 0x01F3 |
| 263 | #define REG_CP_ME_CNTL 0x01F6 |
| 264 | #define REG_CP_ME_RAM_DATA 0x01FA |
| 265 | #define REG_CP_ME_RAM_WADDR 0x01F8 |
| Jordan Crouse | 0c2761a | 2012-02-01 22:11:12 -0700 | [diff] [blame] | 266 | #define REG_CP_ME_RAM_RADDR 0x01F9 |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 267 | #define REG_CP_ME_STATUS 0x01F7 |
| 268 | #define REG_CP_PFP_UCODE_ADDR 0x00C0 |
| 269 | #define REG_CP_PFP_UCODE_DATA 0x00C1 |
| 270 | #define REG_CP_QUEUE_THRESHOLDS 0x01D5 |
| 271 | #define REG_CP_RB_BASE 0x01C0 |
| 272 | #define REG_CP_RB_CNTL 0x01C1 |
| 273 | #define REG_CP_RB_RPTR 0x01C4 |
| 274 | #define REG_CP_RB_RPTR_ADDR 0x01C3 |
| 275 | #define REG_CP_RB_RPTR_WR 0x01C7 |
| 276 | #define REG_CP_RB_WPTR 0x01C5 |
| 277 | #define REG_CP_RB_WPTR_BASE 0x01C8 |
| 278 | #define REG_CP_RB_WPTR_DELAY 0x01C6 |
| 279 | #define REG_CP_STAT 0x047F |
| 280 | #define REG_CP_STATE_DEBUG_DATA 0x01ED |
| 281 | #define REG_CP_STATE_DEBUG_INDEX 0x01EC |
| 282 | #define REG_CP_ST_BASE 0x044D |
| 283 | #define REG_CP_ST_BUFSZ 0x044E |
| 284 | |
| 285 | #define REG_CP_PERFMON_CNTL 0x0444 |
| 286 | #define REG_CP_PERFCOUNTER_SELECT 0x0445 |
| 287 | #define REG_CP_PERFCOUNTER_LO 0x0446 |
| 288 | #define REG_CP_PERFCOUNTER_HI 0x0447 |
| 289 | |
| 290 | #define REG_RBBM_PERFCOUNTER1_SELECT 0x0395 |
| 291 | #define REG_RBBM_PERFCOUNTER1_HI 0x0398 |
| 292 | #define REG_RBBM_PERFCOUNTER1_LO 0x0397 |
| 293 | |
| 294 | #define REG_MASTER_INT_SIGNAL 0x03B7 |
| 295 | |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 296 | #define REG_PA_CL_VPORT_XSCALE 0x210F |
| 297 | #define REG_PA_CL_VPORT_ZOFFSET 0x2114 |
| 298 | #define REG_PA_CL_VPORT_ZSCALE 0x2113 |
| 299 | #define REG_PA_CL_CLIP_CNTL 0x2204 |
| 300 | #define REG_PA_CL_VTE_CNTL 0x2206 |
| 301 | #define REG_PA_SC_AA_MASK 0x2312 |
| 302 | #define REG_PA_SC_LINE_CNTL 0x2300 |
| 303 | #define REG_PA_SC_SCREEN_SCISSOR_BR 0x200F |
| 304 | #define REG_PA_SC_SCREEN_SCISSOR_TL 0x200E |
| 305 | #define REG_PA_SC_VIZ_QUERY 0x2293 |
| 306 | #define REG_PA_SC_VIZ_QUERY_STATUS 0x0C44 |
| 307 | #define REG_PA_SC_WINDOW_OFFSET 0x2080 |
| 308 | #define REG_PA_SC_WINDOW_SCISSOR_BR 0x2082 |
| 309 | #define REG_PA_SC_WINDOW_SCISSOR_TL 0x2081 |
| 310 | #define REG_PA_SU_FACE_DATA 0x0C86 |
| 311 | #define REG_PA_SU_POINT_SIZE 0x2280 |
| 312 | #define REG_PA_SU_LINE_CNTL 0x2282 |
| 313 | #define REG_PA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 |
| 314 | #define REG_PA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 |
| 315 | #define REG_PA_SU_SC_MODE_CNTL 0x2205 |
| 316 | |
| 317 | #define REG_PC_INDEX_OFFSET 0x2102 |
| 318 | |
| 319 | #define REG_RBBM_CNTL 0x003B |
| 320 | #define REG_RBBM_INT_ACK 0x03B6 |
| 321 | #define REG_RBBM_INT_CNTL 0x03B4 |
| 322 | #define REG_RBBM_INT_STATUS 0x03B5 |
| 323 | #define REG_RBBM_PATCH_RELEASE 0x0001 |
| 324 | #define REG_RBBM_PERIPHID1 0x03F9 |
| 325 | #define REG_RBBM_PERIPHID2 0x03FA |
| 326 | #define REG_RBBM_DEBUG 0x039B |
| 327 | #define REG_RBBM_DEBUG_OUT 0x03A0 |
| 328 | #define REG_RBBM_DEBUG_CNTL 0x03A1 |
| 329 | #define REG_RBBM_PM_OVERRIDE1 0x039C |
| 330 | #define REG_RBBM_PM_OVERRIDE2 0x039D |
| 331 | #define REG_RBBM_READ_ERROR 0x03B3 |
| 332 | #define REG_RBBM_SOFT_RESET 0x003C |
| 333 | #define REG_RBBM_STATUS 0x05D0 |
| 334 | |
| 335 | #define REG_RB_COLORCONTROL 0x2202 |
| 336 | #define REG_RB_COLOR_DEST_MASK 0x2326 |
| 337 | #define REG_RB_COLOR_MASK 0x2104 |
| 338 | #define REG_RB_COPY_CONTROL 0x2318 |
| 339 | #define REG_RB_DEPTHCONTROL 0x2200 |
| 340 | #define REG_RB_EDRAM_INFO 0x0F02 |
| 341 | #define REG_RB_MODECONTROL 0x2208 |
| 342 | #define REG_RB_SURFACE_INFO 0x2000 |
| 343 | #define REG_RB_SAMPLE_POS 0x220a |
| 344 | |
| 345 | #define REG_SCRATCH_ADDR 0x01DD |
| 346 | #define REG_SCRATCH_REG0 0x0578 |
| 347 | #define REG_SCRATCH_REG2 0x057A |
| 348 | #define REG_SCRATCH_UMSK 0x01DC |
| 349 | |
| 350 | #define REG_SQ_CF_BOOLEANS 0x4900 |
| 351 | #define REG_SQ_CF_LOOP 0x4908 |
| 352 | #define REG_SQ_GPR_MANAGEMENT 0x0D00 |
| Jeremy Gebben | 5bb7ece | 2011-08-02 11:04:48 -0600 | [diff] [blame] | 353 | #define REG_SQ_FLOW_CONTROL 0x0D01 |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 354 | #define REG_SQ_INST_STORE_MANAGMENT 0x0D02 |
| 355 | #define REG_SQ_INT_ACK 0x0D36 |
| 356 | #define REG_SQ_INT_CNTL 0x0D34 |
| 357 | #define REG_SQ_INT_STATUS 0x0D35 |
| 358 | #define REG_SQ_PROGRAM_CNTL 0x2180 |
| 359 | #define REG_SQ_PS_PROGRAM 0x21F6 |
| 360 | #define REG_SQ_VS_PROGRAM 0x21F7 |
| 361 | #define REG_SQ_WRAPPING_0 0x2183 |
| 362 | #define REG_SQ_WRAPPING_1 0x2184 |
| 363 | |
| 364 | #define REG_VGT_ENHANCE 0x2294 |
| 365 | #define REG_VGT_INDX_OFFSET 0x2102 |
| 366 | #define REG_VGT_MAX_VTX_INDX 0x2100 |
| 367 | #define REG_VGT_MIN_VTX_INDX 0x2101 |
| 368 | |
| 369 | #define REG_TP0_CHICKEN 0x0E1E |
| 370 | #define REG_TC_CNTL_STATUS 0x0E00 |
| 371 | #define REG_PA_SC_AA_CONFIG 0x2301 |
| 372 | #define REG_VGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 |
| 373 | #define REG_SQ_INTERPOLATOR_CNTL 0x2182 |
| 374 | #define REG_RB_DEPTH_INFO 0x2002 |
| 375 | #define REG_COHER_DEST_BASE_0 0x2006 |
| 376 | #define REG_RB_FOG_COLOR 0x2109 |
| 377 | #define REG_RB_STENCILREFMASK_BF 0x210C |
| 378 | #define REG_PA_SC_LINE_STIPPLE 0x2283 |
| 379 | #define REG_SQ_PS_CONST 0x2308 |
| 380 | #define REG_RB_DEPTH_CLEAR 0x231D |
| 381 | #define REG_RB_SAMPLE_COUNT_CTL 0x2324 |
| 382 | #define REG_SQ_CONSTANT_0 0x4000 |
| 383 | #define REG_SQ_FETCH_0 0x4800 |
| 384 | |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 385 | #define REG_COHER_BASE_PM4 0xA2A |
| 386 | #define REG_COHER_STATUS_PM4 0xA2B |
| 387 | #define REG_COHER_SIZE_PM4 0xA29 |
| 388 | |
| Jeremy Gebben | eebc461 | 2011-08-31 10:15:21 -0700 | [diff] [blame] | 389 | /*registers added in adreno220*/ |
| 390 | #define REG_A220_PC_INDX_OFFSET REG_VGT_INDX_OFFSET |
| 391 | #define REG_A220_PC_VERTEX_REUSE_BLOCK_CNTL REG_VGT_VERTEX_REUSE_BLOCK_CNTL |
| 392 | #define REG_A220_PC_MAX_VTX_INDX REG_VGT_MAX_VTX_INDX |
| 393 | #define REG_A220_RB_LRZ_VSC_CONTROL 0x2209 |
| 394 | #define REG_A220_GRAS_CONTROL 0x2210 |
| 395 | #define REG_A220_VSC_BIN_SIZE 0x0C01 |
| 396 | #define REG_A220_VSC_PIPE_DATA_LENGTH_7 0x0C1D |
| 397 | |
| Jeremy Gebben | 99105cb | 2011-08-31 10:23:05 -0700 | [diff] [blame] | 398 | /*registers added in adreno225*/ |
| 399 | #define REG_A225_RB_COLOR_INFO3 0x2005 |
| 400 | #define REG_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x2103 |
| 401 | #define REG_A225_GRAS_UCP0X 0x2340 |
| Jeremy Gebben | e139a04 | 2011-11-17 16:20:41 -0700 | [diff] [blame] | 402 | #define REG_A225_GRAS_UCP5W 0x2357 |
| Jeremy Gebben | 99105cb | 2011-08-31 10:23:05 -0700 | [diff] [blame] | 403 | #define REG_A225_GRAS_UCP_ENABLED 0x2360 |
| 404 | |
| Jordan Crouse | 156cfbc | 2012-01-24 09:32:04 -0700 | [diff] [blame] | 405 | /* Debug registers used by snapshot */ |
| 406 | #define REG_PA_SU_DEBUG_CNTL 0x0C80 |
| 407 | #define REG_PA_SU_DEBUG_DATA 0x0C81 |
| 408 | #define REG_RB_DEBUG_CNTL 0x0F26 |
| 409 | #define REG_RB_DEBUG_DATA 0x0F27 |
| 410 | #define REG_PC_DEBUG_CNTL 0x0C38 |
| 411 | #define REG_PC_DEBUG_DATA 0x0C39 |
| 412 | #define REG_GRAS_DEBUG_CNTL 0x0C80 |
| 413 | #define REG_GRAS_DEBUG_DATA 0x0C81 |
| 414 | #define REG_SQ_DEBUG_MISC 0x0D05 |
| 415 | #define REG_SQ_DEBUG_INPUT_FSM 0x0DAE |
| 416 | #define REG_SQ_DEBUG_CONST_MGR_FSM 0x0DAF |
| 417 | #define REG_SQ_DEBUG_EXP_ALLOC 0x0DB3 |
| 418 | #define REG_SQ_DEBUG_FSM_ALU_0 0x0DB1 |
| 419 | #define REG_SQ_DEBUG_FSM_ALU_1 0x0DB2 |
| 420 | #define REG_SQ_DEBUG_PTR_BUFF 0x0DB4 |
| 421 | #define REG_SQ_DEBUG_GPR_VTX 0x0DB5 |
| 422 | #define REG_SQ_DEBUG_GPR_PIX 0x0DB6 |
| 423 | #define REG_SQ_DEBUG_TB_STATUS_SEL 0x0DB7 |
| 424 | #define REG_SQ_DEBUG_VTX_TB_0 0x0DB8 |
| 425 | #define REG_SQ_DEBUG_VTX_TB_1 0x0DB9 |
| 426 | #define REG_SQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB |
| 427 | #define REG_SQ_DEBUG_TP_FSM 0x0DB0 |
| 428 | #define REG_SQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA |
| 429 | #define REG_SQ_DEBUG_PIX_TB_0 0x0DBC |
| 430 | #define REG_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD |
| 431 | #define REG_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE |
| 432 | #define REG_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF |
| 433 | #define REG_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 |
| 434 | #define REG_SQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 |
| 435 | #define REG_SQ_DEBUG_MISC_0 0x2309 |
| 436 | #define REG_SQ_DEBUG_MISC_1 0x230A |
| 437 | |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 438 | #endif /* __A200_REG_H */ |