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review.evervolv.com / android_kernel_htc_msm8960 / f20e42205ab172cfd449c10e5183e2e371a629d6 / . / drivers / video / omap2 / dss / dispc.c
blob: 79c1c0a44f817e8073ec844a044ad28c6a595983 [file] [log] [blame]
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
Tomi Valkeinenab83b142010-06-09 15:31:01 +0300[diff] [blame]34#include <linux/hardirq.h>
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]35#include <linux/interrupt.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]36
37#include <plat/sram.h>
38#include <plat/clock.h>
39
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +0300[diff] [blame]40#include <video/omapdss.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]41
42#include "dss.h"
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]43#include "dss_features.h"
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]44#include "dispc.h"
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]45
46/* DISPC */
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]47#define DISPC_SZ_REGS SZ_4K
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]48
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]64struct dispc_h_coef {
65 s8 hc4;
66 s8 hc3;
67 u8 hc2;
68 s8 hc1;
69 s8 hc0;
70};
71
72struct dispc_v_coef {
73 s8 vc22;
74 s8 vc2;
75 u8 vc1;
76 s8 vc0;
77 s8 vc00;
78};
79
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]80#define REG_GET(idx, start, end) \
81 FLD_GET(dispc_read_reg(idx), start, end)
82
83#define REG_FLD_MOD(idx, val, start, end) \
84 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
85
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]86struct dispc_irq_stats {
87 unsigned long last_reset;
88 unsigned irq_count;
89 unsigned irqs[32];
90};
91
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]92static struct {
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]93 struct platform_device *pdev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]94 void __iomem *base;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]95 int irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]96
97 u32 fifo_size[3];
98
99 spinlock_t irq_lock;
100 u32 irq_error_mask;
101 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
102 u32 error_irqs;
103 struct work_struct error_work;
104
105 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]106
107#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
108 spinlock_t irq_stats_lock;
109 struct dispc_irq_stats irq_stats;
110#endif
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]111} dispc;
112
113static void _omap_dispc_set_irqs(void);
114
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]115static inline void dispc_write_reg(const u16 idx, u32 val)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]116{
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]117 __raw_writel(val, dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]118}
119
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]120static inline u32 dispc_read_reg(const u16 idx)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]121{
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]122 return __raw_readl(dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]123}
124
125#define SR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]126 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]127#define RR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530[diff] [blame]128 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]129
130void dispc_save_context(void)
131{
132 if (cpu_is_omap24xx())
133 return;
134
135 SR(SYSCONFIG);
136 SR(IRQENABLE);
137 SR(CONTROL);
138 SR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]139 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
140 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
141 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
142 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]143 SR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]144 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
145 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
146 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
147 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]148 SR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]149 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
150 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]151 if (dss_has_feature(FEAT_MGR_LCD2)) {
152 SR(CONTROL2);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]153 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
154 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
155 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
156 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
157 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
158 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
159 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]160 SR(CONFIG2);
161 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]162
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]163 SR(OVL_BA0(OMAP_DSS_GFX));
164 SR(OVL_BA1(OMAP_DSS_GFX));
165 SR(OVL_POSITION(OMAP_DSS_GFX));
166 SR(OVL_SIZE(OMAP_DSS_GFX));
167 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
168 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
169 SR(OVL_ROW_INC(OMAP_DSS_GFX));
170 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
171 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
172 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]173
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]174 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
175 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
176 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]177
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]178 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
179 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
180 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]181 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]182 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
183 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
184 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]185
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]186 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
187 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
188 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]189 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]190
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]191 SR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]192
193 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]194 SR(OVL_BA0(OMAP_DSS_VIDEO1));
195 SR(OVL_BA1(OMAP_DSS_VIDEO1));
196 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
197 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
198 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
199 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
200 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
201 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
202 SR(OVL_FIR(OMAP_DSS_VIDEO1));
203 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
204 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
205 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]206
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]207 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
208 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
209 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
210 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
211 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
212 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
213 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
214 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]215
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]216 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
217 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
218 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
219 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
220 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
221 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
222 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
223 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]224
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]225 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
226 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
227 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
228 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
229 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]230
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]231 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
232 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
233 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
234 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
235 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
236 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
237 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
238 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]239
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]240 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]241
242 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]243 SR(OVL_BA0(OMAP_DSS_VIDEO2));
244 SR(OVL_BA1(OMAP_DSS_VIDEO2));
245 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
246 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
247 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
248 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
249 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
250 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
251 SR(OVL_FIR(OMAP_DSS_VIDEO2));
252 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
253 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
254 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]255
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]256 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
257 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
258 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
259 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
260 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
261 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
262 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
263 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]264
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]265 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
266 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
267 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
268 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
269 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
270 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
271 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
272 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]273
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]274 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
275 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
276 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
277 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
278 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]279
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]280 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
281 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
282 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
283 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
284 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
285 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
286 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
287 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]288
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]289 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]290
291 if (dss_has_feature(FEAT_CORE_CLK_DIV))
292 SR(DIVISOR);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]293}
294
295void dispc_restore_context(void)
296{
297 RR(SYSCONFIG);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200[diff] [blame]298 /*RR(IRQENABLE);*/
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]299 /*RR(CONTROL);*/
300 RR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]301 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
302 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
303 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
304 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]305 RR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]306 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
307 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
308 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
309 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]310 RR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]311 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
312 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]313 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]314 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
315 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
316 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
317 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
318 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
319 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
320 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]321 RR(CONFIG2);
322 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]323
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]324 RR(OVL_BA0(OMAP_DSS_GFX));
325 RR(OVL_BA1(OMAP_DSS_GFX));
326 RR(OVL_POSITION(OMAP_DSS_GFX));
327 RR(OVL_SIZE(OMAP_DSS_GFX));
328 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
329 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
330 RR(OVL_ROW_INC(OMAP_DSS_GFX));
331 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
332 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
333 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
334
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]335
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]336 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
337 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
338 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]339
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]340 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
341 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
342 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]343 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]344 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
345 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
346 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]347
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]348 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
349 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
350 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]351 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]352
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]353 RR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]354
355 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]356 RR(OVL_BA0(OMAP_DSS_VIDEO1));
357 RR(OVL_BA1(OMAP_DSS_VIDEO1));
358 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
359 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
360 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
361 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
362 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
363 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
364 RR(OVL_FIR(OMAP_DSS_VIDEO1));
365 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
366 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
367 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]368
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]369 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
370 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
371 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
372 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
373 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
374 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
375 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
376 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]377
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]378 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
379 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
380 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
381 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
382 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
383 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
384 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
385 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]386
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]387 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
388 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
389 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
390 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
391 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]392
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]393 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
394 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
395 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
396 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
397 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
398 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
399 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
400 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]401
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]402 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]403
404 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]405 RR(OVL_BA0(OMAP_DSS_VIDEO2));
406 RR(OVL_BA1(OMAP_DSS_VIDEO2));
407 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
408 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
409 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
410 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
411 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
412 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
413 RR(OVL_FIR(OMAP_DSS_VIDEO2));
414 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
415 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
416 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]417
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]418 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
419 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
420 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
421 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
422 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
423 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
424 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
425 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]426
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]427 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
428 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
429 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
430 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
431 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
432 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
433 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
434 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]435
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]436 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
437 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
438 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
439 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
440 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]441
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]442 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
443 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
444 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
445 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
446 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
447 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
448 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
449 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]450
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]451 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]452
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]453 if (dss_has_feature(FEAT_CORE_CLK_DIV))
454 RR(DIVISOR);
455
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]456 /* enable last, because LCD & DIGIT enable are here */
457 RR(CONTROL);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]458 if (dss_has_feature(FEAT_MGR_LCD2))
459 RR(CONTROL2);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200[diff] [blame]460 /* clear spurious SYNC_LOST_DIGIT interrupts */
461 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
462
463 /*
464 * enable last so IRQs won't trigger before
465 * the context is fully restored
466 */
467 RR(IRQENABLE);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]468}
469
470#undef SR
471#undef RR
472
473static inline void enable_clocks(bool enable)
474{
475 if (enable)
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]476 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]477 else
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]478 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]479}
480
481bool dispc_go_busy(enum omap_channel channel)
482{
483 int bit;
484
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]485 if (channel == OMAP_DSS_CHANNEL_LCD ||
486 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]487 bit = 5; /* GOLCD */
488 else
489 bit = 6; /* GODIGIT */
490
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]491 if (channel == OMAP_DSS_CHANNEL_LCD2)
492 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
493 else
494 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]495}
496
497void dispc_go(enum omap_channel channel)
498{
499 int bit;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]500 bool enable_bit, go_bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]501
502 enable_clocks(1);
503
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]504 if (channel == OMAP_DSS_CHANNEL_LCD ||
505 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]506 bit = 0; /* LCDENABLE */
507 else
508 bit = 1; /* DIGITALENABLE */
509
510 /* if the channel is not enabled, we don't need GO */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]511 if (channel == OMAP_DSS_CHANNEL_LCD2)
512 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
513 else
514 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
515
516 if (!enable_bit)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]517 goto end;
518
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]519 if (channel == OMAP_DSS_CHANNEL_LCD ||
520 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]521 bit = 5; /* GOLCD */
522 else
523 bit = 6; /* GODIGIT */
524
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]525 if (channel == OMAP_DSS_CHANNEL_LCD2)
526 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
527 else
528 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
529
530 if (go_bit) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]531 DSSERR("GO bit not down for channel %d\n", channel);
532 goto end;
533 }
534
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]535 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
536 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]537
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]538 if (channel == OMAP_DSS_CHANNEL_LCD2)
539 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
540 else
541 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]542end:
543 enable_clocks(0);
544}
545
546static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
547{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]548 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]549}
550
551static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
552{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]553 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]554}
555
556static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
557{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]558 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]559}
560
561static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
562 int vscaleup, int five_taps)
563{
564 /* Coefficients for horizontal up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]565 static const struct dispc_h_coef coef_hup[8] = {
566 { 0, 0, 128, 0, 0 },
567 { -1, 13, 124, -8, 0 },
568 { -2, 30, 112, -11, -1 },
569 { -5, 51, 95, -11, -2 },
570 { 0, -9, 73, 73, -9 },
571 { -2, -11, 95, 51, -5 },
572 { -1, -11, 112, 30, -2 },
573 { 0, -8, 124, 13, -1 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]574 };
575
576 /* Coefficients for vertical up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]577 static const struct dispc_v_coef coef_vup_3tap[8] = {
578 { 0, 0, 128, 0, 0 },
579 { 0, 3, 123, 2, 0 },
580 { 0, 12, 111, 5, 0 },
581 { 0, 32, 89, 7, 0 },
582 { 0, 0, 64, 64, 0 },
583 { 0, 7, 89, 32, 0 },
584 { 0, 5, 111, 12, 0 },
585 { 0, 2, 123, 3, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]586 };
587
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]588 static const struct dispc_v_coef coef_vup_5tap[8] = {
589 { 0, 0, 128, 0, 0 },
590 { -1, 13, 124, -8, 0 },
591 { -2, 30, 112, -11, -1 },
592 { -5, 51, 95, -11, -2 },
593 { 0, -9, 73, 73, -9 },
594 { -2, -11, 95, 51, -5 },
595 { -1, -11, 112, 30, -2 },
596 { 0, -8, 124, 13, -1 },
597 };
598
599 /* Coefficients for horizontal down-sampling */
600 static const struct dispc_h_coef coef_hdown[8] = {
601 { 0, 36, 56, 36, 0 },
602 { 4, 40, 55, 31, -2 },
603 { 8, 44, 54, 27, -5 },
604 { 12, 48, 53, 22, -7 },
605 { -9, 17, 52, 51, 17 },
606 { -7, 22, 53, 48, 12 },
607 { -5, 27, 54, 44, 8 },
608 { -2, 31, 55, 40, 4 },
609 };
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]610
611 /* Coefficients for vertical down-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]612 static const struct dispc_v_coef coef_vdown_3tap[8] = {
613 { 0, 36, 56, 36, 0 },
614 { 0, 40, 57, 31, 0 },
615 { 0, 45, 56, 27, 0 },
616 { 0, 50, 55, 23, 0 },
617 { 0, 18, 55, 55, 0 },
618 { 0, 23, 55, 50, 0 },
619 { 0, 27, 56, 45, 0 },
620 { 0, 31, 57, 40, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]621 };
622
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]623 static const struct dispc_v_coef coef_vdown_5tap[8] = {
624 { 0, 36, 56, 36, 0 },
625 { 4, 40, 55, 31, -2 },
626 { 8, 44, 54, 27, -5 },
627 { 12, 48, 53, 22, -7 },
628 { -9, 17, 52, 51, 17 },
629 { -7, 22, 53, 48, 12 },
630 { -5, 27, 54, 44, 8 },
631 { -2, 31, 55, 40, 4 },
632 };
633
634 const struct dispc_h_coef *h_coef;
635 const struct dispc_v_coef *v_coef;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]636 int i;
637
638 if (hscaleup)
639 h_coef = coef_hup;
640 else
641 h_coef = coef_hdown;
642
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]643 if (vscaleup)
644 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
645 else
646 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]647
648 for (i = 0; i < 8; i++) {
649 u32 h, hv;
650
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]651 h = FLD_VAL(h_coef[i].hc0, 7, 0)
652 | FLD_VAL(h_coef[i].hc1, 15, 8)
653 | FLD_VAL(h_coef[i].hc2, 23, 16)
654 | FLD_VAL(h_coef[i].hc3, 31, 24);
655 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
656 | FLD_VAL(v_coef[i].vc0, 15, 8)
657 | FLD_VAL(v_coef[i].vc1, 23, 16)
658 | FLD_VAL(v_coef[i].vc2, 31, 24);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]659
660 _dispc_write_firh_reg(plane, i, h);
661 _dispc_write_firhv_reg(plane, i, hv);
662 }
663
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200[diff] [blame]664 if (five_taps) {
665 for (i = 0; i < 8; i++) {
666 u32 v;
667 v = FLD_VAL(v_coef[i].vc00, 7, 0)
668 | FLD_VAL(v_coef[i].vc22, 15, 8);
669 _dispc_write_firv_reg(plane, i, v);
670 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]671 }
672}
673
674static void _dispc_setup_color_conv_coef(void)
675{
676 const struct color_conv_coef {
677 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
678 int full_range;
679 } ctbl_bt601_5 = {
680 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
681 };
682
683 const struct color_conv_coef *ct;
684
685#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
686
687 ct = &ctbl_bt601_5;
688
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]689 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
690 CVAL(ct->rcr, ct->ry));
691 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
692 CVAL(ct->gy, ct->rcb));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
694 CVAL(ct->gcb, ct->gcr));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
696 CVAL(ct->bcr, ct->by));
697 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
698 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]699
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]700 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
701 CVAL(ct->rcr, ct->ry));
702 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
703 CVAL(ct->gy, ct->rcb));
704 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
705 CVAL(ct->gcb, ct->gcr));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
707 CVAL(ct->bcr, ct->by));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
709 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]710
711#undef CVAL
712
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]713 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
714 ct->full_range, 11, 11);
715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
716 ct->full_range, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]717}
718
719
720static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
721{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]722 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]723}
724
725static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
726{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]727 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]728}
729
730static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
731{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]732 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]733
734 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]735}
736
737static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
738{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]739 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]740
741 if (plane == OMAP_DSS_GFX)
742 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
743 else
744 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]745}
746
747static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
748{
749 u32 val;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]750
751 BUG_ON(plane == OMAP_DSS_GFX);
752
753 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]754
755 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]756}
757
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]758static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
759{
760 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
761 return;
762
763 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
764 plane == OMAP_DSS_VIDEO1)
765 return;
766
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]767 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]768}
769
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]770static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
771{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]772 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]773 return;
774
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]775 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
776 plane == OMAP_DSS_VIDEO1)
777 return;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]778
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]779 if (plane == OMAP_DSS_GFX)
780 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
781 else if (plane == OMAP_DSS_VIDEO2)
782 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
783}
784
785static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
786{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]787 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]788}
789
790static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
791{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]792 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]793}
794
795static void _dispc_set_color_mode(enum omap_plane plane,
796 enum omap_color_mode color_mode)
797{
798 u32 m = 0;
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame^]799 if (plane != OMAP_DSS_GFX) {
800 switch (color_mode) {
801 case OMAP_DSS_COLOR_NV12:
802 m = 0x0; break;
803 case OMAP_DSS_COLOR_RGB12U:
804 m = 0x1; break;
805 case OMAP_DSS_COLOR_RGBA16:
806 m = 0x2; break;
807 case OMAP_DSS_COLOR_RGBX16:
808 m = 0x4; break;
809 case OMAP_DSS_COLOR_ARGB16:
810 m = 0x5; break;
811 case OMAP_DSS_COLOR_RGB16:
812 m = 0x6; break;
813 case OMAP_DSS_COLOR_ARGB16_1555:
814 m = 0x7; break;
815 case OMAP_DSS_COLOR_RGB24U:
816 m = 0x8; break;
817 case OMAP_DSS_COLOR_RGB24P:
818 m = 0x9; break;
819 case OMAP_DSS_COLOR_YUV2:
820 m = 0xa; break;
821 case OMAP_DSS_COLOR_UYVY:
822 m = 0xb; break;
823 case OMAP_DSS_COLOR_ARGB32:
824 m = 0xc; break;
825 case OMAP_DSS_COLOR_RGBA32:
826 m = 0xd; break;
827 case OMAP_DSS_COLOR_RGBX32:
828 m = 0xe; break;
829 case OMAP_DSS_COLOR_XRGB16_1555:
830 m = 0xf; break;
831 default:
832 BUG(); break;
833 }
834 } else {
835 switch (color_mode) {
836 case OMAP_DSS_COLOR_CLUT1:
837 m = 0x0; break;
838 case OMAP_DSS_COLOR_CLUT2:
839 m = 0x1; break;
840 case OMAP_DSS_COLOR_CLUT4:
841 m = 0x2; break;
842 case OMAP_DSS_COLOR_CLUT8:
843 m = 0x3; break;
844 case OMAP_DSS_COLOR_RGB12U:
845 m = 0x4; break;
846 case OMAP_DSS_COLOR_ARGB16:
847 m = 0x5; break;
848 case OMAP_DSS_COLOR_RGB16:
849 m = 0x6; break;
850 case OMAP_DSS_COLOR_ARGB16_1555:
851 m = 0x7; break;
852 case OMAP_DSS_COLOR_RGB24U:
853 m = 0x8; break;
854 case OMAP_DSS_COLOR_RGB24P:
855 m = 0x9; break;
856 case OMAP_DSS_COLOR_YUV2:
857 m = 0xa; break;
858 case OMAP_DSS_COLOR_UYVY:
859 m = 0xb; break;
860 case OMAP_DSS_COLOR_ARGB32:
861 m = 0xc; break;
862 case OMAP_DSS_COLOR_RGBA32:
863 m = 0xd; break;
864 case OMAP_DSS_COLOR_RGBX32:
865 m = 0xe; break;
866 case OMAP_DSS_COLOR_XRGB16_1555:
867 m = 0xf; break;
868 default:
869 BUG(); break;
870 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]871 }
872
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]874}
875
876static void _dispc_set_channel_out(enum omap_plane plane,
877 enum omap_channel channel)
878{
879 int shift;
880 u32 val;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]881 int chan = 0, chan2 = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]882
883 switch (plane) {
884 case OMAP_DSS_GFX:
885 shift = 8;
886 break;
887 case OMAP_DSS_VIDEO1:
888 case OMAP_DSS_VIDEO2:
889 shift = 16;
890 break;
891 default:
892 BUG();
893 return;
894 }
895
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]896 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]897 if (dss_has_feature(FEAT_MGR_LCD2)) {
898 switch (channel) {
899 case OMAP_DSS_CHANNEL_LCD:
900 chan = 0;
901 chan2 = 0;
902 break;
903 case OMAP_DSS_CHANNEL_DIGIT:
904 chan = 1;
905 chan2 = 0;
906 break;
907 case OMAP_DSS_CHANNEL_LCD2:
908 chan = 0;
909 chan2 = 1;
910 break;
911 default:
912 BUG();
913 }
914
915 val = FLD_MOD(val, chan, shift, shift);
916 val = FLD_MOD(val, chan2, 31, 30);
917 } else {
918 val = FLD_MOD(val, channel, shift, shift);
919 }
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]920 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]921}
922
923void dispc_set_burst_size(enum omap_plane plane,
924 enum omap_burst_size burst_size)
925{
926 int shift;
927 u32 val;
928
929 enable_clocks(1);
930
931 switch (plane) {
932 case OMAP_DSS_GFX:
933 shift = 6;
934 break;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
937 shift = 14;
938 break;
939 default:
940 BUG();
941 return;
942 }
943
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]944 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]945 val = FLD_MOD(val, burst_size, shift+1, shift);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]946 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]947
948 enable_clocks(0);
949}
950
Mythri P Kd3862612011-03-11 18:02:49 +0530[diff] [blame]951void dispc_enable_gamma_table(bool enable)
952{
953 /*
954 * This is partially implemented to support only disabling of
955 * the gamma table.
956 */
957 if (enable) {
958 DSSWARN("Gamma table enabling for TV not yet supported");
959 return;
960 }
961
962 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
963}
964
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]965static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
966{
967 u32 val;
968
969 BUG_ON(plane == OMAP_DSS_GFX);
970
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]971 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]972 val = FLD_MOD(val, enable, 9, 9);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]973 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]974}
975
976void dispc_enable_replication(enum omap_plane plane, bool enable)
977{
978 int bit;
979
980 if (plane == OMAP_DSS_GFX)
981 bit = 5;
982 else
983 bit = 10;
984
985 enable_clocks(1);
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]986 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]987 enable_clocks(0);
988}
989
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]990void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]991{
992 u32 val;
993 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
994 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
995 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]996 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]997 enable_clocks(0);
998}
999
1000void dispc_set_digit_size(u16 width, u16 height)
1001{
1002 u32 val;
1003 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1004 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1005 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]1006 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1007 enable_clocks(0);
1008}
1009
1010static void dispc_read_plane_fifo_sizes(void)
1011{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1012 u32 size;
1013 int plane;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1014 u8 start, end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1015
1016 enable_clocks(1);
1017
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1018 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1019
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1020 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1021 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
1022 start, end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1023 dispc.fifo_size[plane] = size;
1024 }
1025
1026 enable_clocks(0);
1027}
1028
1029u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1030{
1031 return dispc.fifo_size[plane];
1032}
1033
1034void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1035{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1036 u8 hi_start, hi_end, lo_start, lo_end;
1037
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1038 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1039 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1040
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1041 enable_clocks(1);
1042
1043 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1044 plane,
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1045 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1046 lo_start, lo_end),
1047 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1048 hi_start, hi_end),
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1049 low, high);
1050
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1051 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1052 FLD_VAL(high, hi_start, hi_end) |
1053 FLD_VAL(low, lo_start, lo_end));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1054
1055 enable_clocks(0);
1056}
1057
1058void dispc_enable_fifomerge(bool enable)
1059{
1060 enable_clocks(1);
1061
1062 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1063 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1064
1065 enable_clocks(0);
1066}
1067
1068static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1069{
1070 u32 val;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1071 u8 hinc_start, hinc_end, vinc_start, vinc_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1072
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]1073 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1074 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1075
1076 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1077 FLD_VAL(hinc, hinc_start, hinc_end);
1078
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1079 dispc_write_reg(DISPC_OVL_FIR(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1080}
1081
1082static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1083{
1084 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1085 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1086
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1087 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1088 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1089
1090 val = FLD_VAL(vaccu, vert_start, vert_end) |
1091 FLD_VAL(haccu, hor_start, hor_end);
1092
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1093 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1094}
1095
1096static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1097{
1098 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1099 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1100
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1101 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1102 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1103
1104 val = FLD_VAL(vaccu, vert_start, vert_end) |
1105 FLD_VAL(haccu, hor_start, hor_end);
1106
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1107 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1108}
1109
1110
1111static void _dispc_set_scaling(enum omap_plane plane,
1112 u16 orig_width, u16 orig_height,
1113 u16 out_width, u16 out_height,
1114 bool ilace, bool five_taps,
1115 bool fieldmode)
1116{
1117 int fir_hinc;
1118 int fir_vinc;
1119 int hscaleup, vscaleup;
1120 int accu0 = 0;
1121 int accu1 = 0;
1122 u32 l;
1123
1124 BUG_ON(plane == OMAP_DSS_GFX);
1125
1126 hscaleup = orig_width <= out_width;
1127 vscaleup = orig_height <= out_height;
1128
1129 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1130
1131 if (!orig_width || orig_width == out_width)
1132 fir_hinc = 0;
1133 else
1134 fir_hinc = 1024 * orig_width / out_width;
1135
1136 if (!orig_height || orig_height == out_height)
1137 fir_vinc = 0;
1138 else
1139 fir_vinc = 1024 * orig_height / out_height;
1140
1141 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1142
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1143 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1144
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1145 /* RESIZEENABLE and VERTICALTAPS */
1146 l &= ~((0x3 << 5) | (0x1 << 21));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1147 l |= fir_hinc ? (1 << 5) : 0;
1148 l |= fir_vinc ? (1 << 6) : 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1149 l |= five_taps ? (1 << 21) : 0;
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1150
1151 /* VRESIZECONF and HRESIZECONF */
1152 if (dss_has_feature(FEAT_RESIZECONF)) {
1153 l &= ~(0x3 << 7);
1154 l |= hscaleup ? 0 : (1 << 7);
1155 l |= vscaleup ? 0 : (1 << 8);
1156 }
1157
1158 /* LINEBUFFERSPLIT */
1159 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1160 l &= ~(0x1 << 22);
1161 l |= five_taps ? (1 << 22) : 0;
1162 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1163
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1164 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1165
1166 /*
1167 * field 0 = even field = bottom field
1168 * field 1 = odd field = top field
1169 */
1170 if (ilace && !fieldmode) {
1171 accu1 = 0;
1172 accu0 = (fir_vinc / 2) & 0x3ff;
1173 if (accu0 >= 1024/2) {
1174 accu1 = 1024/2;
1175 accu0 -= accu1;
1176 }
1177 }
1178
1179 _dispc_set_vid_accu0(plane, 0, accu0);
1180 _dispc_set_vid_accu1(plane, 0, accu1);
1181}
1182
1183static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1184 bool mirroring, enum omap_color_mode color_mode)
1185{
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1186 bool row_repeat = false;
1187 int vidrot = 0;
1188
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1189 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1190 color_mode == OMAP_DSS_COLOR_UYVY) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1191
1192 if (mirroring) {
1193 switch (rotation) {
1194 case OMAP_DSS_ROT_0:
1195 vidrot = 2;
1196 break;
1197 case OMAP_DSS_ROT_90:
1198 vidrot = 1;
1199 break;
1200 case OMAP_DSS_ROT_180:
1201 vidrot = 0;
1202 break;
1203 case OMAP_DSS_ROT_270:
1204 vidrot = 3;
1205 break;
1206 }
1207 } else {
1208 switch (rotation) {
1209 case OMAP_DSS_ROT_0:
1210 vidrot = 0;
1211 break;
1212 case OMAP_DSS_ROT_90:
1213 vidrot = 1;
1214 break;
1215 case OMAP_DSS_ROT_180:
1216 vidrot = 2;
1217 break;
1218 case OMAP_DSS_ROT_270:
1219 vidrot = 3;
1220 break;
1221 }
1222 }
1223
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1224 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1225 row_repeat = true;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1226 else
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1227 row_repeat = false;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1228 }
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1229
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1230 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
Archit Taneja87a74842011-03-02 11:19:50 +0530[diff] [blame]1231 if (dss_has_feature(FEAT_ROWREPEATENABLE))
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1232 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1233 row_repeat ? 1 : 0, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1234}
1235
1236static int color_mode_to_bpp(enum omap_color_mode color_mode)
1237{
1238 switch (color_mode) {
1239 case OMAP_DSS_COLOR_CLUT1:
1240 return 1;
1241 case OMAP_DSS_COLOR_CLUT2:
1242 return 2;
1243 case OMAP_DSS_COLOR_CLUT4:
1244 return 4;
1245 case OMAP_DSS_COLOR_CLUT8:
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame^]1246 case OMAP_DSS_COLOR_NV12:
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1247 return 8;
1248 case OMAP_DSS_COLOR_RGB12U:
1249 case OMAP_DSS_COLOR_RGB16:
1250 case OMAP_DSS_COLOR_ARGB16:
1251 case OMAP_DSS_COLOR_YUV2:
1252 case OMAP_DSS_COLOR_UYVY:
Amber Jainf20e4222011-05-19 19:47:50 +0530[diff] [blame^]1253 case OMAP_DSS_COLOR_RGBA16:
1254 case OMAP_DSS_COLOR_RGBX16:
1255 case OMAP_DSS_COLOR_ARGB16_1555:
1256 case OMAP_DSS_COLOR_XRGB16_1555:
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1257 return 16;
1258 case OMAP_DSS_COLOR_RGB24P:
1259 return 24;
1260 case OMAP_DSS_COLOR_RGB24U:
1261 case OMAP_DSS_COLOR_ARGB32:
1262 case OMAP_DSS_COLOR_RGBA32:
1263 case OMAP_DSS_COLOR_RGBX32:
1264 return 32;
1265 default:
1266 BUG();
1267 }
1268}
1269
1270static s32 pixinc(int pixels, u8 ps)
1271{
1272 if (pixels == 1)
1273 return 1;
1274 else if (pixels > 1)
1275 return 1 + (pixels - 1) * ps;
1276 else if (pixels < 0)
1277 return 1 - (-pixels + 1) * ps;
1278 else
1279 BUG();
1280}
1281
1282static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1283 u16 screen_width,
1284 u16 width, u16 height,
1285 enum omap_color_mode color_mode, bool fieldmode,
1286 unsigned int field_offset,
1287 unsigned *offset0, unsigned *offset1,
1288 s32 *row_inc, s32 *pix_inc)
1289{
1290 u8 ps;
1291
1292 /* FIXME CLUT formats */
1293 switch (color_mode) {
1294 case OMAP_DSS_COLOR_CLUT1:
1295 case OMAP_DSS_COLOR_CLUT2:
1296 case OMAP_DSS_COLOR_CLUT4:
1297 case OMAP_DSS_COLOR_CLUT8:
1298 BUG();
1299 return;
1300 case OMAP_DSS_COLOR_YUV2:
1301 case OMAP_DSS_COLOR_UYVY:
1302 ps = 4;
1303 break;
1304 default:
1305 ps = color_mode_to_bpp(color_mode) / 8;
1306 break;
1307 }
1308
1309 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1310 width, height);
1311
1312 /*
1313 * field 0 = even field = bottom field
1314 * field 1 = odd field = top field
1315 */
1316 switch (rotation + mirror * 4) {
1317 case OMAP_DSS_ROT_0:
1318 case OMAP_DSS_ROT_180:
1319 /*
1320 * If the pixel format is YUV or UYVY divide the width
1321 * of the image by 2 for 0 and 180 degree rotation.
1322 */
1323 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1324 color_mode == OMAP_DSS_COLOR_UYVY)
1325 width = width >> 1;
1326 case OMAP_DSS_ROT_90:
1327 case OMAP_DSS_ROT_270:
1328 *offset1 = 0;
1329 if (field_offset)
1330 *offset0 = field_offset * screen_width * ps;
1331 else
1332 *offset0 = 0;
1333
1334 *row_inc = pixinc(1 + (screen_width - width) +
1335 (fieldmode ? screen_width : 0),
1336 ps);
1337 *pix_inc = pixinc(1, ps);
1338 break;
1339
1340 case OMAP_DSS_ROT_0 + 4:
1341 case OMAP_DSS_ROT_180 + 4:
1342 /* If the pixel format is YUV or UYVY divide the width
1343 * of the image by 2 for 0 degree and 180 degree
1344 */
1345 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1346 color_mode == OMAP_DSS_COLOR_UYVY)
1347 width = width >> 1;
1348 case OMAP_DSS_ROT_90 + 4:
1349 case OMAP_DSS_ROT_270 + 4:
1350 *offset1 = 0;
1351 if (field_offset)
1352 *offset0 = field_offset * screen_width * ps;
1353 else
1354 *offset0 = 0;
1355 *row_inc = pixinc(1 - (screen_width + width) -
1356 (fieldmode ? screen_width : 0),
1357 ps);
1358 *pix_inc = pixinc(1, ps);
1359 break;
1360
1361 default:
1362 BUG();
1363 }
1364}
1365
1366static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1367 u16 screen_width,
1368 u16 width, u16 height,
1369 enum omap_color_mode color_mode, bool fieldmode,
1370 unsigned int field_offset,
1371 unsigned *offset0, unsigned *offset1,
1372 s32 *row_inc, s32 *pix_inc)
1373{
1374 u8 ps;
1375 u16 fbw, fbh;
1376
1377 /* FIXME CLUT formats */
1378 switch (color_mode) {
1379 case OMAP_DSS_COLOR_CLUT1:
1380 case OMAP_DSS_COLOR_CLUT2:
1381 case OMAP_DSS_COLOR_CLUT4:
1382 case OMAP_DSS_COLOR_CLUT8:
1383 BUG();
1384 return;
1385 default:
1386 ps = color_mode_to_bpp(color_mode) / 8;
1387 break;
1388 }
1389
1390 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1391 width, height);
1392
1393 /* width & height are overlay sizes, convert to fb sizes */
1394
1395 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1396 fbw = width;
1397 fbh = height;
1398 } else {
1399 fbw = height;
1400 fbh = width;
1401 }
1402
1403 /*
1404 * field 0 = even field = bottom field
1405 * field 1 = odd field = top field
1406 */
1407 switch (rotation + mirror * 4) {
1408 case OMAP_DSS_ROT_0:
1409 *offset1 = 0;
1410 if (field_offset)
1411 *offset0 = *offset1 + field_offset * screen_width * ps;
1412 else
1413 *offset0 = *offset1;
1414 *row_inc = pixinc(1 + (screen_width - fbw) +
1415 (fieldmode ? screen_width : 0),
1416 ps);
1417 *pix_inc = pixinc(1, ps);
1418 break;
1419 case OMAP_DSS_ROT_90:
1420 *offset1 = screen_width * (fbh - 1) * ps;
1421 if (field_offset)
1422 *offset0 = *offset1 + field_offset * ps;
1423 else
1424 *offset0 = *offset1;
1425 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1426 (fieldmode ? 1 : 0), ps);
1427 *pix_inc = pixinc(-screen_width, ps);
1428 break;
1429 case OMAP_DSS_ROT_180:
1430 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1431 if (field_offset)
1432 *offset0 = *offset1 - field_offset * screen_width * ps;
1433 else
1434 *offset0 = *offset1;
1435 *row_inc = pixinc(-1 -
1436 (screen_width - fbw) -
1437 (fieldmode ? screen_width : 0),
1438 ps);
1439 *pix_inc = pixinc(-1, ps);
1440 break;
1441 case OMAP_DSS_ROT_270:
1442 *offset1 = (fbw - 1) * ps;
1443 if (field_offset)
1444 *offset0 = *offset1 - field_offset * ps;
1445 else
1446 *offset0 = *offset1;
1447 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1448 (fieldmode ? 1 : 0), ps);
1449 *pix_inc = pixinc(screen_width, ps);
1450 break;
1451
1452 /* mirroring */
1453 case OMAP_DSS_ROT_0 + 4:
1454 *offset1 = (fbw - 1) * ps;
1455 if (field_offset)
1456 *offset0 = *offset1 + field_offset * screen_width * ps;
1457 else
1458 *offset0 = *offset1;
1459 *row_inc = pixinc(screen_width * 2 - 1 +
1460 (fieldmode ? screen_width : 0),
1461 ps);
1462 *pix_inc = pixinc(-1, ps);
1463 break;
1464
1465 case OMAP_DSS_ROT_90 + 4:
1466 *offset1 = 0;
1467 if (field_offset)
1468 *offset0 = *offset1 + field_offset * ps;
1469 else
1470 *offset0 = *offset1;
1471 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1472 (fieldmode ? 1 : 0),
1473 ps);
1474 *pix_inc = pixinc(screen_width, ps);
1475 break;
1476
1477 case OMAP_DSS_ROT_180 + 4:
1478 *offset1 = screen_width * (fbh - 1) * ps;
1479 if (field_offset)
1480 *offset0 = *offset1 - field_offset * screen_width * ps;
1481 else
1482 *offset0 = *offset1;
1483 *row_inc = pixinc(1 - screen_width * 2 -
1484 (fieldmode ? screen_width : 0),
1485 ps);
1486 *pix_inc = pixinc(1, ps);
1487 break;
1488
1489 case OMAP_DSS_ROT_270 + 4:
1490 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1491 if (field_offset)
1492 *offset0 = *offset1 - field_offset * ps;
1493 else
1494 *offset0 = *offset1;
1495 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1496 (fieldmode ? 1 : 0),
1497 ps);
1498 *pix_inc = pixinc(-screen_width, ps);
1499 break;
1500
1501 default:
1502 BUG();
1503 }
1504}
1505
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1506static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1507 u16 height, u16 out_width, u16 out_height,
1508 enum omap_color_mode color_mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1509{
1510 u32 fclk = 0;
1511 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1512 u64 tmp, pclk = dispc_pclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1513
1514 if (height > out_height) {
1515 /* FIXME get real display PPL */
1516 unsigned int ppl = 800;
1517
1518 tmp = pclk * height * out_width;
1519 do_div(tmp, 2 * out_height * ppl);
1520 fclk = tmp;
1521
Ville Syrjälä2d9c5592010-01-08 11:56:41 +0200[diff] [blame]1522 if (height > 2 * out_height) {
1523 if (ppl == out_width)
1524 return 0;
1525
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1526 tmp = pclk * (height - 2 * out_height) * out_width;
1527 do_div(tmp, 2 * out_height * (ppl - out_width));
1528 fclk = max(fclk, (u32) tmp);
1529 }
1530 }
1531
1532 if (width > out_width) {
1533 tmp = pclk * width;
1534 do_div(tmp, out_width);
1535 fclk = max(fclk, (u32) tmp);
1536
1537 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1538 fclk <<= 1;
1539 }
1540
1541 return fclk;
1542}
1543
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1544static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1545 u16 height, u16 out_width, u16 out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1546{
1547 unsigned int hf, vf;
1548
1549 /*
1550 * FIXME how to determine the 'A' factor
1551 * for the no downscaling case ?
1552 */
1553
1554 if (width > 3 * out_width)
1555 hf = 4;
1556 else if (width > 2 * out_width)
1557 hf = 3;
1558 else if (width > out_width)
1559 hf = 2;
1560 else
1561 hf = 1;
1562
1563 if (height > out_height)
1564 vf = 2;
1565 else
1566 vf = 1;
1567
1568 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]1569 return dispc_pclk_rate(channel) * vf * hf;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1570}
1571
1572void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1573{
1574 enable_clocks(1);
1575 _dispc_set_channel_out(plane, channel_out);
1576 enable_clocks(0);
1577}
1578
1579static int _dispc_setup_plane(enum omap_plane plane,
1580 u32 paddr, u16 screen_width,
1581 u16 pos_x, u16 pos_y,
1582 u16 width, u16 height,
1583 u16 out_width, u16 out_height,
1584 enum omap_color_mode color_mode,
1585 bool ilace,
1586 enum omap_dss_rotation_type rotation_type,
1587 u8 rotation, int mirror,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1588 u8 global_alpha, u8 pre_mult_alpha,
1589 enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1590{
1591 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1592 bool five_taps = 0;
1593 bool fieldmode = 0;
1594 int cconv = 0;
1595 unsigned offset0, offset1;
1596 s32 row_inc;
1597 s32 pix_inc;
1598 u16 frame_height = height;
1599 unsigned int field_offset = 0;
1600
1601 if (paddr == 0)
1602 return -EINVAL;
1603
1604 if (ilace && height == out_height)
1605 fieldmode = 1;
1606
1607 if (ilace) {
1608 if (fieldmode)
1609 height /= 2;
1610 pos_y /= 2;
1611 out_height /= 2;
1612
1613 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1614 "out_height %d\n",
1615 height, pos_y, out_height);
1616 }
1617
Archit Taneja8dad2ab2010-11-25 17:58:10 +0530[diff] [blame]1618 if (!dss_feat_color_mode_supported(plane, color_mode))
1619 return -EINVAL;
1620
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1621 if (plane == OMAP_DSS_GFX) {
1622 if (width != out_width || height != out_height)
1623 return -EINVAL;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1624 } else {
1625 /* video plane */
1626
1627 unsigned long fclk = 0;
1628
1629 if (out_width < width / maxdownscale ||
1630 out_width > width * 8)
1631 return -EINVAL;
1632
1633 if (out_height < height / maxdownscale ||
1634 out_height > height * 8)
1635 return -EINVAL;
1636
Archit Taneja8dad2ab2010-11-25 17:58:10 +0530[diff] [blame]1637 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1638 color_mode == OMAP_DSS_COLOR_UYVY)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1639 cconv = 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1640
1641 /* Must use 5-tap filter? */
1642 five_taps = height > out_height * 2;
1643
1644 if (!five_taps) {
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1645 fclk = calc_fclk(channel, width, height, out_width,
1646 out_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1647
1648 /* Try 5-tap filter if 3-tap fclk is too high */
1649 if (cpu_is_omap34xx() && height > out_height &&
1650 fclk > dispc_fclk_rate())
1651 five_taps = true;
1652 }
1653
1654 if (width > (2048 >> five_taps)) {
1655 DSSERR("failed to set up scaling, fclk too low\n");
1656 return -EINVAL;
1657 }
1658
1659 if (five_taps)
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]1660 fclk = calc_fclk_five_taps(channel, width, height,
1661 out_width, out_height, color_mode);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1662
1663 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1664 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1665
Ville Syrjälä2d9c5592010-01-08 11:56:41 +0200[diff] [blame]1666 if (!fclk || fclk > dispc_fclk_rate()) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1667 DSSERR("failed to set up scaling, "
1668 "required fclk rate = %lu Hz, "
1669 "current fclk rate = %lu Hz\n",
1670 fclk, dispc_fclk_rate());
1671 return -EINVAL;
1672 }
1673 }
1674
1675 if (ilace && !fieldmode) {
1676 /*
1677 * when downscaling the bottom field may have to start several
1678 * source lines below the top field. Unfortunately ACCUI
1679 * registers will only hold the fractional part of the offset
1680 * so the integer part must be added to the base address of the
1681 * bottom field.
1682 */
1683 if (!height || height == out_height)
1684 field_offset = 0;
1685 else
1686 field_offset = height / out_height / 2;
1687 }
1688
1689 /* Fields are independent but interleaved in memory. */
1690 if (fieldmode)
1691 field_offset = 1;
1692
1693 if (rotation_type == OMAP_DSS_ROT_DMA)
1694 calc_dma_rotation_offset(rotation, mirror,
1695 screen_width, width, frame_height, color_mode,
1696 fieldmode, field_offset,
1697 &offset0, &offset1, &row_inc, &pix_inc);
1698 else
1699 calc_vrfb_rotation_offset(rotation, mirror,
1700 screen_width, width, frame_height, color_mode,
1701 fieldmode, field_offset,
1702 &offset0, &offset1, &row_inc, &pix_inc);
1703
1704 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1705 offset0, offset1, row_inc, pix_inc);
1706
1707 _dispc_set_color_mode(plane, color_mode);
1708
1709 _dispc_set_plane_ba0(plane, paddr + offset0);
1710 _dispc_set_plane_ba1(plane, paddr + offset1);
1711
1712 _dispc_set_row_inc(plane, row_inc);
1713 _dispc_set_pix_inc(plane, pix_inc);
1714
1715 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1716 out_width, out_height);
1717
1718 _dispc_set_plane_pos(plane, pos_x, pos_y);
1719
1720 _dispc_set_pic_size(plane, width, height);
1721
1722 if (plane != OMAP_DSS_GFX) {
1723 _dispc_set_scaling(plane, width, height,
1724 out_width, out_height,
1725 ilace, five_taps, fieldmode);
1726 _dispc_set_vid_size(plane, out_width, out_height);
1727 _dispc_set_vid_color_conv(plane, cconv);
1728 }
1729
1730 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1731
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]1732 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1733 _dispc_setup_global_alpha(plane, global_alpha);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1734
1735 return 0;
1736}
1737
1738static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1739{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]1740 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1741}
1742
1743static void dispc_disable_isr(void *data, u32 mask)
1744{
1745 struct completion *compl = data;
1746 complete(compl);
1747}
1748
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1749static void _enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1750{
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1751 if (channel == OMAP_DSS_CHANNEL_LCD2)
1752 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1753 else
1754 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1755}
1756
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1757static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1758{
1759 struct completion frame_done_completion;
1760 bool is_on;
1761 int r;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1762 u32 irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1763
1764 enable_clocks(1);
1765
1766 /* When we disable LCD output, we need to wait until frame is done.
1767 * Otherwise the DSS is still working, and turning off the clocks
1768 * prevents DSS from going to OFF mode */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1769 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1770 REG_GET(DISPC_CONTROL2, 0, 0) :
1771 REG_GET(DISPC_CONTROL, 0, 0);
1772
1773 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1774 DISPC_IRQ_FRAMEDONE;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1775
1776 if (!enable && is_on) {
1777 init_completion(&frame_done_completion);
1778
1779 r = omap_dispc_register_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1780 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1781
1782 if (r)
1783 DSSERR("failed to register FRAMEDONE isr\n");
1784 }
1785
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1786 _enable_lcd_out(channel, enable);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1787
1788 if (!enable && is_on) {
1789 if (!wait_for_completion_timeout(&frame_done_completion,
1790 msecs_to_jiffies(100)))
1791 DSSERR("timeout waiting for FRAME DONE\n");
1792
1793 r = omap_dispc_unregister_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1794 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1795
1796 if (r)
1797 DSSERR("failed to unregister FRAMEDONE isr\n");
1798 }
1799
1800 enable_clocks(0);
1801}
1802
1803static void _enable_digit_out(bool enable)
1804{
1805 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1806}
1807
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1808static void dispc_enable_digit_out(bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1809{
1810 struct completion frame_done_completion;
1811 int r;
1812
1813 enable_clocks(1);
1814
1815 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1816 enable_clocks(0);
1817 return;
1818 }
1819
1820 if (enable) {
1821 unsigned long flags;
1822 /* When we enable digit output, we'll get an extra digit
1823 * sync lost interrupt, that we need to ignore */
1824 spin_lock_irqsave(&dispc.irq_lock, flags);
1825 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1826 _omap_dispc_set_irqs();
1827 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1828 }
1829
1830 /* When we disable digit output, we need to wait until fields are done.
1831 * Otherwise the DSS is still working, and turning off the clocks
1832 * prevents DSS from going to OFF mode. And when enabling, we need to
1833 * wait for the extra sync losts */
1834 init_completion(&frame_done_completion);
1835
1836 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1837 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1838 if (r)
1839 DSSERR("failed to register EVSYNC isr\n");
1840
1841 _enable_digit_out(enable);
1842
1843 /* XXX I understand from TRM that we should only wait for the
1844 * current field to complete. But it seems we have to wait
1845 * for both fields */
1846 if (!wait_for_completion_timeout(&frame_done_completion,
1847 msecs_to_jiffies(100)))
1848 DSSERR("timeout waiting for EVSYNC\n");
1849
1850 if (!wait_for_completion_timeout(&frame_done_completion,
1851 msecs_to_jiffies(100)))
1852 DSSERR("timeout waiting for EVSYNC\n");
1853
1854 r = omap_dispc_unregister_isr(dispc_disable_isr,
1855 &frame_done_completion,
1856 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1857 if (r)
1858 DSSERR("failed to unregister EVSYNC isr\n");
1859
1860 if (enable) {
1861 unsigned long flags;
1862 spin_lock_irqsave(&dispc.irq_lock, flags);
1863 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1864 if (dss_has_feature(FEAT_MGR_LCD2))
1865 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1866 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1867 _omap_dispc_set_irqs();
1868 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1869 }
1870
1871 enable_clocks(0);
1872}
1873
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1874bool dispc_is_channel_enabled(enum omap_channel channel)
1875{
1876 if (channel == OMAP_DSS_CHANNEL_LCD)
1877 return !!REG_GET(DISPC_CONTROL, 0, 0);
1878 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1879 return !!REG_GET(DISPC_CONTROL, 1, 1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1880 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1881 return !!REG_GET(DISPC_CONTROL2, 0, 0);
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1882 else
1883 BUG();
1884}
1885
1886void dispc_enable_channel(enum omap_channel channel, bool enable)
1887{
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1888 if (channel == OMAP_DSS_CHANNEL_LCD ||
1889 channel == OMAP_DSS_CHANNEL_LCD2)
1890 dispc_enable_lcd_out(channel, enable);
Tomi Valkeinena2faee82010-01-08 17:14:53 +0200[diff] [blame]1891 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1892 dispc_enable_digit_out(enable);
1893 else
1894 BUG();
1895}
1896
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1897void dispc_lcd_enable_signal_polarity(bool act_high)
1898{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1899 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1900 return;
1901
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1902 enable_clocks(1);
1903 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1904 enable_clocks(0);
1905}
1906
1907void dispc_lcd_enable_signal(bool enable)
1908{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1909 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1910 return;
1911
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1912 enable_clocks(1);
1913 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1914 enable_clocks(0);
1915}
1916
1917void dispc_pck_free_enable(bool enable)
1918{
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]1919 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1920 return;
1921
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1922 enable_clocks(1);
1923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1924 enable_clocks(0);
1925}
1926
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]1927void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1928{
1929 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1930 if (channel == OMAP_DSS_CHANNEL_LCD2)
1931 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1932 else
1933 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1934 enable_clocks(0);
1935}
1936
1937
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]1938void dispc_set_lcd_display_type(enum omap_channel channel,
1939 enum omap_lcd_display_type type)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1940{
1941 int mode;
1942
1943 switch (type) {
1944 case OMAP_DSS_LCD_DISPLAY_STN:
1945 mode = 0;
1946 break;
1947
1948 case OMAP_DSS_LCD_DISPLAY_TFT:
1949 mode = 1;
1950 break;
1951
1952 default:
1953 BUG();
1954 return;
1955 }
1956
1957 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1958 if (channel == OMAP_DSS_CHANNEL_LCD2)
1959 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1960 else
1961 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1962 enable_clocks(0);
1963}
1964
1965void dispc_set_loadmode(enum omap_dss_load_mode mode)
1966{
1967 enable_clocks(1);
1968 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1969 enable_clocks(0);
1970}
1971
1972
1973void dispc_set_default_color(enum omap_channel channel, u32 color)
1974{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1975 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]1976 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1977 enable_clocks(0);
1978}
1979
1980u32 dispc_get_default_color(enum omap_channel channel)
1981{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1982 u32 l;
1983
1984 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]1985 channel != OMAP_DSS_CHANNEL_LCD &&
1986 channel != OMAP_DSS_CHANNEL_LCD2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1987
1988 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]1989 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1990 enable_clocks(0);
1991
1992 return l;
1993}
1994
1995void dispc_set_trans_key(enum omap_channel ch,
1996 enum omap_dss_trans_key_type type,
1997 u32 trans_key)
1998{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]1999 enable_clocks(1);
2000 if (ch == OMAP_DSS_CHANNEL_LCD)
2001 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2002 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2003 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2004 else /* OMAP_DSS_CHANNEL_LCD2 */
2005 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2006
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]2007 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2008 enable_clocks(0);
2009}
2010
2011void dispc_get_trans_key(enum omap_channel ch,
2012 enum omap_dss_trans_key_type *type,
2013 u32 *trans_key)
2014{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2015 enable_clocks(1);
2016 if (type) {
2017 if (ch == OMAP_DSS_CHANNEL_LCD)
2018 *type = REG_GET(DISPC_CONFIG, 11, 11);
2019 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2020 *type = REG_GET(DISPC_CONFIG, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2021 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2022 *type = REG_GET(DISPC_CONFIG2, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2023 else
2024 BUG();
2025 }
2026
2027 if (trans_key)
Sumit Semwal8613b002010-12-02 11:27:09 +0000[diff] [blame]2028 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2029 enable_clocks(0);
2030}
2031
2032void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2033{
2034 enable_clocks(1);
2035 if (ch == OMAP_DSS_CHANNEL_LCD)
2036 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2037 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2038 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2039 else /* OMAP_DSS_CHANNEL_LCD2 */
2040 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2041 enable_clocks(0);
2042}
2043void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2044{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]2045 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2046 return;
2047
2048 enable_clocks(1);
2049 if (ch == OMAP_DSS_CHANNEL_LCD)
2050 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2051 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2052 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2053 else /* OMAP_DSS_CHANNEL_LCD2 */
2054 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2055 enable_clocks(0);
2056}
2057bool dispc_alpha_blending_enabled(enum omap_channel ch)
2058{
2059 bool enabled;
2060
Archit Tanejaa0acb552010-09-15 19:20:00 +0530[diff] [blame]2061 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2062 return false;
2063
2064 enable_clocks(1);
2065 if (ch == OMAP_DSS_CHANNEL_LCD)
2066 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2067 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Archit Taneja712247a2010-11-08 12:56:21 +0100[diff] [blame]2068 enabled = REG_GET(DISPC_CONFIG, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2069 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2070 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2071 else
2072 BUG();
2073 enable_clocks(0);
2074
2075 return enabled;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2076}
2077
2078
2079bool dispc_trans_key_enabled(enum omap_channel ch)
2080{
2081 bool enabled;
2082
2083 enable_clocks(1);
2084 if (ch == OMAP_DSS_CHANNEL_LCD)
2085 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2086 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2087 enabled = REG_GET(DISPC_CONFIG, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2088 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2089 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2090 else
2091 BUG();
2092 enable_clocks(0);
2093
2094 return enabled;
2095}
2096
2097
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2098void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2099{
2100 int code;
2101
2102 switch (data_lines) {
2103 case 12:
2104 code = 0;
2105 break;
2106 case 16:
2107 code = 1;
2108 break;
2109 case 18:
2110 code = 2;
2111 break;
2112 case 24:
2113 code = 3;
2114 break;
2115 default:
2116 BUG();
2117 return;
2118 }
2119
2120 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2121 if (channel == OMAP_DSS_CHANNEL_LCD2)
2122 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2123 else
2124 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2125 enable_clocks(0);
2126}
2127
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2128void dispc_set_parallel_interface_mode(enum omap_channel channel,
2129 enum omap_parallel_interface_mode mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2130{
2131 u32 l;
2132 int stallmode;
2133 int gpout0 = 1;
2134 int gpout1;
2135
2136 switch (mode) {
2137 case OMAP_DSS_PARALLELMODE_BYPASS:
2138 stallmode = 0;
2139 gpout1 = 1;
2140 break;
2141
2142 case OMAP_DSS_PARALLELMODE_RFBI:
2143 stallmode = 1;
2144 gpout1 = 0;
2145 break;
2146
2147 case OMAP_DSS_PARALLELMODE_DSI:
2148 stallmode = 1;
2149 gpout1 = 1;
2150 break;
2151
2152 default:
2153 BUG();
2154 return;
2155 }
2156
2157 enable_clocks(1);
2158
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2159 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2160 l = dispc_read_reg(DISPC_CONTROL2);
2161 l = FLD_MOD(l, stallmode, 11, 11);
2162 dispc_write_reg(DISPC_CONTROL2, l);
2163 } else {
2164 l = dispc_read_reg(DISPC_CONTROL);
2165 l = FLD_MOD(l, stallmode, 11, 11);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2166 l = FLD_MOD(l, gpout0, 15, 15);
2167 l = FLD_MOD(l, gpout1, 16, 16);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2168 dispc_write_reg(DISPC_CONTROL, l);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2169 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2170
2171 enable_clocks(0);
2172}
2173
2174static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2175 int vsw, int vfp, int vbp)
2176{
2177 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2178 if (hsw < 1 || hsw > 64 ||
2179 hfp < 1 || hfp > 256 ||
2180 hbp < 1 || hbp > 256 ||
2181 vsw < 1 || vsw > 64 ||
2182 vfp < 0 || vfp > 255 ||
2183 vbp < 0 || vbp > 255)
2184 return false;
2185 } else {
2186 if (hsw < 1 || hsw > 256 ||
2187 hfp < 1 || hfp > 4096 ||
2188 hbp < 1 || hbp > 4096 ||
2189 vsw < 1 || vsw > 256 ||
2190 vfp < 0 || vfp > 4095 ||
2191 vbp < 0 || vbp > 4095)
2192 return false;
2193 }
2194
2195 return true;
2196}
2197
2198bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2199{
2200 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2201 timings->hbp, timings->vsw,
2202 timings->vfp, timings->vbp);
2203}
2204
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2205static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2206 int hfp, int hbp, int vsw, int vfp, int vbp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2207{
2208 u32 timing_h, timing_v;
2209
2210 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2211 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2212 FLD_VAL(hbp-1, 27, 20);
2213
2214 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2215 FLD_VAL(vbp, 27, 20);
2216 } else {
2217 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2218 FLD_VAL(hbp-1, 31, 20);
2219
2220 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2221 FLD_VAL(vbp, 31, 20);
2222 }
2223
2224 enable_clocks(1);
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2225 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2226 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2227 enable_clocks(0);
2228}
2229
2230/* change name to mode? */
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2231void dispc_set_lcd_timings(enum omap_channel channel,
2232 struct omap_video_timings *timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2233{
2234 unsigned xtot, ytot;
2235 unsigned long ht, vt;
2236
2237 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2238 timings->hbp, timings->vsw,
2239 timings->vfp, timings->vbp))
2240 BUG();
2241
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2242 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2243 timings->hbp, timings->vsw, timings->vfp,
2244 timings->vbp);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2245
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000[diff] [blame]2246 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2247
2248 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2249 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2250
2251 ht = (timings->pixel_clock * 1000) / xtot;
2252 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2253
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2254 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2255 timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2256 DSSDBG("pck %u\n", timings->pixel_clock);
2257 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2258 timings->hsw, timings->hfp, timings->hbp,
2259 timings->vsw, timings->vfp, timings->vbp);
2260
2261 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2262}
2263
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2264static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2265 u16 pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2266{
2267 BUG_ON(lck_div < 1);
2268 BUG_ON(pck_div < 2);
2269
2270 enable_clocks(1);
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2271 dispc_write_reg(DISPC_DIVISORo(channel),
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2272 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2273 enable_clocks(0);
2274}
2275
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2276static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2277 int *pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2278{
2279 u32 l;
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2280 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2281 *lck_div = FLD_GET(l, 23, 16);
2282 *pck_div = FLD_GET(l, 7, 0);
2283}
2284
2285unsigned long dispc_fclk_rate(void)
2286{
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2287 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2288 unsigned long r = 0;
2289
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2290 switch (dss_get_dispc_clk_source()) {
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2291 case OMAP_DSS_CLK_SRC_FCK:
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2292 r = dss_clk_get_rate(DSS_CLK_FCK);
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2293 break;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2294 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2295 dsidev = dsi_get_dsidev_from_id(0);
2296 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2297 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +0530[diff] [blame]2298 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2299 dsidev = dsi_get_dsidev_from_id(1);
2300 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2301 break;
Taneja, Archit66534e82011-03-08 05:50:34 -0600[diff] [blame]2302 default:
2303 BUG();
2304 }
2305
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2306 return r;
2307}
2308
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2309unsigned long dispc_lclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2310{
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2311 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2312 int lcd;
2313 unsigned long r;
2314 u32 l;
2315
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2316 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2317
2318 lcd = FLD_GET(l, 23, 16);
2319
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2320 switch (dss_get_lcd_clk_source(channel)) {
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2321 case OMAP_DSS_CLK_SRC_FCK:
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2322 r = dss_clk_get_rate(DSS_CLK_FCK);
2323 break;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2324 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530[diff] [blame]2325 dsidev = dsi_get_dsidev_from_id(0);
2326 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2327 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +0530[diff] [blame]2328 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2329 dsidev = dsi_get_dsidev_from_id(1);
2330 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2331 break;
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2332 default:
2333 BUG();
2334 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2335
2336 return r / lcd;
2337}
2338
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2339unsigned long dispc_pclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2340{
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2341 int pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2342 unsigned long r;
2343 u32 l;
2344
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2345 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2346
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2347 pcd = FLD_GET(l, 7, 0);
2348
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2349 r = dispc_lclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2350
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2351 return r / pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2352}
2353
2354void dispc_dump_clocks(struct seq_file *s)
2355{
2356 int lcd, pcd;
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]2357 u32 l;
Archit Taneja89a35e52011-04-12 13:52:23 +0530[diff] [blame]2358 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2359 enum omap_dss_clk_source lcd_clk_src;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2360
2361 enable_clocks(1);
2362
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2363 seq_printf(s, "- DISPC -\n");
2364
Archit Taneja067a57e2011-03-02 11:57:25 +0530[diff] [blame]2365 seq_printf(s, "dispc fclk source = %s (%s)\n",
2366 dss_get_generic_clk_source_name(dispc_clk_src),
2367 dss_feat_get_clk_source_name(dispc_clk_src));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2368
2369 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2370
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]2371 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2372 seq_printf(s, "- DISPC-CORE-CLK -\n");
2373 l = dispc_read_reg(DISPC_DIVISOR);
2374 lcd = FLD_GET(l, 23, 16);
2375
2376 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2377 (dispc_fclk_rate()/lcd), lcd);
2378 }
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2379 seq_printf(s, "- LCD1 -\n");
2380
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2381 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2382
2383 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2384 dss_get_generic_clk_source_name(lcd_clk_src),
2385 dss_feat_get_clk_source_name(lcd_clk_src));
2386
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2387 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2388
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2389 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2390 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2391 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2392 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2393 if (dss_has_feature(FEAT_MGR_LCD2)) {
2394 seq_printf(s, "- LCD2 -\n");
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2395
Taneja, Architea751592011-03-08 05:50:35 -0600[diff] [blame]2396 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2397
2398 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2399 dss_get_generic_clk_source_name(lcd_clk_src),
2400 dss_feat_get_clk_source_name(lcd_clk_src));
2401
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2402 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2403
2404 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2405 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2406 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2407 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2408 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2409 enable_clocks(0);
2410}
2411
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2412#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2413void dispc_dump_irqs(struct seq_file *s)
2414{
2415 unsigned long flags;
2416 struct dispc_irq_stats stats;
2417
2418 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2419
2420 stats = dispc.irq_stats;
2421 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2422 dispc.irq_stats.last_reset = jiffies;
2423
2424 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2425
2426 seq_printf(s, "period %u ms\n",
2427 jiffies_to_msecs(jiffies - stats.last_reset));
2428
2429 seq_printf(s, "irqs %d\n", stats.irq_count);
2430#define PIS(x) \
2431 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2432
2433 PIS(FRAMEDONE);
2434 PIS(VSYNC);
2435 PIS(EVSYNC_EVEN);
2436 PIS(EVSYNC_ODD);
2437 PIS(ACBIAS_COUNT_STAT);
2438 PIS(PROG_LINE_NUM);
2439 PIS(GFX_FIFO_UNDERFLOW);
2440 PIS(GFX_END_WIN);
2441 PIS(PAL_GAMMA_MASK);
2442 PIS(OCP_ERR);
2443 PIS(VID1_FIFO_UNDERFLOW);
2444 PIS(VID1_END_WIN);
2445 PIS(VID2_FIFO_UNDERFLOW);
2446 PIS(VID2_END_WIN);
2447 PIS(SYNC_LOST);
2448 PIS(SYNC_LOST_DIGIT);
2449 PIS(WAKEUP);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2450 if (dss_has_feature(FEAT_MGR_LCD2)) {
2451 PIS(FRAMEDONE2);
2452 PIS(VSYNC2);
2453 PIS(ACBIAS_COUNT_STAT2);
2454 PIS(SYNC_LOST2);
2455 }
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2456#undef PIS
2457}
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2458#endif
2459
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2460void dispc_dump_regs(struct seq_file *s)
2461{
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2462#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2463
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2464 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2465
2466 DUMPREG(DISPC_REVISION);
2467 DUMPREG(DISPC_SYSCONFIG);
2468 DUMPREG(DISPC_SYSSTATUS);
2469 DUMPREG(DISPC_IRQSTATUS);
2470 DUMPREG(DISPC_IRQENABLE);
2471 DUMPREG(DISPC_CONTROL);
2472 DUMPREG(DISPC_CONFIG);
2473 DUMPREG(DISPC_CAPABLE);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2474 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2475 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2476 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2477 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2478 DUMPREG(DISPC_LINE_STATUS);
2479 DUMPREG(DISPC_LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2480 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2481 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2482 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2483 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2484 DUMPREG(DISPC_GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2485 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2486 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2487 if (dss_has_feature(FEAT_MGR_LCD2)) {
2488 DUMPREG(DISPC_CONTROL2);
2489 DUMPREG(DISPC_CONFIG2);
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2490 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2491 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2492 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2493 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2494 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2495 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2496 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2497 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2498
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2499 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2500 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2501 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2502 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2503 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2504 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2505 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2506 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2507 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2508 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2509 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2510
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2511 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2512 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2513 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2514
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2515 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2516 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2517 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2518 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2519 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2520 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2521 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2522
Archit Taneja702d1442011-05-06 11:45:50 +0530[diff] [blame]2523 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2524 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2525 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2526 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2527
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2528 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2529
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2530 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2531 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2532 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2533 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2534 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2535 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2536 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2537 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2538 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2539 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2540 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2541 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2542 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2543
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2544 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2545 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2546 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2547 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2548 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2549 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2550 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2551 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2552 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2553 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2554 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2555 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2556 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2557
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2558 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2559 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2560 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2561 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2562 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2563 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2564 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2565 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2566 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2567 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2568 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2569 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2570 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2571 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2572 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2573 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2574 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2575 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2576 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2577 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2578 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2579 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2580 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2581 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2582 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2583 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2584 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2585 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2586 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2587
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2588 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2589 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2590 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2591 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2592 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2593 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2594 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2595 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2596 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2597 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2598 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2599 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2600 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2601 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2602 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2603 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2604 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2605 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2606 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2607 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2608 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2609 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2610 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2611 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2612 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2613 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2614 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2615 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2616 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2617
Archit Taneja9b372c22011-05-06 11:45:49 +0530[diff] [blame]2618 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2619 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2620
Archit Taneja6af9cd12011-01-31 16:27:44 +0000[diff] [blame]2621 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2622#undef DUMPREG
2623}
2624
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2625static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2626 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2627{
2628 u32 l = 0;
2629
2630 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2631 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2632
2633 l |= FLD_VAL(onoff, 17, 17);
2634 l |= FLD_VAL(rf, 16, 16);
2635 l |= FLD_VAL(ieo, 15, 15);
2636 l |= FLD_VAL(ipc, 14, 14);
2637 l |= FLD_VAL(ihs, 13, 13);
2638 l |= FLD_VAL(ivs, 12, 12);
2639 l |= FLD_VAL(acbi, 11, 8);
2640 l |= FLD_VAL(acb, 7, 0);
2641
2642 enable_clocks(1);
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2643 dispc_write_reg(DISPC_POL_FREQ(channel), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2644 enable_clocks(0);
2645}
2646
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2647void dispc_set_pol_freq(enum omap_channel channel,
2648 enum omap_panel_config config, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2649{
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2650 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2651 (config & OMAP_DSS_LCD_RF) != 0,
2652 (config & OMAP_DSS_LCD_IEO) != 0,
2653 (config & OMAP_DSS_LCD_IPC) != 0,
2654 (config & OMAP_DSS_LCD_IHS) != 0,
2655 (config & OMAP_DSS_LCD_IVS) != 0,
2656 acbi, acb);
2657}
2658
2659/* with fck as input clock rate, find dispc dividers that produce req_pck */
2660void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2661 struct dispc_clock_info *cinfo)
2662{
2663 u16 pcd_min = is_tft ? 2 : 3;
2664 unsigned long best_pck;
2665 u16 best_ld, cur_ld;
2666 u16 best_pd, cur_pd;
2667
2668 best_pck = 0;
2669 best_ld = 0;
2670 best_pd = 0;
2671
2672 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2673 unsigned long lck = fck / cur_ld;
2674
2675 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2676 unsigned long pck = lck / cur_pd;
2677 long old_delta = abs(best_pck - req_pck);
2678 long new_delta = abs(pck - req_pck);
2679
2680 if (best_pck == 0 || new_delta < old_delta) {
2681 best_pck = pck;
2682 best_ld = cur_ld;
2683 best_pd = cur_pd;
2684
2685 if (pck == req_pck)
2686 goto found;
2687 }
2688
2689 if (pck < req_pck)
2690 break;
2691 }
2692
2693 if (lck / pcd_min < req_pck)
2694 break;
2695 }
2696
2697found:
2698 cinfo->lck_div = best_ld;
2699 cinfo->pck_div = best_pd;
2700 cinfo->lck = fck / cinfo->lck_div;
2701 cinfo->pck = cinfo->lck / cinfo->pck_div;
2702}
2703
2704/* calculate clock rates using dividers in cinfo */
2705int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2706 struct dispc_clock_info *cinfo)
2707{
2708 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2709 return -EINVAL;
2710 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2711 return -EINVAL;
2712
2713 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2714 cinfo->pck = cinfo->lck / cinfo->pck_div;
2715
2716 return 0;
2717}
2718
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2719int dispc_set_clock_div(enum omap_channel channel,
2720 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2721{
2722 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2723 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2724
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2725 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2726
2727 return 0;
2728}
2729
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000[diff] [blame]2730int dispc_get_clock_div(enum omap_channel channel,
2731 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2732{
2733 unsigned long fck;
2734
2735 fck = dispc_fclk_rate();
2736
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -0600[diff] [blame]2737 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2738 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2739
2740 cinfo->lck = fck / cinfo->lck_div;
2741 cinfo->pck = cinfo->lck / cinfo->pck_div;
2742
2743 return 0;
2744}
2745
2746/* dispc.irq_lock has to be locked by the caller */
2747static void _omap_dispc_set_irqs(void)
2748{
2749 u32 mask;
2750 u32 old_mask;
2751 int i;
2752 struct omap_dispc_isr_data *isr_data;
2753
2754 mask = dispc.irq_error_mask;
2755
2756 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2757 isr_data = &dispc.registered_isr[i];
2758
2759 if (isr_data->isr == NULL)
2760 continue;
2761
2762 mask |= isr_data->mask;
2763 }
2764
2765 enable_clocks(1);
2766
2767 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2768 /* clear the irqstatus for newly enabled irqs */
2769 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2770
2771 dispc_write_reg(DISPC_IRQENABLE, mask);
2772
2773 enable_clocks(0);
2774}
2775
2776int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2777{
2778 int i;
2779 int ret;
2780 unsigned long flags;
2781 struct omap_dispc_isr_data *isr_data;
2782
2783 if (isr == NULL)
2784 return -EINVAL;
2785
2786 spin_lock_irqsave(&dispc.irq_lock, flags);
2787
2788 /* check for duplicate entry */
2789 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2790 isr_data = &dispc.registered_isr[i];
2791 if (isr_data->isr == isr && isr_data->arg == arg &&
2792 isr_data->mask == mask) {
2793 ret = -EINVAL;
2794 goto err;
2795 }
2796 }
2797
2798 isr_data = NULL;
2799 ret = -EBUSY;
2800
2801 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2802 isr_data = &dispc.registered_isr[i];
2803
2804 if (isr_data->isr != NULL)
2805 continue;
2806
2807 isr_data->isr = isr;
2808 isr_data->arg = arg;
2809 isr_data->mask = mask;
2810 ret = 0;
2811
2812 break;
2813 }
2814
Tomi Valkeinenb9cb0982011-03-04 18:19:54 +0200[diff] [blame]2815 if (ret)
2816 goto err;
2817
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2818 _omap_dispc_set_irqs();
2819
2820 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2821
2822 return 0;
2823err:
2824 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2825
2826 return ret;
2827}
2828EXPORT_SYMBOL(omap_dispc_register_isr);
2829
2830int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2831{
2832 int i;
2833 unsigned long flags;
2834 int ret = -EINVAL;
2835 struct omap_dispc_isr_data *isr_data;
2836
2837 spin_lock_irqsave(&dispc.irq_lock, flags);
2838
2839 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2840 isr_data = &dispc.registered_isr[i];
2841 if (isr_data->isr != isr || isr_data->arg != arg ||
2842 isr_data->mask != mask)
2843 continue;
2844
2845 /* found the correct isr */
2846
2847 isr_data->isr = NULL;
2848 isr_data->arg = NULL;
2849 isr_data->mask = 0;
2850
2851 ret = 0;
2852 break;
2853 }
2854
2855 if (ret == 0)
2856 _omap_dispc_set_irqs();
2857
2858 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2859
2860 return ret;
2861}
2862EXPORT_SYMBOL(omap_dispc_unregister_isr);
2863
2864#ifdef DEBUG
2865static void print_irq_status(u32 status)
2866{
2867 if ((status & dispc.irq_error_mask) == 0)
2868 return;
2869
2870 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2871
2872#define PIS(x) \
2873 if (status & DISPC_IRQ_##x) \
2874 printk(#x " ");
2875 PIS(GFX_FIFO_UNDERFLOW);
2876 PIS(OCP_ERR);
2877 PIS(VID1_FIFO_UNDERFLOW);
2878 PIS(VID2_FIFO_UNDERFLOW);
2879 PIS(SYNC_LOST);
2880 PIS(SYNC_LOST_DIGIT);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]2881 if (dss_has_feature(FEAT_MGR_LCD2))
2882 PIS(SYNC_LOST2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2883#undef PIS
2884
2885 printk("\n");
2886}
2887#endif
2888
2889/* Called from dss.c. Note that we don't touch clocks here,
2890 * but we presume they are on because we got an IRQ. However,
2891 * an irq handler may turn the clocks off, so we may not have
2892 * clock later in the function. */
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2893static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2894{
2895 int i;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2896 u32 irqstatus, irqenable;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2897 u32 handledirqs = 0;
2898 u32 unhandled_errors;
2899 struct omap_dispc_isr_data *isr_data;
2900 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2901
2902 spin_lock(&dispc.irq_lock);
2903
2904 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2905 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2906
2907 /* IRQ is not for us */
2908 if (!(irqstatus & irqenable)) {
2909 spin_unlock(&dispc.irq_lock);
2910 return IRQ_NONE;
2911 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2912
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200[diff] [blame]2913#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2914 spin_lock(&dispc.irq_stats_lock);
2915 dispc.irq_stats.irq_count++;
2916 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2917 spin_unlock(&dispc.irq_stats_lock);
2918#endif
2919
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2920#ifdef DEBUG
2921 if (dss_debug)
2922 print_irq_status(irqstatus);
2923#endif
2924 /* Ack the interrupt. Do it here before clocks are possibly turned
2925 * off */
2926 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2927 /* flush posted write */
2928 dispc_read_reg(DISPC_IRQSTATUS);
2929
2930 /* make a copy and unlock, so that isrs can unregister
2931 * themselves */
2932 memcpy(registered_isr, dispc.registered_isr,
2933 sizeof(registered_isr));
2934
2935 spin_unlock(&dispc.irq_lock);
2936
2937 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2938 isr_data = &registered_isr[i];
2939
2940 if (!isr_data->isr)
2941 continue;
2942
2943 if (isr_data->mask & irqstatus) {
2944 isr_data->isr(isr_data->arg, irqstatus);
2945 handledirqs |= isr_data->mask;
2946 }
2947 }
2948
2949 spin_lock(&dispc.irq_lock);
2950
2951 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2952
2953 if (unhandled_errors) {
2954 dispc.error_irqs |= unhandled_errors;
2955
2956 dispc.irq_error_mask &= ~unhandled_errors;
2957 _omap_dispc_set_irqs();
2958
2959 schedule_work(&dispc.error_work);
2960 }
2961
2962 spin_unlock(&dispc.irq_lock);
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]2963
2964 return IRQ_HANDLED;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]2965}
2966
2967static void dispc_error_worker(struct work_struct *work)
2968{
2969 int i;
2970 u32 errors;
2971 unsigned long flags;
2972
2973 spin_lock_irqsave(&dispc.irq_lock, flags);
2974 errors = dispc.error_irqs;
2975 dispc.error_irqs = 0;
2976 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2977
2978 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2979 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2980 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2981 struct omap_overlay *ovl;
2982 ovl = omap_dss_get_overlay(i);
2983
2984 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2985 continue;
2986
2987 if (ovl->id == 0) {
2988 dispc_enable_plane(ovl->id, 0);
2989 dispc_go(ovl->manager->id);
2990 mdelay(50);
2991 break;
2992 }
2993 }
2994 }
2995
2996 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2997 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2998 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2999 struct omap_overlay *ovl;
3000 ovl = omap_dss_get_overlay(i);
3001
3002 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3003 continue;
3004
3005 if (ovl->id == 1) {
3006 dispc_enable_plane(ovl->id, 0);
3007 dispc_go(ovl->manager->id);
3008 mdelay(50);
3009 break;
3010 }
3011 }
3012 }
3013
3014 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3015 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3016 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3017 struct omap_overlay *ovl;
3018 ovl = omap_dss_get_overlay(i);
3019
3020 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3021 continue;
3022
3023 if (ovl->id == 2) {
3024 dispc_enable_plane(ovl->id, 0);
3025 dispc_go(ovl->manager->id);
3026 mdelay(50);
3027 break;
3028 }
3029 }
3030 }
3031
3032 if (errors & DISPC_IRQ_SYNC_LOST) {
3033 struct omap_overlay_manager *manager = NULL;
3034 bool enable = false;
3035
3036 DSSERR("SYNC_LOST, disabling LCD\n");
3037
3038 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3039 struct omap_overlay_manager *mgr;
3040 mgr = omap_dss_get_overlay_manager(i);
3041
3042 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3043 manager = mgr;
3044 enable = mgr->device->state ==
3045 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3046 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3047 break;
3048 }
3049 }
3050
3051 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3052 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3053 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3054 struct omap_overlay *ovl;
3055 ovl = omap_dss_get_overlay(i);
3056
3057 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3058 continue;
3059
3060 if (ovl->id != 0 && ovl->manager == manager)
3061 dispc_enable_plane(ovl->id, 0);
3062 }
3063
3064 dispc_go(manager->id);
3065 mdelay(50);
3066 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3067 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3068 }
3069 }
3070
3071 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3072 struct omap_overlay_manager *manager = NULL;
3073 bool enable = false;
3074
3075 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3076
3077 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3078 struct omap_overlay_manager *mgr;
3079 mgr = omap_dss_get_overlay_manager(i);
3080
3081 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3082 manager = mgr;
3083 enable = mgr->device->state ==
3084 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3085 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3086 break;
3087 }
3088 }
3089
3090 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3091 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3092 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3093 struct omap_overlay *ovl;
3094 ovl = omap_dss_get_overlay(i);
3095
3096 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3097 continue;
3098
3099 if (ovl->id != 0 && ovl->manager == manager)
3100 dispc_enable_plane(ovl->id, 0);
3101 }
3102
3103 dispc_go(manager->id);
3104 mdelay(50);
3105 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3106 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3107 }
3108 }
3109
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]3110 if (errors & DISPC_IRQ_SYNC_LOST2) {
3111 struct omap_overlay_manager *manager = NULL;
3112 bool enable = false;
3113
3114 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3115
3116 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3117 struct omap_overlay_manager *mgr;
3118 mgr = omap_dss_get_overlay_manager(i);
3119
3120 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3121 manager = mgr;
3122 enable = mgr->device->state ==
3123 OMAP_DSS_DISPLAY_ACTIVE;
3124 mgr->device->driver->disable(mgr->device);
3125 break;
3126 }
3127 }
3128
3129 if (manager) {
3130 struct omap_dss_device *dssdev = manager->device;
3131 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3132 struct omap_overlay *ovl;
3133 ovl = omap_dss_get_overlay(i);
3134
3135 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3136 continue;
3137
3138 if (ovl->id != 0 && ovl->manager == manager)
3139 dispc_enable_plane(ovl->id, 0);
3140 }
3141
3142 dispc_go(manager->id);
3143 mdelay(50);
3144 if (enable)
3145 dssdev->driver->enable(dssdev);
3146 }
3147 }
3148
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3149 if (errors & DISPC_IRQ_OCP_ERR) {
3150 DSSERR("OCP_ERR\n");
3151 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3152 struct omap_overlay_manager *mgr;
3153 mgr = omap_dss_get_overlay_manager(i);
3154
3155 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +0200[diff] [blame]3156 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3157 }
3158 }
3159
3160 spin_lock_irqsave(&dispc.irq_lock, flags);
3161 dispc.irq_error_mask |= errors;
3162 _omap_dispc_set_irqs();
3163 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3164}
3165
3166int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3167{
3168 void dispc_irq_wait_handler(void *data, u32 mask)
3169 {
3170 complete((struct completion *)data);
3171 }
3172
3173 int r;
3174 DECLARE_COMPLETION_ONSTACK(completion);
3175
3176 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3177 irqmask);
3178
3179 if (r)
3180 return r;
3181
3182 timeout = wait_for_completion_timeout(&completion, timeout);
3183
3184 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3185
3186 if (timeout == 0)
3187 return -ETIMEDOUT;
3188
3189 if (timeout == -ERESTARTSYS)
3190 return -ERESTARTSYS;
3191
3192 return 0;
3193}
3194
3195int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3196 unsigned long timeout)
3197{
3198 void dispc_irq_wait_handler(void *data, u32 mask)
3199 {
3200 complete((struct completion *)data);
3201 }
3202
3203 int r;
3204 DECLARE_COMPLETION_ONSTACK(completion);
3205
3206 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3207 irqmask);
3208
3209 if (r)
3210 return r;
3211
3212 timeout = wait_for_completion_interruptible_timeout(&completion,
3213 timeout);
3214
3215 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3216
3217 if (timeout == 0)
3218 return -ETIMEDOUT;
3219
3220 if (timeout == -ERESTARTSYS)
3221 return -ERESTARTSYS;
3222
3223 return 0;
3224}
3225
3226#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3227void dispc_fake_vsync_irq(void)
3228{
3229 u32 irqstatus = DISPC_IRQ_VSYNC;
3230 int i;
3231
Tomi Valkeinenab83b142010-06-09 15:31:01 +0300[diff] [blame]3232 WARN_ON(!in_interrupt());
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3233
3234 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3235 struct omap_dispc_isr_data *isr_data;
3236 isr_data = &dispc.registered_isr[i];
3237
3238 if (!isr_data->isr)
3239 continue;
3240
3241 if (isr_data->mask & irqstatus)
3242 isr_data->isr(isr_data->arg, irqstatus);
3243 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3244}
3245#endif
3246
3247static void _omap_dispc_initialize_irq(void)
3248{
3249 unsigned long flags;
3250
3251 spin_lock_irqsave(&dispc.irq_lock, flags);
3252
3253 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3254
3255 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000[diff] [blame]3256 if (dss_has_feature(FEAT_MGR_LCD2))
3257 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3258
3259 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3260 * so clear it */
3261 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3262
3263 _omap_dispc_set_irqs();
3264
3265 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3266}
3267
3268void dispc_enable_sidle(void)
3269{
3270 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3271}
3272
3273void dispc_disable_sidle(void)
3274{
3275 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3276}
3277
3278static void _omap_dispc_initial_config(void)
3279{
3280 u32 l;
3281
3282 l = dispc_read_reg(DISPC_SYSCONFIG);
3283 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3284 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3285 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3286 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3287 dispc_write_reg(DISPC_SYSCONFIG, l);
3288
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600[diff] [blame]3289 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3290 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3291 l = dispc_read_reg(DISPC_DIVISOR);
3292 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3293 l = FLD_MOD(l, 1, 0, 0);
3294 l = FLD_MOD(l, 1, 23, 16);
3295 dispc_write_reg(DISPC_DIVISOR, l);
3296 }
3297
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3298 /* FUNCGATED */
Archit Taneja6ced40b2010-12-02 11:27:13 +0000[diff] [blame]3299 if (dss_has_feature(FEAT_FUNCGATED))
3300 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3301
3302 /* L3 firewall setting: enable access to OCM RAM */
3303 /* XXX this should be somewhere in plat-omap */
3304 if (cpu_is_omap24xx())
3305 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3306
3307 _dispc_setup_color_conv_coef();
3308
3309 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3310
3311 dispc_read_plane_fifo_sizes();
3312}
3313
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3314int dispc_enable_plane(enum omap_plane plane, bool enable)
3315{
3316 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3317
3318 enable_clocks(1);
3319 _dispc_enable_plane(plane, enable);
3320 enable_clocks(0);
3321
3322 return 0;
3323}
3324
3325int dispc_setup_plane(enum omap_plane plane,
3326 u32 paddr, u16 screen_width,
3327 u16 pos_x, u16 pos_y,
3328 u16 width, u16 height,
3329 u16 out_width, u16 out_height,
3330 enum omap_color_mode color_mode,
3331 bool ilace,
3332 enum omap_dss_rotation_type rotation_type,
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]3333 u8 rotation, bool mirror, u8 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3334 u8 pre_mult_alpha, enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3335{
3336 int r = 0;
3337
3338 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3339 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3340 plane, paddr, screen_width, pos_x, pos_y,
3341 width, height,
3342 out_width, out_height,
3343 ilace, color_mode,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3344 rotation, mirror, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3345
3346 enable_clocks(1);
3347
3348 r = _dispc_setup_plane(plane,
3349 paddr, screen_width,
3350 pos_x, pos_y,
3351 width, height,
3352 out_width, out_height,
3353 color_mode, ilace,
3354 rotation_type,
3355 rotation, mirror,
Rajkumar Nfd28a392010-11-04 12:28:42 +0100[diff] [blame]3356 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +0000[diff] [blame]3357 pre_mult_alpha, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200[diff] [blame]3358
3359 enable_clocks(0);
3360
3361 return r;
3362}
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3363
3364/* DISPC HW IP initialisation */
3365static int omap_dispchw_probe(struct platform_device *pdev)
3366{
3367 u32 rev;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3368 int r = 0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3369 struct resource *dispc_mem;
3370
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3371 dispc.pdev = pdev;
3372
3373 spin_lock_init(&dispc.irq_lock);
3374
3375#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3376 spin_lock_init(&dispc.irq_stats_lock);
3377 dispc.irq_stats.last_reset = jiffies;
3378#endif
3379
3380 INIT_WORK(&dispc.error_work, dispc_error_worker);
3381
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3382 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3383 if (!dispc_mem) {
3384 DSSERR("can't get IORESOURCE_MEM DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3385 r = -EINVAL;
3386 goto fail0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +0000[diff] [blame]3387 }
3388 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3389 if (!dispc.base) {
3390 DSSERR("can't ioremap DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3391 r = -ENOMEM;
3392 goto fail0;
3393 }
3394 dispc.irq = platform_get_irq(dispc.pdev, 0);
3395 if (dispc.irq < 0) {
3396 DSSERR("platform_get_irq failed\n");
3397 r = -ENODEV;
3398 goto fail1;
3399 }
3400
3401 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3402 "OMAP DISPC", dispc.pdev);
3403 if (r < 0) {
3404 DSSERR("request_irq failed\n");
3405 goto fail1;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3406 }
3407
3408 enable_clocks(1);
3409
3410 _omap_dispc_initial_config();
3411
3412 _omap_dispc_initialize_irq();
3413
3414 dispc_save_context();
3415
3416 rev = dispc_read_reg(DISPC_REVISION);
Sumit Semwala06b62f2011-01-24 06:22:03 +0000[diff] [blame]3417 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3418 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3419
3420 enable_clocks(0);
3421
3422 return 0;
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3423fail1:
3424 iounmap(dispc.base);
3425fail0:
3426 return r;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3427}
3428
3429static int omap_dispchw_remove(struct platform_device *pdev)
3430{
archit tanejaaffe3602011-02-23 08:41:03 +0000[diff] [blame]3431 free_irq(dispc.irq, dispc.pdev);
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +0000[diff] [blame]3432 iounmap(dispc.base);
3433 return 0;
3434}
3435
3436static struct platform_driver omap_dispchw_driver = {
3437 .probe = omap_dispchw_probe,
3438 .remove = omap_dispchw_remove,
3439 .driver = {
3440 .name = "omapdss_dispc",
3441 .owner = THIS_MODULE,
3442 },
3443};
3444
3445int dispc_init_platform_driver(void)
3446{
3447 return platform_driver_register(&omap_dispchw_driver);
3448}
3449
3450void dispc_uninit_platform_driver(void)
3451{
3452 return platform_driver_unregister(&omap_dispchw_driver);
3453}