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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * gdb-low.S contains the low-level trap handler for the GDB stub.
3 *
4 * Copyright (C) 1995 Andreas Busse
5 */
6#include <linux/config.h>
7#include <linux/sys.h>
8
9#include <asm/asm.h>
10#include <asm/errno.h>
11#include <asm/mipsregs.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/gdb-stub.h>
15
Ralf Baechle875d43e2005-09-03 15:56:16 -070016#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#define DMFC0 mfc0
18#define DMTC0 mtc0
19#define LDC1 lwc1
20#define SDC1 lwc1
21#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -070022#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#define DMFC0 dmfc0
24#define DMTC0 dmtc0
25#define LDC1 ldc1
26#define SDC1 ldc1
27#endif
28
29/*
30 * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)
31 * part is used to store registers and passed to exception handler.
32 * The upper part is reserved for "call func" feature where gdb client
33 * saves some of the regs, setups call frame and passes args.
34 *
35 * A trace shows about 200 bytes are used to store about half of all regs.
36 * The rest should be big enough for frame setup and passing args.
37 */
38
39/*
40 * The low level trap handler
41 */
42 .align 5
43 NESTED(trap_low, GDB_FR_SIZE, sp)
44 .set noat
45 .set noreorder
46
47 mfc0 k0, CP0_STATUS
48 sll k0, 3 /* extract cu0 bit */
49 bltz k0, 1f
50 move k1, sp
51
52 /*
53 * Called from user mode, go somewhere else.
54 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 mfc0 k0, CP0_CAUSE
56 andi k0, k0, 0x7c
57 add k1, k1, k0
Ralf Baechlef4c72cc2005-10-18 13:25:29 +010058 PTR_L k0, saved_vectors(k1)
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 jr k0
60 nop
611:
62 move k0, sp
Ralf Baechlef4c72cc2005-10-18 13:25:29 +010063 PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 LONG_S k0, GDB_FR_REG29(sp)
65 LONG_S $2, GDB_FR_REG2(sp)
66
67/*
68 * First save the CP0 and special registers
69 */
70
71 mfc0 v0, CP0_STATUS
72 LONG_S v0, GDB_FR_STATUS(sp)
73 mfc0 v0, CP0_CAUSE
74 LONG_S v0, GDB_FR_CAUSE(sp)
75 DMFC0 v0, CP0_EPC
76 LONG_S v0, GDB_FR_EPC(sp)
77 DMFC0 v0, CP0_BADVADDR
78 LONG_S v0, GDB_FR_BADVADDR(sp)
79 mfhi v0
80 LONG_S v0, GDB_FR_HI(sp)
81 mflo v0
82 LONG_S v0, GDB_FR_LO(sp)
83
84/*
85 * Now the integer registers
86 */
87
88 LONG_S zero, GDB_FR_REG0(sp) /* I know... */
89 LONG_S $1, GDB_FR_REG1(sp)
90 /* v0 already saved */
91 LONG_S $3, GDB_FR_REG3(sp)
92 LONG_S $4, GDB_FR_REG4(sp)
93 LONG_S $5, GDB_FR_REG5(sp)
94 LONG_S $6, GDB_FR_REG6(sp)
95 LONG_S $7, GDB_FR_REG7(sp)
96 LONG_S $8, GDB_FR_REG8(sp)
97 LONG_S $9, GDB_FR_REG9(sp)
98 LONG_S $10, GDB_FR_REG10(sp)
99 LONG_S $11, GDB_FR_REG11(sp)
100 LONG_S $12, GDB_FR_REG12(sp)
101 LONG_S $13, GDB_FR_REG13(sp)
102 LONG_S $14, GDB_FR_REG14(sp)
103 LONG_S $15, GDB_FR_REG15(sp)
104 LONG_S $16, GDB_FR_REG16(sp)
105 LONG_S $17, GDB_FR_REG17(sp)
106 LONG_S $18, GDB_FR_REG18(sp)
107 LONG_S $19, GDB_FR_REG19(sp)
108 LONG_S $20, GDB_FR_REG20(sp)
109 LONG_S $21, GDB_FR_REG21(sp)
110 LONG_S $22, GDB_FR_REG22(sp)
111 LONG_S $23, GDB_FR_REG23(sp)
112 LONG_S $24, GDB_FR_REG24(sp)
113 LONG_S $25, GDB_FR_REG25(sp)
114 LONG_S $26, GDB_FR_REG26(sp)
115 LONG_S $27, GDB_FR_REG27(sp)
116 LONG_S $28, GDB_FR_REG28(sp)
117 /* sp already saved */
118 LONG_S $30, GDB_FR_REG30(sp)
119 LONG_S $31, GDB_FR_REG31(sp)
120
121 CLI /* disable interrupts */
122
123/*
124 * Followed by the floating point registers
125 */
126 mfc0 v0, CP0_STATUS /* FPU enabled? */
127 srl v0, v0, 16
128 andi v0, v0, (ST0_CU1 >> 16)
129
130 beqz v0,2f /* disabled, skip */
131 nop
132
133 SDC1 $0, GDB_FR_FPR0(sp)
134 SDC1 $1, GDB_FR_FPR1(sp)
135 SDC1 $2, GDB_FR_FPR2(sp)
136 SDC1 $3, GDB_FR_FPR3(sp)
137 SDC1 $4, GDB_FR_FPR4(sp)
138 SDC1 $5, GDB_FR_FPR5(sp)
139 SDC1 $6, GDB_FR_FPR6(sp)
140 SDC1 $7, GDB_FR_FPR7(sp)
141 SDC1 $8, GDB_FR_FPR8(sp)
142 SDC1 $9, GDB_FR_FPR9(sp)
143 SDC1 $10, GDB_FR_FPR10(sp)
144 SDC1 $11, GDB_FR_FPR11(sp)
145 SDC1 $12, GDB_FR_FPR12(sp)
146 SDC1 $13, GDB_FR_FPR13(sp)
147 SDC1 $14, GDB_FR_FPR14(sp)
148 SDC1 $15, GDB_FR_FPR15(sp)
149 SDC1 $16, GDB_FR_FPR16(sp)
150 SDC1 $17, GDB_FR_FPR17(sp)
151 SDC1 $18, GDB_FR_FPR18(sp)
152 SDC1 $19, GDB_FR_FPR19(sp)
153 SDC1 $20, GDB_FR_FPR20(sp)
154 SDC1 $21, GDB_FR_FPR21(sp)
155 SDC1 $22, GDB_FR_FPR22(sp)
156 SDC1 $23, GDB_FR_FPR23(sp)
157 SDC1 $24, GDB_FR_FPR24(sp)
158 SDC1 $25, GDB_FR_FPR25(sp)
159 SDC1 $26, GDB_FR_FPR26(sp)
160 SDC1 $27, GDB_FR_FPR27(sp)
161 SDC1 $28, GDB_FR_FPR28(sp)
162 SDC1 $29, GDB_FR_FPR29(sp)
163 SDC1 $30, GDB_FR_FPR30(sp)
164 SDC1 $31, GDB_FR_FPR31(sp)
165
166/*
167 * FPU control registers
168 */
169
170 cfc1 v0, CP1_STATUS
171 LONG_S v0, GDB_FR_FSR(sp)
172 cfc1 v0, CP1_REVISION
173 LONG_S v0, GDB_FR_FIR(sp)
174
175/*
176 * Current stack frame ptr
177 */
178
1792:
180 LONG_S sp, GDB_FR_FRP(sp)
181
182/*
183 * CP0 registers (R4000/R4400 unused registers skipped)
184 */
185
186 mfc0 v0, CP0_INDEX
187 LONG_S v0, GDB_FR_CP0_INDEX(sp)
188 mfc0 v0, CP0_RANDOM
189 LONG_S v0, GDB_FR_CP0_RANDOM(sp)
190 DMFC0 v0, CP0_ENTRYLO0
191 LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp)
192 DMFC0 v0, CP0_ENTRYLO1
193 LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp)
194 DMFC0 v0, CP0_CONTEXT
195 LONG_S v0, GDB_FR_CP0_CONTEXT(sp)
196 mfc0 v0, CP0_PAGEMASK
197 LONG_S v0, GDB_FR_CP0_PAGEMASK(sp)
198 mfc0 v0, CP0_WIRED
199 LONG_S v0, GDB_FR_CP0_WIRED(sp)
200 DMFC0 v0, CP0_ENTRYHI
201 LONG_S v0, GDB_FR_CP0_ENTRYHI(sp)
202 mfc0 v0, CP0_PRID
203 LONG_S v0, GDB_FR_CP0_PRID(sp)
204
205 .set at
206
207/*
208 * Continue with the higher level handler
209 */
210
211 move a0,sp
212
213 jal handle_exception
214 nop
215
216/*
217 * Restore all writable registers, in reverse order
218 */
219
220 .set noat
221
222 LONG_L v0, GDB_FR_CP0_ENTRYHI(sp)
223 LONG_L v1, GDB_FR_CP0_WIRED(sp)
224 DMTC0 v0, CP0_ENTRYHI
225 mtc0 v1, CP0_WIRED
226 LONG_L v0, GDB_FR_CP0_PAGEMASK(sp)
227 LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp)
228 mtc0 v0, CP0_PAGEMASK
229 DMTC0 v1, CP0_ENTRYLO1
230 LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp)
231 LONG_L v1, GDB_FR_CP0_INDEX(sp)
232 DMTC0 v0, CP0_ENTRYLO0
233 LONG_L v0, GDB_FR_CP0_CONTEXT(sp)
234 mtc0 v1, CP0_INDEX
235 DMTC0 v0, CP0_CONTEXT
236
237
238/*
239 * Next, the floating point registers
240 */
241 mfc0 v0, CP0_STATUS /* check if the FPU is enabled */
242 srl v0, v0, 16
243 andi v0, v0, (ST0_CU1 >> 16)
244
245 beqz v0, 3f /* disabled, skip */
246 nop
247
248 LDC1 $31, GDB_FR_FPR31(sp)
249 LDC1 $30, GDB_FR_FPR30(sp)
250 LDC1 $29, GDB_FR_FPR29(sp)
251 LDC1 $28, GDB_FR_FPR28(sp)
252 LDC1 $27, GDB_FR_FPR27(sp)
253 LDC1 $26, GDB_FR_FPR26(sp)
254 LDC1 $25, GDB_FR_FPR25(sp)
255 LDC1 $24, GDB_FR_FPR24(sp)
256 LDC1 $23, GDB_FR_FPR23(sp)
257 LDC1 $22, GDB_FR_FPR22(sp)
258 LDC1 $21, GDB_FR_FPR21(sp)
259 LDC1 $20, GDB_FR_FPR20(sp)
260 LDC1 $19, GDB_FR_FPR19(sp)
261 LDC1 $18, GDB_FR_FPR18(sp)
262 LDC1 $17, GDB_FR_FPR17(sp)
263 LDC1 $16, GDB_FR_FPR16(sp)
264 LDC1 $15, GDB_FR_FPR15(sp)
265 LDC1 $14, GDB_FR_FPR14(sp)
266 LDC1 $13, GDB_FR_FPR13(sp)
267 LDC1 $12, GDB_FR_FPR12(sp)
268 LDC1 $11, GDB_FR_FPR11(sp)
269 LDC1 $10, GDB_FR_FPR10(sp)
270 LDC1 $9, GDB_FR_FPR9(sp)
271 LDC1 $8, GDB_FR_FPR8(sp)
272 LDC1 $7, GDB_FR_FPR7(sp)
273 LDC1 $6, GDB_FR_FPR6(sp)
274 LDC1 $5, GDB_FR_FPR5(sp)
275 LDC1 $4, GDB_FR_FPR4(sp)
276 LDC1 $3, GDB_FR_FPR3(sp)
277 LDC1 $2, GDB_FR_FPR2(sp)
278 LDC1 $1, GDB_FR_FPR1(sp)
279 LDC1 $0, GDB_FR_FPR0(sp)
280
281/*
282 * Now the CP0 and integer registers
283 */
284
2853:
286 mfc0 t0, CP0_STATUS
287 ori t0, 0x1f
288 xori t0, 0x1f
289 mtc0 t0, CP0_STATUS
290
291 LONG_L v0, GDB_FR_STATUS(sp)
292 LONG_L v1, GDB_FR_EPC(sp)
293 mtc0 v0, CP0_STATUS
294 DMTC0 v1, CP0_EPC
295 LONG_L v0, GDB_FR_HI(sp)
296 LONG_L v1, GDB_FR_LO(sp)
297 mthi v0
298 mtlo v1
299 LONG_L $31, GDB_FR_REG31(sp)
300 LONG_L $30, GDB_FR_REG30(sp)
301 LONG_L $28, GDB_FR_REG28(sp)
302 LONG_L $27, GDB_FR_REG27(sp)
303 LONG_L $26, GDB_FR_REG26(sp)
304 LONG_L $25, GDB_FR_REG25(sp)
305 LONG_L $24, GDB_FR_REG24(sp)
306 LONG_L $23, GDB_FR_REG23(sp)
307 LONG_L $22, GDB_FR_REG22(sp)
308 LONG_L $21, GDB_FR_REG21(sp)
309 LONG_L $20, GDB_FR_REG20(sp)
310 LONG_L $19, GDB_FR_REG19(sp)
311 LONG_L $18, GDB_FR_REG18(sp)
312 LONG_L $17, GDB_FR_REG17(sp)
313 LONG_L $16, GDB_FR_REG16(sp)
314 LONG_L $15, GDB_FR_REG15(sp)
315 LONG_L $14, GDB_FR_REG14(sp)
316 LONG_L $13, GDB_FR_REG13(sp)
317 LONG_L $12, GDB_FR_REG12(sp)
318 LONG_L $11, GDB_FR_REG11(sp)
319 LONG_L $10, GDB_FR_REG10(sp)
320 LONG_L $9, GDB_FR_REG9(sp)
321 LONG_L $8, GDB_FR_REG8(sp)
322 LONG_L $7, GDB_FR_REG7(sp)
323 LONG_L $6, GDB_FR_REG6(sp)
324 LONG_L $5, GDB_FR_REG5(sp)
325 LONG_L $4, GDB_FR_REG4(sp)
326 LONG_L $3, GDB_FR_REG3(sp)
327 LONG_L $2, GDB_FR_REG2(sp)
328 LONG_L $1, GDB_FR_REG1(sp)
329#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
330 LONG_L k0, GDB_FR_EPC(sp)
331 LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */
332 jr k0
333 rfe
334#else
335 LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */
336
337 .set mips3
338 eret
339 .set mips0
340#endif
341 .set at
342 .set reorder
343 END(trap_low)
344
345LEAF(kgdb_read_byte)
3464: lb t0, (a0)
347 sb t0, (a1)
348 li v0, 0
349 jr ra
350 .section __ex_table,"a"
351 PTR 4b, kgdbfault
352 .previous
353 END(kgdb_read_byte)
354
355LEAF(kgdb_write_byte)
3565: sb a0, (a1)
357 li v0, 0
358 jr ra
359 .section __ex_table,"a"
360 PTR 5b, kgdbfault
361 .previous
362 END(kgdb_write_byte)
363
364 .type kgdbfault@function
365 .ent kgdbfault
366
367kgdbfault: li v0, -EFAULT
368 jr ra
369 .end kgdbfault