Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / f70dba83669bf718c2f1731f0f58b8149e883593 / . / arch / arm / mach-omap2 / cm44xx.h
blob: 336d94889e5b50ee1e613bb88e7dacc18dff4a3d [file] [log] [blame]
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]1/*
2 * OMAP44xx CM1 & CM2 instance offset macros
3 *
Benoit Coussona6108552010-05-20 12:31:11 -0600[diff] [blame]4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
24
25
26/* CM1 */
27
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]28/* CM1.OCP_SOCKET_CM1 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]29#define OMAP4_REVISION_CM1_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]30#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]31#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]32#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
33
34/* CM1.CKGEN_CM1 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]35#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]36#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]37#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]38#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]39#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]40#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]41#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]42#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]43#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]44#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]45#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]46#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]47#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]48#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]49#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]50#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]51#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]52#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]53#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]54#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]55#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]56#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]57#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]58#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]59#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]60#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]61#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]62#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]63#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]64#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]65#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]66#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]67#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]68#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]69#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]70#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]71#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]72#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]73#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]74#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]75#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]76#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]77#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]78#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]79#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]80#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]81#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]82#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]83#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]84#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]85#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]86#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]87#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]88#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]89#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]90#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]91#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]92#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]93#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]94#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]95#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]96#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]97#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]98#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]99#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]100#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]101#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]102#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]103#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]104#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]105#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]106#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]107#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]108#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]109#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]110#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]111#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]112#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]113#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]114#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]115#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]116#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]117#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]118#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]119#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]120#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]121#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]122#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]123#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]124#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]125#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]126#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]127#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]128#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]129#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]130#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]131#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]132#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]133#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]134#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]135#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]136#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]137#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]138#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]139#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]140#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]141#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]142#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]143#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]144#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
145
146/* CM1.MPU_CM1 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]147#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]148#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]149#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]150#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]151#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]152#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]153#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]154#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
155
156/* CM1.TESLA_CM1 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]157#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]158#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]159#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]160#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]161#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]162#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]163#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]164#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
165
166/* CM1.ABE_CM1 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]167#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]168#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]169#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]170#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]171#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]172#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]173#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]174#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]175#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]176#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]177#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]178#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]179#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]180#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]181#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]182#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]183#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]184#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]185#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]186#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]187#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]188#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]189#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]190#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]191#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]192#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]193#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]194#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]195#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]196#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
197
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]198/* CM2 */
199
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]200/* CM2.OCP_SOCKET_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]201#define OMAP4_REVISION_CM2_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]202#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]203#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]204#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
205
206/* CM2.CKGEN_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]207#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]208#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]209#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]210#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]211#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]212#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]213#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]214#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]215#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]216#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]217#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]218#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]219#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]220#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]221#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]222#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]223#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]224#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]225#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]226#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]227#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]228#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]229#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]230#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]231#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]232#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]233#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]234#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]235#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]236#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]237#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]238#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]239#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]240#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]241#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]242#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]243#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]244#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]245#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]246#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]247#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]248#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]249#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]250#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]251#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]252#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]253#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]254#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]255#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]256#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]257#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]258#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]259#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]260#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]261#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]262#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]263#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]264#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]265#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]266#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]267#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]268#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]269#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]270#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]271#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]272#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]273#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]274#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]275#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]276#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]277#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]278#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]279#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]280#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]281#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]282#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]283#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]284#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]285#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]286#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
287
288/* CM2.ALWAYS_ON_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]289#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]290#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]291#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]292#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]293#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]294#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]295#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]296#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]297#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]298#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
299
300/* CM2.CORE_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]301#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]302#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]303#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]304#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]305#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]306#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]307#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]308#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]309#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]310#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]311#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]312#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]313#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]314#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]315#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]316#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]317#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]318#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]319#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]320#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]321#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]322#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]323#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]324#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]325#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]326#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]327#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]328#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]329#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]330#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]331#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]332#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]333#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]334#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]335#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]336#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]337#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]338#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]339#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]340#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]341#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]342#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]343#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]344#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]345#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]346#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]347#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]348#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]349#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]350#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]351#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]352#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]353#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]354#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]355#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]356#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]357#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]358#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]359#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]360#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]361#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]362#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]363#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]364#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]365#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]366#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]367#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]368#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]369#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]370#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]371#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]372#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]373#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]374#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]375#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]376#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]377#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]378#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]379#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]380#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]381#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]382#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
383
384/* CM2.IVAHD_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]385#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]386#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]387#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]388#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]389#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]390#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]391#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]392#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]393#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]394#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
395
396/* CM2.CAM_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]397#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]398#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]399#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]400#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]401#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]402#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]403#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]404#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]405#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]406#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
407
408/* CM2.DSS_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]409#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]410#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]411#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]412#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]413#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]414#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]415#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]416#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]417#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]418#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
419
420/* CM2.GFX_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]421#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]422#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]423#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]424#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]425#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]426#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]427#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]428#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
429
430/* CM2.L3INIT_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]431#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]432#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]433#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]434#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]435#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]436#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]437#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]438#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]439#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]440#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]441#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]442#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]443#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]444#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]445#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]446#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]447#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]448#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]449#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]450#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]451#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]452#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]453#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]454#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]455#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]456#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]457#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]458#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]459#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]460#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]461#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]462#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]463#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]464#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]465#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]466#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]467#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]468#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]469#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]470#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
471
472/* CM2.L4PER_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]473#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]474#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]475#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]476#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]477#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]478#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]479#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]480#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]481#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]482#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]483#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]484#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]485#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]486#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]487#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]488#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]489#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]490#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]491#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]492#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]493#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]494#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]495#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]496#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]497#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]498#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]499#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]500#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]501#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]502#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]503#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]504#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]505#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]506#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]507#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]508#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]509#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]510#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]511#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]512#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]513#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]514#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]515#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]516#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]517#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]518#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]519#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]520#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]521#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]522#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]523#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]524#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]525#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]526#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]527#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]528#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]529#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]530#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]531#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]532#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]533#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]534#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]535#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]536#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]537#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]538#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]539#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]540#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]541#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]542#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]543#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]544#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]545#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]546#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]547#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]548#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]549#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]550#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]551#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]552#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]553#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]554#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]555#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]556#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]557#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]558#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]559#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]560#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]561#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]562#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]563#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]564#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]565#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]566#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]567#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]568#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]569#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]570#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]571#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]572#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]573#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]574#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
575
576/* CM2.CEFUSE_CM2 register offsets */
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]577#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]578#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
Rajendra Nayakfe894d52010-05-20 12:31:12 -0600[diff] [blame]579#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]580#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]581#endif