| Paul Mundt | 5f24071 | 2010-01-20 15:23:54 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SDK7786 FPGA IRQ Controller Support. |
| 3 | * |
| 4 | * Copyright (C) 2010 Matt Fleming |
| 5 | * Copyright (C) 2010 Paul Mundt |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | #include <linux/irq.h> |
| 12 | #include <mach/fpga.h> |
| 13 | #include <mach/irq.h> |
| 14 | |
| 15 | enum { |
| 16 | ATA_IRQ_BIT = 1, |
| 17 | SPI_BUSY_BIT = 2, |
| 18 | LIRQ5_BIT = 3, |
| 19 | LIRQ6_BIT = 4, |
| 20 | LIRQ7_BIT = 5, |
| 21 | LIRQ8_BIT = 6, |
| 22 | KEY_IRQ_BIT = 7, |
| 23 | PEN_IRQ_BIT = 8, |
| 24 | ETH_IRQ_BIT = 9, |
| 25 | RTC_ALARM_BIT = 10, |
| 26 | CRYSTAL_FAIL_BIT = 12, |
| 27 | ETH_PME_BIT = 14, |
| 28 | }; |
| 29 | |
| 30 | void __init sdk7786_init_irq(void) |
| 31 | { |
| 32 | unsigned int tmp; |
| 33 | |
| 34 | /* Enable priority encoding for all IRLs */ |
| 35 | fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR); |
| 36 | |
| 37 | /* Clear FPGA interrupt status registers */ |
| 38 | fpga_write_reg(0x0000, INTASR); |
| 39 | fpga_write_reg(0x0000, INTBSR); |
| 40 | |
| 41 | /* Unmask FPGA interrupts */ |
| 42 | tmp = fpga_read_reg(INTAMR); |
| 43 | tmp &= ~(1 << ETH_IRQ_BIT); |
| 44 | fpga_write_reg(tmp, INTAMR); |
| 45 | |
| 46 | plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK); |
| 47 | plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); |
| 48 | } |