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Roland McGrath1eeaed72008-01-30 13:31:51 +01001/*
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
8 */
9
Vegard Nossum77ef50a2008-06-18 17:08:48 +020010#ifndef ASM_X86__I387_H
11#define ASM_X86__I387_H
Roland McGrath1eeaed72008-01-30 13:31:51 +010012
13#include <linux/sched.h>
14#include <linux/kernel_stat.h>
15#include <linux/regset.h>
Suresh Siddhae4914012008-08-13 22:02:26 +100016#include <linux/hardirq.h>
H. Peter Anvin92c37fa2008-02-04 16:47:58 +010017#include <asm/asm.h>
Roland McGrath1eeaed72008-01-30 13:31:51 +010018#include <asm/processor.h>
19#include <asm/sigcontext.h>
20#include <asm/user.h>
21#include <asm/uaccess.h>
22
23extern void fpu_init(void);
Roland McGrath1eeaed72008-01-30 13:31:51 +010024extern void mxcsr_feature_mask_init(void);
Suresh Siddhaaa283f42008-03-10 15:28:05 -070025extern int init_fpu(struct task_struct *child);
Roland McGrath1eeaed72008-01-30 13:31:51 +010026extern asmlinkage void math_state_restore(void);
Suresh Siddha61c46282008-03-10 15:28:04 -070027extern void init_thread_xstate(void);
Jaswinder Singh36454932008-07-21 22:31:57 +053028extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
Roland McGrath1eeaed72008-01-30 13:31:51 +010029
30extern user_regset_active_fn fpregs_active, xfpregs_active;
31extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
32extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
33
34#ifdef CONFIG_IA32_EMULATION
35struct _fpstate_ia32;
36extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
37extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
38#endif
39
40#ifdef CONFIG_X86_64
41
42/* Ignore delayed exceptions from user space */
43static inline void tolerant_fwait(void)
44{
45 asm volatile("1: fwait\n"
46 "2:\n"
Joe Perchesaffe6632008-03-23 01:02:18 -070047 _ASM_EXTABLE(1b, 2b));
Roland McGrath1eeaed72008-01-30 13:31:51 +010048}
49
50static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
51{
52 int err;
53
54 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
55 "2:\n"
56 ".section .fixup,\"ax\"\n"
57 "3: movl $-1,%[err]\n"
58 " jmp 2b\n"
59 ".previous\n"
Joe Perchesaffe6632008-03-23 01:02:18 -070060 _ASM_EXTABLE(1b, 3b)
Roland McGrath1eeaed72008-01-30 13:31:51 +010061 : [err] "=r" (err)
62#if 0 /* See comment in __save_init_fpu() below. */
63 : [fx] "r" (fx), "m" (*fx), "0" (0));
64#else
65 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
66#endif
Roland McGrath1eeaed72008-01-30 13:31:51 +010067 return err;
68}
69
70#define X87_FSW_ES (1 << 7) /* Exception Summary */
71
72/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
73 is pending. Clear the x87 state here by setting it to fixed
74 values. The kernel data segment can be sometimes 0 and sometimes
75 new user value. Both should be ok.
76 Use the PDA as safe address because it should be already in L1. */
77static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
78{
79 if (unlikely(fx->swd & X87_FSW_ES))
Joe Perchesaffe6632008-03-23 01:02:18 -070080 asm volatile("fnclex");
Roland McGrath1eeaed72008-01-30 13:31:51 +010081 alternative_input(ASM_NOP8 ASM_NOP2,
Joe Perchesaffe6632008-03-23 01:02:18 -070082 " emms\n" /* clear stack tags */
83 " fildl %%gs:0", /* load to clear state */
84 X86_FEATURE_FXSAVE_LEAK);
Roland McGrath1eeaed72008-01-30 13:31:51 +010085}
86
87static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
88{
89 int err;
90
91 asm volatile("1: rex64/fxsave (%[fx])\n\t"
92 "2:\n"
93 ".section .fixup,\"ax\"\n"
94 "3: movl $-1,%[err]\n"
95 " jmp 2b\n"
96 ".previous\n"
Joe Perchesaffe6632008-03-23 01:02:18 -070097 _ASM_EXTABLE(1b, 3b)
Roland McGrath1eeaed72008-01-30 13:31:51 +010098 : [err] "=r" (err), "=m" (*fx)
99#if 0 /* See comment in __fxsave_clear() below. */
100 : [fx] "r" (fx), "0" (0));
101#else
102 : [fx] "cdaSDb" (fx), "0" (0));
103#endif
Joe Perchesaffe6632008-03-23 01:02:18 -0700104 if (unlikely(err) &&
105 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
Roland McGrath1eeaed72008-01-30 13:31:51 +0100106 err = -EFAULT;
107 /* No need to clear here because the caller clears USED_MATH */
108 return err;
109}
110
111static inline void __save_init_fpu(struct task_struct *tsk)
112{
113 /* Using "rex64; fxsave %0" is broken because, if the memory operand
114 uses any extended registers for addressing, a second REX prefix
115 will be generated (to the assembler, rex64 followed by semicolon
116 is a separate instruction), and hence the 64-bitness is lost. */
117#if 0
118 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
119 starting with gas 2.16. */
120 __asm__ __volatile__("fxsaveq %0"
Suresh Siddha61c46282008-03-10 15:28:04 -0700121 : "=m" (tsk->thread.xstate->fxsave));
Roland McGrath1eeaed72008-01-30 13:31:51 +0100122#elif 0
123 /* Using, as a workaround, the properly prefixed form below isn't
124 accepted by any binutils version so far released, complaining that
125 the same type of prefix is used twice if an extended register is
126 needed for addressing (fix submitted to mainline 2005-11-21). */
127 __asm__ __volatile__("rex64/fxsave %0"
Suresh Siddha61c46282008-03-10 15:28:04 -0700128 : "=m" (tsk->thread.xstate->fxsave));
Roland McGrath1eeaed72008-01-30 13:31:51 +0100129#else
130 /* This, however, we can work around by forcing the compiler to select
131 an addressing mode that doesn't require extended registers. */
Suresh Siddha61c46282008-03-10 15:28:04 -0700132 __asm__ __volatile__("rex64/fxsave (%1)"
133 : "=m" (tsk->thread.xstate->fxsave)
134 : "cdaSDb" (&tsk->thread.xstate->fxsave));
Roland McGrath1eeaed72008-01-30 13:31:51 +0100135#endif
Suresh Siddha61c46282008-03-10 15:28:04 -0700136 clear_fpu_state(&tsk->thread.xstate->fxsave);
Roland McGrath1eeaed72008-01-30 13:31:51 +0100137 task_thread_info(tsk)->status &= ~TS_USEDFPU;
138}
139
Roland McGrath1eeaed72008-01-30 13:31:51 +0100140#else /* CONFIG_X86_32 */
141
Suresh Siddhae8a496a2008-05-23 16:26:37 -0700142extern void finit(void);
143
Roland McGrath1eeaed72008-01-30 13:31:51 +0100144static inline void tolerant_fwait(void)
145{
146 asm volatile("fnclex ; fwait");
147}
148
149static inline void restore_fpu(struct task_struct *tsk)
150{
151 /*
152 * The "nop" is needed to make the instructions the same
153 * length.
154 */
155 alternative_input(
156 "nop ; frstor %1",
157 "fxrstor %1",
158 X86_FEATURE_FXSR,
Suresh Siddha61c46282008-03-10 15:28:04 -0700159 "m" (tsk->thread.xstate->fxsave));
Roland McGrath1eeaed72008-01-30 13:31:51 +0100160}
161
162/* We need a safe address that is cheap to find and that is already
163 in L1 during context switch. The best choices are unfortunately
164 different for UP and SMP */
165#ifdef CONFIG_SMP
166#define safe_address (__per_cpu_offset[0])
167#else
168#define safe_address (kstat_cpu(0).cpustat.user)
169#endif
170
171/*
172 * These must be called with preempt disabled
173 */
174static inline void __save_init_fpu(struct task_struct *tsk)
175{
176 /* Use more nops than strictly needed in case the compiler
177 varies code */
178 alternative_input(
179 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
180 "fxsave %[fx]\n"
181 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
182 X86_FEATURE_FXSR,
Suresh Siddha61c46282008-03-10 15:28:04 -0700183 [fx] "m" (tsk->thread.xstate->fxsave),
184 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
Roland McGrath1eeaed72008-01-30 13:31:51 +0100185 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
186 is pending. Clear the x87 state here by setting it to fixed
187 values. safe_address is a random variable that should be in L1 */
188 alternative_input(
189 GENERIC_NOP8 GENERIC_NOP2,
190 "emms\n\t" /* clear stack tags */
191 "fildl %[addr]", /* set F?P to defined value */
192 X86_FEATURE_FXSAVE_LEAK,
193 [addr] "m" (safe_address));
194 task_thread_info(tsk)->status &= ~TS_USEDFPU;
195}
196
197/*
198 * Signal frame handlers...
199 */
200extern int save_i387(struct _fpstate __user *buf);
201extern int restore_i387(struct _fpstate __user *buf);
202
203#endif /* CONFIG_X86_64 */
204
205static inline void __unlazy_fpu(struct task_struct *tsk)
206{
207 if (task_thread_info(tsk)->status & TS_USEDFPU) {
208 __save_init_fpu(tsk);
209 stts();
210 } else
211 tsk->fpu_counter = 0;
212}
213
214static inline void __clear_fpu(struct task_struct *tsk)
215{
216 if (task_thread_info(tsk)->status & TS_USEDFPU) {
217 tolerant_fwait();
218 task_thread_info(tsk)->status &= ~TS_USEDFPU;
219 stts();
220 }
221}
222
223static inline void kernel_fpu_begin(void)
224{
225 struct thread_info *me = current_thread_info();
226 preempt_disable();
227 if (me->status & TS_USEDFPU)
228 __save_init_fpu(me->task);
229 else
230 clts();
231}
232
233static inline void kernel_fpu_end(void)
234{
235 stts();
236 preempt_enable();
237}
238
Suresh Siddhae4914012008-08-13 22:02:26 +1000239/*
240 * Some instructions like VIA's padlock instructions generate a spurious
241 * DNA fault but don't modify SSE registers. And these instructions
242 * get used from interrupt context aswell. To prevent these kernel instructions
243 * in interrupt context interact wrongly with other user/kernel fpu usage, we
244 * should use them only in the context of irq_ts_save/restore()
245 */
246static inline int irq_ts_save(void)
247{
248 /*
249 * If we are in process context, we are ok to take a spurious DNA fault.
250 * Otherwise, doing clts() in process context require pre-emption to
251 * be disabled or some heavy lifting like kernel_fpu_begin()
252 */
253 if (!in_interrupt())
254 return 0;
255
256 if (read_cr0() & X86_CR0_TS) {
257 clts();
258 return 1;
259 }
260
261 return 0;
262}
263
264static inline void irq_ts_restore(int TS_state)
265{
266 if (TS_state)
267 stts();
268}
269
Roland McGrath1eeaed72008-01-30 13:31:51 +0100270#ifdef CONFIG_X86_64
271
272static inline void save_init_fpu(struct task_struct *tsk)
273{
274 __save_init_fpu(tsk);
275 stts();
276}
277
278#define unlazy_fpu __unlazy_fpu
279#define clear_fpu __clear_fpu
280
281#else /* CONFIG_X86_32 */
282
283/*
284 * These disable preemption on their own and are safe
285 */
286static inline void save_init_fpu(struct task_struct *tsk)
287{
288 preempt_disable();
289 __save_init_fpu(tsk);
290 stts();
291 preempt_enable();
292}
293
294static inline void unlazy_fpu(struct task_struct *tsk)
295{
296 preempt_disable();
297 __unlazy_fpu(tsk);
298 preempt_enable();
299}
300
301static inline void clear_fpu(struct task_struct *tsk)
302{
303 preempt_disable();
304 __clear_fpu(tsk);
305 preempt_enable();
306}
307
308#endif /* CONFIG_X86_64 */
309
310/*
Roland McGrath1eeaed72008-01-30 13:31:51 +0100311 * i387 state interaction
312 */
313static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
314{
315 if (cpu_has_fxsr) {
Suresh Siddha61c46282008-03-10 15:28:04 -0700316 return tsk->thread.xstate->fxsave.cwd;
Roland McGrath1eeaed72008-01-30 13:31:51 +0100317 } else {
Suresh Siddha1679f272008-04-16 10:27:53 +0200318 return (unsigned short)tsk->thread.xstate->fsave.cwd;
Roland McGrath1eeaed72008-01-30 13:31:51 +0100319 }
320}
321
322static inline unsigned short get_fpu_swd(struct task_struct *tsk)
323{
324 if (cpu_has_fxsr) {
Suresh Siddha61c46282008-03-10 15:28:04 -0700325 return tsk->thread.xstate->fxsave.swd;
Roland McGrath1eeaed72008-01-30 13:31:51 +0100326 } else {
Suresh Siddha1679f272008-04-16 10:27:53 +0200327 return (unsigned short)tsk->thread.xstate->fsave.swd;
Roland McGrath1eeaed72008-01-30 13:31:51 +0100328 }
329}
330
331static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
332{
333 if (cpu_has_xmm) {
Suresh Siddha61c46282008-03-10 15:28:04 -0700334 return tsk->thread.xstate->fxsave.mxcsr;
Roland McGrath1eeaed72008-01-30 13:31:51 +0100335 } else {
336 return MXCSR_DEFAULT;
337 }
338}
339
Vegard Nossum77ef50a2008-06-18 17:08:48 +0200340#endif /* ASM_X86__I387_H */