blob: 9fb9fb60fbe0f70e0894dcd52fcfe284b39c82cb [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Daniel Walker8d747cd2010-02-25 11:37:43 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Daniel Walker8d747cd2010-02-25 11:37:43 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/bootmem.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080020#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#ifdef CONFIG_SPI_QSD
22#include <linux/spi/spi.h>
23#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053024#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <linux/mfd/pmic8058.h>
26#include <linux/mfd/marimba.h>
27#include <linux/i2c.h>
28#include <linux/input.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080029#include <linux/smsc911x.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030#include <linux/ofn_atlab.h>
31#include <linux/power_supply.h>
32#include <linux/input/pmic8058-keypad.h>
33#include <linux/i2c/isa1200.h>
34#include <linux/pwm.h>
35#include <linux/pmic8058-pwm.h>
36#include <linux/i2c/tsc2007.h>
37#include <linux/input/kp_flip_switch.h>
38#include <linux/leds-pmic8058.h>
39#include <linux/input/cy8c_ts.h>
40#include <linux/msm_adc.h>
41#include <linux/dma-mapping.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080042
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/setup.h>
46
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047#include <mach/mpp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080048#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070049#include <mach/camera.h>
50#include <mach/memory.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080051#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#include <mach/msm_hsusb.h>
53#include <mach/rpc_hsusb.h>
54#include <mach/msm_spi.h>
55#include <mach/qdsp5v2/msm_lpa.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080056#include <mach/dma.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070057#include <linux/android_pmem.h>
58#include <linux/input/msm_ts.h>
59#include <mach/pmic.h>
60#include <mach/rpc_pmapp.h>
61#include <mach/qdsp5v2/aux_pcm.h>
62#include <mach/qdsp5v2/mi2s.h>
63#include <mach/qdsp5v2/audio_dev_ctl.h>
64#include <mach/msm_battery.h>
65#include <mach/rpc_server_handset.h>
66#include <mach/msm_tsif.h>
67#include <mach/socinfo.h>
68#include <mach/msm_memtypes.h>
69#include <linux/cyttsp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080070
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#include <asm/mach/mmc.h>
72#include <asm/mach/flash.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080073#include <mach/vreg.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#include <linux/platform_data/qcom_crypto_device.h>
75
Daniel Walker8d747cd2010-02-25 11:37:43 -080076#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070077#include "timer.h"
78#ifdef CONFIG_USB_G_ANDROID
79#include <linux/usb/android.h>
80#include <mach/usbdiag.h>
81#endif
82#include "pm.h"
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -060083#include "pm-boot.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070084#include "spm.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -070085#include "acpuclock.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070086#include <mach/dal_axi.h>
87#include <mach/msm_serial_hs.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088#include <mach/qdsp5v2/mi2s.h>
89#include <mach/qdsp5v2/audio_dev_ctl.h>
90#include <mach/sdio_al.h>
91#include "smd_private.h"
92#include <linux/bma150.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080093
Justin Paupore637a25d2011-07-14 17:11:04 -070094#include "board-msm7x30-regulator.h"
95
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070096#define MSM_PMEM_SF_SIZE 0x1700000
97#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
98#define MSM_FB_SIZE 0x780000
99#else
100#define MSM_FB_SIZE 0x500000
101#endif
102#define MSM_PMEM_ADSP_SIZE 0x1E00000
103#define MSM_FLUID_PMEM_ADSP_SIZE 0x2800000
104#define PMEM_KERNEL_EBI0_SIZE 0x600000
105#define MSM_PMEM_AUDIO_SIZE 0x200000
Daniel Walker90e37c52010-05-12 14:24:15 -0700106
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700107#define PMIC_GPIO_INT 27
108#define PMIC_VREG_WLAN_LEVEL 2900
109#define PMIC_GPIO_SD_DET 36
110#define PMIC_GPIO_SDC4_EN_N 17 /* PMIC GPIO Number 18 */
111#define PMIC_GPIO_HDMI_5V_EN_V3 32 /* PMIC GPIO for V3 H/W */
112#define PMIC_GPIO_HDMI_5V_EN_V2 39 /* PMIC GPIO for V2 H/W */
113
114#define ADV7520_I2C_ADDR 0x39
115
116#define FPGA_SDCC_STATUS 0x8E0001A8
117
118#define FPGA_OPTNAV_GPIO_ADDR 0x8E000026
119#define OPTNAV_I2C_SLAVE_ADDR (0xB0 >> 1)
120#define OPTNAV_IRQ 20
121#define OPTNAV_CHIP_SELECT 19
122
123/* Macros assume PMIC GPIOs start at 0 */
124#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_GPIO_IRQS)
125#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_GPIO_IRQS)
126
127#define PMIC_GPIO_FLASH_BOOST_ENABLE 15 /* PMIC GPIO Number 16 */
128#define PMIC_GPIO_HAP_ENABLE 16 /* PMIC GPIO Number 17 */
129
130#define PMIC_GPIO_WLAN_EXT_POR 22 /* PMIC GPIO NUMBER 23 */
131
132#define BMA150_GPIO_INT 1
133
134#define HAP_LVL_SHFT_MSM_GPIO 24
135
136#define PMIC_GPIO_QUICKVX_CLK 37 /* PMIC GPIO 38 */
137
138#define PM_FLIP_MPP 5 /* PMIC MPP 06 */
139static int pm8058_gpios_init(void)
140{
141 int rc;
142 int pmic_gpio_hdmi_5v_en;
143
144#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
145 struct pm8058_gpio sdcc_det = {
146 .direction = PM_GPIO_DIR_IN,
147 .pull = PM_GPIO_PULL_UP_1P5,
148 .vin_sel = 2,
149 .function = PM_GPIO_FUNC_NORMAL,
150 .inv_int_pol = 0,
151 };
152#endif
153 struct pm8058_gpio sdc4_en = {
154 .direction = PM_GPIO_DIR_OUT,
155 .pull = PM_GPIO_PULL_NO,
156 .vin_sel = PM_GPIO_VIN_L5,
157 .function = PM_GPIO_FUNC_NORMAL,
158 .inv_int_pol = 0,
159 .out_strength = PM_GPIO_STRENGTH_LOW,
160 .output_value = 0,
161 };
162
163 struct pm8058_gpio haptics_enable = {
164 .direction = PM_GPIO_DIR_OUT,
165 .pull = PM_GPIO_PULL_NO,
166 .out_strength = PM_GPIO_STRENGTH_HIGH,
167 .function = PM_GPIO_FUNC_NORMAL,
168 .inv_int_pol = 0,
169 .vin_sel = 2,
170 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
171 .output_value = 0,
172 };
173
174 struct pm8058_gpio hdmi_5V_en = {
175 .direction = PM_GPIO_DIR_OUT,
176 .pull = PM_GPIO_PULL_NO,
177 .vin_sel = PM_GPIO_VIN_VPH,
178 .function = PM_GPIO_FUNC_NORMAL,
179 .out_strength = PM_GPIO_STRENGTH_LOW,
180 .output_value = 0,
181 };
182
183 struct pm8058_gpio flash_boost_enable = {
184 .direction = PM_GPIO_DIR_OUT,
185 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
186 .output_value = 0,
187 .pull = PM_GPIO_PULL_NO,
188 .vin_sel = PM_GPIO_VIN_S3,
189 .out_strength = PM_GPIO_STRENGTH_HIGH,
190 .function = PM_GPIO_FUNC_2,
191 };
192
193 struct pm8058_gpio gpio23 = {
194 .direction = PM_GPIO_DIR_OUT,
195 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
196 .output_value = 0,
197 .pull = PM_GPIO_PULL_NO,
198 .vin_sel = 2,
199 .out_strength = PM_GPIO_STRENGTH_LOW,
200 .function = PM_GPIO_FUNC_NORMAL,
201 };
202
203
204 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
205 machine_is_msm7x30_fluid())
206 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
207 else
208 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
209
210 if (machine_is_msm7x30_fluid()) {
211 rc = pm8058_gpio_config(PMIC_GPIO_HAP_ENABLE, &haptics_enable);
212 if (rc) {
213 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
214 (PMIC_GPIO_HAP_ENABLE + 1));
215 return rc;
216 }
217 rc = pm8058_gpio_config(PMIC_GPIO_FLASH_BOOST_ENABLE,
218 &flash_boost_enable);
219 if (rc) {
220 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
221 (PMIC_GPIO_FLASH_BOOST_ENABLE + 1));
222 return rc;
223 }
224 }
225
226#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
227 if (machine_is_msm7x30_fluid())
228 sdcc_det.inv_int_pol = 1;
229
230 rc = pm8058_gpio_config(PMIC_GPIO_SD_DET - 1, &sdcc_det);
231 if (rc) {
232 pr_err("%s PMIC_GPIO_SD_DET config failed\n", __func__);
233 return rc;
234 }
235#endif
236
237 rc = pm8058_gpio_config(pmic_gpio_hdmi_5v_en, &hdmi_5V_en);
238 if (rc) {
239 pr_err("%s PMIC_GPIO_HDMI_5V_EN config failed\n", __func__);
240 return rc;
241 }
242
243 /* Deassert GPIO#23 (source for Ext_POR on WLAN-Volans) */
244 rc = pm8058_gpio_config(PMIC_GPIO_WLAN_EXT_POR, &gpio23);
245 if (rc) {
246 pr_err("%s PMIC_GPIO_WLAN_EXT_POR config failed\n", __func__);
247 return rc;
248 }
249
250 if (machine_is_msm7x30_fluid()) {
251 rc = pm8058_gpio_config(PMIC_GPIO_SDC4_EN_N, &sdc4_en);
252 if (rc) {
253 pr_err("%s PMIC_GPIO_SDC4_EN_N config failed\n",
254 __func__);
255 return rc;
256 }
257 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N),
258 "sdc4_en");
259 if (rc) {
260 pr_err("%s PMIC_GPIO_SDC4_EN_N gpio_request failed\n",
261 __func__);
262 return rc;
263 }
264 gpio_set_value_cansleep(
265 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N), 0);
266 }
267
268 return 0;
269}
270
Justin Paupore637a25d2011-07-14 17:11:04 -0700271/* Regulator API support */
272
273#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
274static struct platform_device msm_proccomm_regulator_dev = {
275 .name = PROCCOMM_REGULATOR_DEV_NAME,
276 .id = -1,
277 .dev = {
278 .platform_data = &msm7x30_proccomm_regulator_data
279 }
280};
281#endif
282
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700283/*virtual key support */
284static ssize_t tma300_vkeys_show(struct kobject *kobj,
285 struct kobj_attribute *attr, char *buf)
286{
287 return sprintf(buf,
288 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":50:842:80:100"
289 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":170:842:80:100"
290 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":290:842:80:100"
291 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":410:842:80:100"
292 "\n");
293}
294
295static struct kobj_attribute tma300_vkeys_attr = {
296 .attr = {
297 .mode = S_IRUGO,
298 },
299 .show = &tma300_vkeys_show,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530300};
301
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700302static struct attribute *tma300_properties_attrs[] = {
303 &tma300_vkeys_attr.attr,
304 NULL
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530305};
306
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700307static struct attribute_group tma300_properties_attr_group = {
308 .attrs = tma300_properties_attrs,
309};
310
311static struct kobject *properties_kobj;
312
313#define CYTTSP_TS_GPIO_IRQ 150
314static int cyttsp_platform_init(struct i2c_client *client)
315{
316 int rc = -EINVAL;
317 struct vreg *vreg_ldo8, *vreg_ldo15;
318
319 vreg_ldo8 = vreg_get(NULL, "gp7");
320
321 if (!vreg_ldo8) {
322 pr_err("%s: VREG L8 get failed\n", __func__);
323 return rc;
324 }
325
326 rc = vreg_set_level(vreg_ldo8, 1800);
327 if (rc) {
328 pr_err("%s: VREG L8 set failed\n", __func__);
329 goto l8_put;
330 }
331
332 rc = vreg_enable(vreg_ldo8);
333 if (rc) {
334 pr_err("%s: VREG L8 enable failed\n", __func__);
335 goto l8_put;
336 }
337
338 vreg_ldo15 = vreg_get(NULL, "gp6");
339
340 if (!vreg_ldo15) {
341 pr_err("%s: VREG L15 get failed\n", __func__);
342 goto l8_disable;
343 }
344
345 rc = vreg_set_level(vreg_ldo15, 3050);
346 if (rc) {
347 pr_err("%s: VREG L15 set failed\n", __func__);
348 goto l8_disable;
349 }
350
351 rc = vreg_enable(vreg_ldo15);
352 if (rc) {
353 pr_err("%s: VREG L15 enable failed\n", __func__);
354 goto l8_disable;
355 }
356
357 /* check this device active by reading first byte/register */
358 rc = i2c_smbus_read_byte_data(client, 0x01);
359 if (rc < 0) {
360 pr_err("%s: i2c sanity check failed\n", __func__);
361 goto l8_disable;
362 }
363
364 rc = gpio_tlmm_config(GPIO_CFG(CYTTSP_TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
365 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
366 if (rc) {
367 pr_err("%s: Could not configure gpio %d\n",
368 __func__, CYTTSP_TS_GPIO_IRQ);
369 goto l8_disable;
370 }
371
372 /* virtual keys */
373 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
374 properties_kobj = kobject_create_and_add("board_properties",
375 NULL);
376 if (properties_kobj)
377 rc = sysfs_create_group(properties_kobj,
378 &tma300_properties_attr_group);
379 if (!properties_kobj || rc)
380 pr_err("%s: failed to create board_properties\n",
381 __func__);
382
383 return CY_OK;
384
385l8_disable:
386 vreg_disable(vreg_ldo8);
387l8_put:
388 vreg_put(vreg_ldo8);
389 return rc;
390}
391
Anirudh Ghayalf9929b12011-09-07 15:57:36 +0530392/* TODO: Put the regulator to LPM / HPM in suspend/resume*/
393static int cyttsp_platform_suspend(struct i2c_client *client)
394{
395 msleep(20);
396
397 return CY_OK;
398}
399
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700400static int cyttsp_platform_resume(struct i2c_client *client)
401{
402 /* add any special code to strobe a wakeup pin or chip reset */
403 mdelay(10);
404
405 return CY_OK;
406}
407
408static struct cyttsp_platform_data cyttsp_data = {
409 .fw_fname = "cyttsp_7630_fluid.hex",
410 .panel_maxx = 479,
411 .panel_maxy = 799,
412 .disp_maxx = 469,
413 .disp_maxy = 799,
414 .disp_minx = 10,
415 .disp_miny = 0,
416 .flags = 0,
417 .gen = CY_GEN3, /* or */
418 .use_st = CY_USE_ST,
419 .use_mt = CY_USE_MT,
420 .use_hndshk = CY_SEND_HNDSHK,
421 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +0530422 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700423 .use_gestures = CY_USE_GESTURES,
424 /* activate up to 4 groups
425 * and set active distance
426 */
427 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
428 CY_GEST_GRP3 | CY_GEST_GRP4 |
429 CY_ACT_DIST,
430 /* change act_intrvl to customize the Active power state
431 * scanning/processing refresh interval for Operating mode
432 */
433 .act_intrvl = CY_ACT_INTRVL_DFLT,
434 /* change tch_tmout to customize the touch timeout for the
435 * Active power state for Operating mode
436 */
437 .tch_tmout = CY_TCH_TMOUT_DFLT,
438 /* change lp_intrvl to customize the Low Power power state
439 * scanning/processing refresh interval for Operating mode
440 */
441 .lp_intrvl = CY_LP_INTRVL_DFLT,
442 .resume = cyttsp_platform_resume,
Anirudh Ghayalf9929b12011-09-07 15:57:36 +0530443 .suspend = cyttsp_platform_suspend,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700444 .init = cyttsp_platform_init,
445 .sleep_gpio = -1,
446 .resout_gpio = -1,
447 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
Mohan Pallaka49c37d62011-08-01 11:52:00 +0530448 .correct_fw_ver = 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700449};
450
451static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
452{
453 struct pm8058_gpio pwm_gpio_config = {
454 .direction = PM_GPIO_DIR_OUT,
455 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
456 .output_value = 0,
457 .pull = PM_GPIO_PULL_NO,
458 .vin_sel = PM_GPIO_VIN_S3,
459 .out_strength = PM_GPIO_STRENGTH_HIGH,
460 .function = PM_GPIO_FUNC_2,
461 };
462 int rc = -EINVAL;
463 int id, mode, max_mA;
464
465 id = mode = max_mA = 0;
466 switch (ch) {
467 case 0:
468 case 1:
469 case 2:
470 if (on) {
471 id = 24 + ch;
472 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
473 if (rc)
474 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
475 __func__, id, rc);
476 }
477 break;
478
479 case 3:
480 id = PM_PWM_LED_KPD;
481 mode = PM_PWM_CONF_DTEST3;
482 max_mA = 200;
483 break;
484
485 case 4:
486 id = PM_PWM_LED_0;
487 mode = PM_PWM_CONF_PWM1;
488 max_mA = 40;
489 break;
490
491 case 5:
492 id = PM_PWM_LED_2;
493 mode = PM_PWM_CONF_PWM2;
494 max_mA = 40;
495 break;
496
497 case 6:
498 id = PM_PWM_LED_FLASH;
499 mode = PM_PWM_CONF_DTEST3;
500 max_mA = 200;
501 break;
502
503 default:
504 break;
505 }
506
507 if (ch >= 3 && ch <= 6) {
508 if (!on) {
509 mode = PM_PWM_CONF_NONE;
510 max_mA = 0;
511 }
512 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
513 if (rc)
514 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
515 __func__, ch, rc);
516 }
517
518 return rc;
519}
520
521static int pm8058_pwm_enable(struct pwm_device *pwm, int ch, int on)
522{
523 int rc;
524
525 switch (ch) {
526 case 7:
527 rc = pm8058_pwm_set_dtest(pwm, on);
528 if (rc)
529 pr_err("%s: pwm_set_dtest(%d): rc=%d\n",
530 __func__, on, rc);
531 break;
532 default:
533 rc = -EINVAL;
534 break;
535 }
536 return rc;
537}
538
539static const unsigned int fluid_keymap[] = {
540 KEY(0, 0, KEY_7),
541 KEY(0, 1, KEY_ENTER),
542 KEY(0, 2, KEY_UP),
543 /* drop (0,3) as it always shows up in pair with(0,2) */
544 KEY(0, 4, KEY_DOWN),
545
546 KEY(1, 0, KEY_CAMERA_SNAPSHOT),
547 KEY(1, 1, KEY_SELECT),
548 KEY(1, 2, KEY_1),
549 KEY(1, 3, KEY_VOLUMEUP),
550 KEY(1, 4, KEY_VOLUMEDOWN),
551};
552
553static const unsigned int surf_keymap[] = {
554 KEY(0, 0, KEY_7),
555 KEY(0, 1, KEY_DOWN),
556 KEY(0, 2, KEY_UP),
557 KEY(0, 3, KEY_RIGHT),
558 KEY(0, 4, KEY_ENTER),
559 KEY(0, 5, KEY_L),
560 KEY(0, 6, KEY_BACK),
561 KEY(0, 7, KEY_M),
562
563 KEY(1, 0, KEY_LEFT),
564 KEY(1, 1, KEY_SEND),
565 KEY(1, 2, KEY_1),
566 KEY(1, 3, KEY_4),
567 KEY(1, 4, KEY_CLEAR),
568 KEY(1, 5, KEY_MSDOS),
569 KEY(1, 6, KEY_SPACE),
570 KEY(1, 7, KEY_COMMA),
571
572 KEY(2, 0, KEY_6),
573 KEY(2, 1, KEY_5),
574 KEY(2, 2, KEY_8),
575 KEY(2, 3, KEY_3),
576 KEY(2, 4, KEY_NUMERIC_STAR),
577 KEY(2, 5, KEY_UP),
578 KEY(2, 6, KEY_DOWN), /* SYN */
579 KEY(2, 7, KEY_LEFTSHIFT),
580
581 KEY(3, 0, KEY_9),
582 KEY(3, 1, KEY_NUMERIC_POUND),
583 KEY(3, 2, KEY_0),
584 KEY(3, 3, KEY_2),
585 KEY(3, 4, KEY_SLEEP),
586 KEY(3, 5, KEY_F1),
587 KEY(3, 6, KEY_F2),
588 KEY(3, 7, KEY_F3),
589
590 KEY(4, 0, KEY_BACK),
591 KEY(4, 1, KEY_HOME),
592 KEY(4, 2, KEY_MENU),
593 KEY(4, 3, KEY_VOLUMEUP),
594 KEY(4, 4, KEY_VOLUMEDOWN),
595 KEY(4, 5, KEY_F4),
596 KEY(4, 6, KEY_F5),
597 KEY(4, 7, KEY_F6),
598
599 KEY(5, 0, KEY_R),
600 KEY(5, 1, KEY_T),
601 KEY(5, 2, KEY_Y),
602 KEY(5, 3, KEY_LEFTALT),
603 KEY(5, 4, KEY_KPENTER),
604 KEY(5, 5, KEY_Q),
605 KEY(5, 6, KEY_W),
606 KEY(5, 7, KEY_E),
607
608 KEY(6, 0, KEY_F),
609 KEY(6, 1, KEY_G),
610 KEY(6, 2, KEY_H),
611 KEY(6, 3, KEY_CAPSLOCK),
612 KEY(6, 4, KEY_PAGEUP),
613 KEY(6, 5, KEY_A),
614 KEY(6, 6, KEY_S),
615 KEY(6, 7, KEY_D),
616
617 KEY(7, 0, KEY_V),
618 KEY(7, 1, KEY_B),
619 KEY(7, 2, KEY_N),
620 KEY(7, 3, KEY_MENU), /* REVISIT - SYM */
621 KEY(7, 4, KEY_PAGEDOWN),
622 KEY(7, 5, KEY_Z),
623 KEY(7, 6, KEY_X),
624 KEY(7, 7, KEY_C),
625
626 KEY(8, 0, KEY_P),
627 KEY(8, 1, KEY_J),
628 KEY(8, 2, KEY_K),
629 KEY(8, 3, KEY_INSERT),
630 KEY(8, 4, KEY_LINEFEED),
631 KEY(8, 5, KEY_U),
632 KEY(8, 6, KEY_I),
633 KEY(8, 7, KEY_O),
634
635 KEY(9, 0, KEY_4),
636 KEY(9, 1, KEY_5),
637 KEY(9, 2, KEY_6),
638 KEY(9, 3, KEY_7),
639 KEY(9, 4, KEY_8),
640 KEY(9, 5, KEY_1),
641 KEY(9, 6, KEY_2),
642 KEY(9, 7, KEY_3),
643
644 KEY(10, 0, KEY_F7),
645 KEY(10, 1, KEY_F8),
646 KEY(10, 2, KEY_F9),
647 KEY(10, 3, KEY_F10),
648 KEY(10, 4, KEY_FN),
649 KEY(10, 5, KEY_9),
650 KEY(10, 6, KEY_0),
651 KEY(10, 7, KEY_DOT),
652
653 KEY(11, 0, KEY_LEFTCTRL),
654 KEY(11, 1, KEY_F11), /* START */
655 KEY(11, 2, KEY_ENTER),
656 KEY(11, 3, KEY_SEARCH),
657 KEY(11, 4, KEY_DELETE),
658 KEY(11, 5, KEY_RIGHT),
659 KEY(11, 6, KEY_LEFT),
660 KEY(11, 7, KEY_RIGHTSHIFT),
661};
662
663static struct resource resources_keypad[] = {
664 {
665 .start = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
666 .end = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
667 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800668 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700669 {
670 .start = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
671 .end = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
672 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800673 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700674};
675
676static struct matrix_keymap_data surf_keymap_data = {
677 .keymap_size = ARRAY_SIZE(surf_keymap),
678 .keymap = surf_keymap,
679};
680
681
682static struct pmic8058_keypad_data surf_keypad_data = {
683 .input_name = "surf_keypad",
684 .input_phys_device = "surf_keypad/input0",
685 .num_rows = 12,
686 .num_cols = 8,
687 .rows_gpio_start = 8,
688 .cols_gpio_start = 0,
689 .debounce_ms = {8, 10},
690 .scan_delay_ms = 32,
691 .row_hold_ns = 91500,
692 .wakeup = 1,
693 .keymap_data = &surf_keymap_data,
694};
695
696static struct matrix_keymap_data fluid_keymap_data = {
697 .keymap_size = ARRAY_SIZE(fluid_keymap),
698 .keymap = fluid_keymap,
699};
700
701
702
703static struct pmic8058_keypad_data fluid_keypad_data = {
704 .input_name = "fluid-keypad",
705 .input_phys_device = "fluid-keypad/input0",
706 .num_rows = 5,
707 .num_cols = 5,
708 .rows_gpio_start = 8,
709 .cols_gpio_start = 0,
710 .debounce_ms = {8, 10},
711 .scan_delay_ms = 32,
712 .row_hold_ns = 91500,
713 .wakeup = 1,
714 .keymap_data = &fluid_keymap_data,
715};
716
717static struct pm8058_pwm_pdata pm8058_pwm_data = {
718 .config = pm8058_pwm_config,
719 .enable = pm8058_pwm_enable,
720};
721
722/* Put sub devices with fixed location first in sub_devices array */
723#define PM8058_SUBDEV_KPD 0
724#define PM8058_SUBDEV_LED 1
725
726static struct pm8058_gpio_platform_data pm8058_gpio_data = {
727 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
728 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
729 .init = pm8058_gpios_init,
730};
731
732static struct pm8058_gpio_platform_data pm8058_mpp_data = {
733 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
734 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
735};
736
737static struct pmic8058_led pmic8058_ffa_leds[] = {
738 [0] = {
739 .name = "keyboard-backlight",
740 .max_brightness = 15,
741 .id = PMIC8058_ID_LED_KB_LIGHT,
Dima Zavinba5499e2011-01-10 11:00:30 -0800742 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700743};
744
745static struct pmic8058_leds_platform_data pm8058_ffa_leds_data = {
746 .num_leds = ARRAY_SIZE(pmic8058_ffa_leds),
747 .leds = pmic8058_ffa_leds,
748};
749
750static struct pmic8058_led pmic8058_surf_leds[] = {
751 [0] = {
752 .name = "keyboard-backlight",
753 .max_brightness = 15,
754 .id = PMIC8058_ID_LED_KB_LIGHT,
755 },
756 [1] = {
757 .name = "voice:red",
758 .max_brightness = 20,
759 .id = PMIC8058_ID_LED_0,
760 },
761 [2] = {
762 .name = "wlan:green",
763 .max_brightness = 20,
764 .id = PMIC8058_ID_LED_2,
765 },
766};
767
768static struct mfd_cell pm8058_subdevs[] = {
769 { .name = "pm8058-keypad",
770 .id = -1,
771 .num_resources = ARRAY_SIZE(resources_keypad),
772 .resources = resources_keypad,
773 },
774 { .name = "pm8058-led",
775 .id = -1,
776 },
777 { .name = "pm8058-gpio",
778 .id = -1,
779 .platform_data = &pm8058_gpio_data,
780 .pdata_size = sizeof(pm8058_gpio_data),
781 },
782 { .name = "pm8058-mpp",
783 .id = -1,
784 .platform_data = &pm8058_mpp_data,
785 .pdata_size = sizeof(pm8058_mpp_data),
786 },
787 { .name = "pm8058-pwm",
788 .id = -1,
789 .platform_data = &pm8058_pwm_data,
790 .pdata_size = sizeof(pm8058_pwm_data),
791 },
792 { .name = "pm8058-nfc",
793 .id = -1,
794 },
795 { .name = "pm8058-upl",
796 .id = -1,
797 },
798};
799
800static struct pmic8058_leds_platform_data pm8058_surf_leds_data = {
801 .num_leds = ARRAY_SIZE(pmic8058_surf_leds),
802 .leds = pmic8058_surf_leds,
803};
804
805static struct pmic8058_led pmic8058_fluid_leds[] = {
806 [0] = {
807 .name = "keyboard-backlight",
808 .max_brightness = 15,
809 .id = PMIC8058_ID_LED_KB_LIGHT,
810 },
811 [1] = {
812 .name = "flash:led_0",
813 .max_brightness = 15,
814 .id = PMIC8058_ID_FLASH_LED_0,
815 },
816 [2] = {
817 .name = "flash:led_1",
818 .max_brightness = 15,
819 .id = PMIC8058_ID_FLASH_LED_1,
820 },
821};
822
823static struct pmic8058_leds_platform_data pm8058_fluid_leds_data = {
824 .num_leds = ARRAY_SIZE(pmic8058_fluid_leds),
825 .leds = pmic8058_fluid_leds,
826};
827
828static struct pm8058_platform_data pm8058_7x30_data = {
829 .irq_base = PMIC8058_IRQ_BASE,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +0530830 .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700831
832 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
833 .sub_devices = pm8058_subdevs,
834 .irq_trigger_flags = IRQF_TRIGGER_LOW,
835};
836
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +0530837#ifdef CONFIG_MSM_SSBI
838static struct msm_ssbi_platform_data msm7x30_ssbi_pm8058_pdata = {
839 .controller_type = MSM_SBI_CTRL_SSBI2,
840 .slave = {
841 .name = "pm8058-core",
842 .platform_data = &pm8058_7x30_data,
843 },
844};
845#endif
846
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700847static struct i2c_board_info cy8info[] __initdata = {
848 {
849 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
850 .platform_data = &cyttsp_data,
851#ifndef CY_USE_TIMER
852 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
853#endif /* CY_USE_TIMER */
854 },
855};
856
857static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
858#ifdef CONFIG_MT9D112
859 {
860 I2C_BOARD_INFO("mt9d112", 0x78 >> 1),
Dima Zavinba5499e2011-01-10 11:00:30 -0800861 },
862#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700863#ifdef CONFIG_WEBCAM_OV9726
864 {
865 I2C_BOARD_INFO("ov9726", 0x10),
866 },
867#endif
868#ifdef CONFIG_S5K3E2FX
869 {
870 I2C_BOARD_INFO("s5k3e2fx", 0x20 >> 1),
871 },
872#endif
873#ifdef CONFIG_MT9P012
874 {
875 I2C_BOARD_INFO("mt9p012", 0x6C >> 1),
876 },
877#endif
878#ifdef CONFIG_VX6953
879 {
880 I2C_BOARD_INFO("vx6953", 0x20),
881 },
882#endif
883#ifdef CONFIG_MT9E013
884 {
885 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
886 },
887#endif
888#ifdef CONFIG_SN12M0PZ
889 {
890 I2C_BOARD_INFO("sn12m0pz", 0x34 >> 1),
891 },
892#endif
893#if defined(CONFIG_MT9T013) || defined(CONFIG_SENSORS_MT9T013)
894 {
895 I2C_BOARD_INFO("mt9t013", 0x6C),
896 },
897#endif
898
Dima Zavinba5499e2011-01-10 11:00:30 -0800899};
900
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700901#ifdef CONFIG_MSM_CAMERA
902#define CAM_STNDBY 143
903static uint32_t camera_off_vcm_gpio_table[] = {
904GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VCM */
905};
906
907static uint32_t camera_off_gpio_table[] = {
908 /* parallel CAMERA interfaces */
909 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
910 GPIO_CFG(2, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
911 GPIO_CFG(3, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
912 GPIO_CFG(4, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
913 GPIO_CFG(5, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
914 GPIO_CFG(6, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
915 GPIO_CFG(7, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
916 GPIO_CFG(8, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
917 GPIO_CFG(9, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
918 GPIO_CFG(10, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
919 GPIO_CFG(11, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
920 GPIO_CFG(12, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
921 GPIO_CFG(13, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
922 GPIO_CFG(14, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
923 GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
924};
925
926static uint32_t camera_on_vcm_gpio_table[] = {
927GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), /* VCM */
928};
929
930static uint32_t camera_on_gpio_table[] = {
931 /* parallel CAMERA interfaces */
932 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
933 GPIO_CFG(2, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
934 GPIO_CFG(3, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
935 GPIO_CFG(4, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
936 GPIO_CFG(5, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
937 GPIO_CFG(6, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
938 GPIO_CFG(7, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
939 GPIO_CFG(8, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
940 GPIO_CFG(9, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
941 GPIO_CFG(10, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
942 GPIO_CFG(11, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
943 GPIO_CFG(12, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
944 GPIO_CFG(13, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
945 GPIO_CFG(14, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
946 GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
947};
948
949static uint32_t camera_off_gpio_fluid_table[] = {
950 /* FLUID: CAM_VGA_RST_N */
951 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
952 /* FLUID: CAMIF_STANDBY */
953 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
954};
955
956static uint32_t camera_on_gpio_fluid_table[] = {
957 /* FLUID: CAM_VGA_RST_N */
958 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
959 /* FLUID: CAMIF_STANDBY */
960 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
961};
962
963static void config_gpio_table(uint32_t *table, int len)
964{
965 int n, rc;
966 for (n = 0; n < len; n++) {
967 rc = gpio_tlmm_config(table[n], GPIO_CFG_ENABLE);
968 if (rc) {
969 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
970 __func__, table[n], rc);
971 break;
972 }
973 }
974}
975static int config_camera_on_gpios(void)
976{
977 config_gpio_table(camera_on_gpio_table,
978 ARRAY_SIZE(camera_on_gpio_table));
979
980 if (adie_get_detected_codec_type() != TIMPANI_ID)
981 /* GPIO1 is shared also used in Timpani RF card so
982 only configure it for non-Timpani RF card */
983 config_gpio_table(camera_on_vcm_gpio_table,
984 ARRAY_SIZE(camera_on_vcm_gpio_table));
985
986 if (machine_is_msm7x30_fluid()) {
987 config_gpio_table(camera_on_gpio_fluid_table,
988 ARRAY_SIZE(camera_on_gpio_fluid_table));
989 /* FLUID: turn on 5V booster */
990 gpio_set_value(
991 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 1);
992 /* FLUID: drive high to put secondary sensor to STANDBY */
993 gpio_set_value(CAM_STNDBY, 1);
994 }
995 return 0;
996}
997
998static void config_camera_off_gpios(void)
999{
1000 config_gpio_table(camera_off_gpio_table,
1001 ARRAY_SIZE(camera_off_gpio_table));
1002
1003 if (adie_get_detected_codec_type() != TIMPANI_ID)
1004 /* GPIO1 is shared also used in Timpani RF card so
1005 only configure it for non-Timpani RF card */
1006 config_gpio_table(camera_off_vcm_gpio_table,
1007 ARRAY_SIZE(camera_off_vcm_gpio_table));
1008
1009 if (machine_is_msm7x30_fluid()) {
1010 config_gpio_table(camera_off_gpio_fluid_table,
1011 ARRAY_SIZE(camera_off_gpio_fluid_table));
1012 /* FLUID: turn off 5V booster */
1013 gpio_set_value(
1014 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 0);
1015 }
1016}
1017
1018struct resource msm_camera_resources[] = {
1019 {
1020 .start = 0xA6000000,
1021 .end = 0xA6000000 + SZ_1M - 1,
1022 .flags = IORESOURCE_MEM,
1023 },
1024 {
1025 .start = INT_VFE,
1026 .end = INT_VFE,
1027 .flags = IORESOURCE_IRQ,
1028 },
1029 {
1030 .flags = IORESOURCE_DMA,
1031 }
1032};
1033
1034struct msm_camera_device_platform_data msm_camera_device_data = {
1035 .camera_gpio_on = config_camera_on_gpios,
1036 .camera_gpio_off = config_camera_off_gpios,
1037 .ioext.camifpadphy = 0xAB000000,
1038 .ioext.camifpadsz = 0x00000400,
1039 .ioext.csiphy = 0xA6100000,
1040 .ioext.csisz = 0x00000400,
1041 .ioext.csiirq = INT_CSI,
1042 .ioclk.mclk_clk_rate = 24000000,
1043 .ioclk.vfe_clk_rate = 147456000,
1044};
1045
1046static struct msm_camera_sensor_flash_src msm_flash_src_pwm = {
1047 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PWM,
1048 ._fsrc.pwm_src.freq = 1000,
1049 ._fsrc.pwm_src.max_load = 300,
1050 ._fsrc.pwm_src.low_load = 30,
1051 ._fsrc.pwm_src.high_load = 100,
1052 ._fsrc.pwm_src.channel = 7,
1053};
1054
1055#ifdef CONFIG_MT9D112
1056static struct msm_camera_sensor_flash_data flash_mt9d112 = {
1057 .flash_type = MSM_CAMERA_FLASH_LED,
1058 .flash_src = &msm_flash_src_pwm
1059};
1060
1061static struct msm_camera_sensor_info msm_camera_sensor_mt9d112_data = {
1062 .sensor_name = "mt9d112",
1063 .sensor_reset = 0,
1064 .sensor_pwd = 85,
1065 .vcm_pwd = 1,
1066 .vcm_enable = 0,
1067 .pdata = &msm_camera_device_data,
1068 .resource = msm_camera_resources,
1069 .num_resources = ARRAY_SIZE(msm_camera_resources),
1070 .flash_data = &flash_mt9d112,
1071 .csi_if = 0
1072};
1073
1074static struct platform_device msm_camera_sensor_mt9d112 = {
1075 .name = "msm_camera_mt9d112",
1076 .dev = {
1077 .platform_data = &msm_camera_sensor_mt9d112_data,
1078 },
1079};
1080#endif
1081
1082#ifdef CONFIG_WEBCAM_OV9726
1083
1084static struct msm_camera_sensor_platform_info ov9726_sensor_7630_info = {
1085 .mount_angle = 90
1086};
1087
1088static struct msm_camera_sensor_flash_data flash_ov9726 = {
1089 .flash_type = MSM_CAMERA_FLASH_LED,
1090 .flash_src = &msm_flash_src_pwm
1091};
1092static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
1093 .sensor_name = "ov9726",
1094 .sensor_reset = 0,
1095 .sensor_pwd = 85,
1096 .vcm_pwd = 1,
1097 .vcm_enable = 0,
1098 .pdata = &msm_camera_device_data,
1099 .resource = msm_camera_resources,
1100 .num_resources = ARRAY_SIZE(msm_camera_resources),
1101 .flash_data = &flash_ov9726,
1102 .sensor_platform_info = &ov9726_sensor_7630_info,
1103 .csi_if = 1
1104};
1105struct platform_device msm_camera_sensor_ov9726 = {
1106 .name = "msm_camera_ov9726",
1107 .dev = {
1108 .platform_data = &msm_camera_sensor_ov9726_data,
1109 },
1110};
1111#endif
1112
1113#ifdef CONFIG_S5K3E2FX
1114static struct msm_camera_sensor_flash_data flash_s5k3e2fx = {
1115 .flash_type = MSM_CAMERA_FLASH_LED,
1116 .flash_src = &msm_flash_src_pwm,
1117};
1118
1119static struct msm_camera_sensor_info msm_camera_sensor_s5k3e2fx_data = {
1120 .sensor_name = "s5k3e2fx",
1121 .sensor_reset = 0,
1122 .sensor_pwd = 85,
1123 .vcm_pwd = 1,
1124 .vcm_enable = 0,
1125 .pdata = &msm_camera_device_data,
1126 .resource = msm_camera_resources,
1127 .num_resources = ARRAY_SIZE(msm_camera_resources),
1128 .flash_data = &flash_s5k3e2fx,
1129 .csi_if = 0
1130};
1131
1132static struct platform_device msm_camera_sensor_s5k3e2fx = {
1133 .name = "msm_camera_s5k3e2fx",
1134 .dev = {
1135 .platform_data = &msm_camera_sensor_s5k3e2fx_data,
1136 },
1137};
1138#endif
1139
1140#ifdef CONFIG_MT9P012
1141static struct msm_camera_sensor_flash_data flash_mt9p012 = {
1142 .flash_type = MSM_CAMERA_FLASH_LED,
1143 .flash_src = &msm_flash_src_pwm
1144};
1145
1146static struct msm_camera_sensor_info msm_camera_sensor_mt9p012_data = {
1147 .sensor_name = "mt9p012",
1148 .sensor_reset = 0,
1149 .sensor_pwd = 85,
1150 .vcm_pwd = 1,
1151 .vcm_enable = 1,
1152 .pdata = &msm_camera_device_data,
1153 .resource = msm_camera_resources,
1154 .num_resources = ARRAY_SIZE(msm_camera_resources),
1155 .flash_data = &flash_mt9p012,
1156 .csi_if = 0
1157};
1158
1159static struct platform_device msm_camera_sensor_mt9p012 = {
1160 .name = "msm_camera_mt9p012",
1161 .dev = {
1162 .platform_data = &msm_camera_sensor_mt9p012_data,
1163 },
1164};
1165#endif
1166
1167#ifdef CONFIG_MT9E013
1168static struct msm_camera_sensor_platform_info mt9e013_sensor_7630_info = {
1169 .mount_angle = 0
1170};
1171
1172static struct msm_camera_sensor_flash_data flash_mt9e013 = {
1173 .flash_type = MSM_CAMERA_FLASH_LED,
1174 .flash_src = &msm_flash_src_pwm
1175};
1176
1177static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
1178 .sensor_name = "mt9e013",
1179 .sensor_reset = 0,
1180 .sensor_pwd = 85,
1181 .vcm_pwd = 1,
1182 .vcm_enable = 1,
1183 .pdata = &msm_camera_device_data,
1184 .resource = msm_camera_resources,
1185 .num_resources = ARRAY_SIZE(msm_camera_resources),
1186 .flash_data = &flash_mt9e013,
1187 .sensor_platform_info = &mt9e013_sensor_7630_info,
1188 .csi_if = 1
1189};
1190
1191static struct platform_device msm_camera_sensor_mt9e013 = {
1192 .name = "msm_camera_mt9e013",
1193 .dev = {
1194 .platform_data = &msm_camera_sensor_mt9e013_data,
1195 },
1196};
1197#endif
1198
1199#ifdef CONFIG_VX6953
Jilai Wang971f97f2011-07-13 14:25:25 -04001200static struct msm_camera_sensor_platform_info vx6953_sensor_7630_info = {
1201 .mount_angle = 0
1202};
1203
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001204static struct msm_camera_sensor_flash_data flash_vx6953 = {
1205 .flash_type = MSM_CAMERA_FLASH_LED,
1206 .flash_src = &msm_flash_src_pwm
1207};
1208static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
1209 .sensor_name = "vx6953",
1210 .sensor_reset = 0,
1211 .sensor_pwd = 85,
1212 .vcm_pwd = 1,
1213 .vcm_enable = 0,
1214 .pdata = &msm_camera_device_data,
1215 .resource = msm_camera_resources,
1216 .num_resources = ARRAY_SIZE(msm_camera_resources),
Jilai Wang971f97f2011-07-13 14:25:25 -04001217 .sensor_platform_info = &vx6953_sensor_7630_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001218 .flash_data = &flash_vx6953,
1219 .csi_if = 1
1220};
1221static struct platform_device msm_camera_sensor_vx6953 = {
1222 .name = "msm_camera_vx6953",
1223 .dev = {
1224 .platform_data = &msm_camera_sensor_vx6953_data,
1225 },
1226};
1227#endif
1228
1229#ifdef CONFIG_SN12M0PZ
1230static struct msm_camera_sensor_flash_src msm_flash_src_current_driver = {
1231 .flash_sr_type = MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER,
1232 ._fsrc.current_driver_src.low_current = 210,
1233 ._fsrc.current_driver_src.high_current = 700,
1234 ._fsrc.current_driver_src.driver_channel = &pm8058_fluid_leds_data,
1235};
1236
1237static struct msm_camera_sensor_flash_data flash_sn12m0pz = {
1238 .flash_type = MSM_CAMERA_FLASH_LED,
1239 .flash_src = &msm_flash_src_current_driver
1240};
1241static struct msm_camera_sensor_info msm_camera_sensor_sn12m0pz_data = {
1242 .sensor_name = "sn12m0pz",
1243 .sensor_reset = 0,
1244 .sensor_pwd = 85,
1245 .vcm_pwd = 1,
1246 .vcm_enable = 1,
1247 .pdata = &msm_camera_device_data,
1248 .flash_data = &flash_sn12m0pz,
1249 .resource = msm_camera_resources,
1250 .num_resources = ARRAY_SIZE(msm_camera_resources),
1251 .csi_if = 0
1252};
1253
1254static struct platform_device msm_camera_sensor_sn12m0pz = {
1255 .name = "msm_camera_sn12m0pz",
1256 .dev = {
1257 .platform_data = &msm_camera_sensor_sn12m0pz_data,
1258 },
1259};
1260#endif
1261
1262#ifdef CONFIG_MT9T013
1263static struct msm_camera_sensor_flash_data flash_mt9t013 = {
1264 .flash_type = MSM_CAMERA_FLASH_LED,
1265 .flash_src = &msm_flash_src_pwm
1266};
1267
1268static struct msm_camera_sensor_info msm_camera_sensor_mt9t013_data = {
1269 .sensor_name = "mt9t013",
1270 .sensor_reset = 0,
1271 .sensor_pwd = 85,
1272 .vcm_pwd = 1,
1273 .vcm_enable = 0,
1274 .pdata = &msm_camera_device_data,
1275 .resource = msm_camera_resources,
1276 .num_resources = ARRAY_SIZE(msm_camera_resources),
1277 .flash_data = &flash_mt9t013,
1278 .csi_if = 1
1279};
1280
1281static struct platform_device msm_camera_sensor_mt9t013 = {
1282 .name = "msm_camera_mt9t013",
1283 .dev = {
1284 .platform_data = &msm_camera_sensor_mt9t013_data,
1285 },
1286};
1287#endif
1288
1289#ifdef CONFIG_MSM_GEMINI
1290static struct resource msm_gemini_resources[] = {
1291 {
1292 .start = 0xA3A00000,
1293 .end = 0xA3A00000 + 0x0150 - 1,
1294 .flags = IORESOURCE_MEM,
1295 },
1296 {
1297 .start = INT_JPEG,
1298 .end = INT_JPEG,
1299 .flags = IORESOURCE_IRQ,
1300 },
1301};
1302
1303static struct platform_device msm_gemini_device = {
1304 .name = "msm_gemini",
1305 .resource = msm_gemini_resources,
1306 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1307};
1308#endif
1309
1310#ifdef CONFIG_MSM_VPE
1311static struct resource msm_vpe_resources[] = {
1312 {
1313 .start = 0xAD200000,
1314 .end = 0xAD200000 + SZ_1M - 1,
1315 .flags = IORESOURCE_MEM,
1316 },
1317 {
1318 .start = INT_VPE,
1319 .end = INT_VPE,
1320 .flags = IORESOURCE_IRQ,
1321 },
1322};
1323
1324static struct platform_device msm_vpe_device = {
1325 .name = "msm_vpe",
1326 .id = 0,
1327 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1328 .resource = msm_vpe_resources,
1329};
1330#endif
1331
1332#endif /*CONFIG_MSM_CAMERA*/
1333
1334#ifdef CONFIG_MSM7KV2_AUDIO
1335static uint32_t audio_pamp_gpio_config =
1336 GPIO_CFG(82, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1337
1338static uint32_t audio_fluid_icodec_tx_config =
1339 GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1340
1341static int __init snddev_poweramp_gpio_init(void)
1342{
1343 int rc;
1344
1345 pr_info("snddev_poweramp_gpio_init \n");
1346 rc = gpio_tlmm_config(audio_pamp_gpio_config, GPIO_CFG_ENABLE);
1347 if (rc) {
1348 printk(KERN_ERR
1349 "%s: gpio_tlmm_config(%#x)=%d\n",
1350 __func__, audio_pamp_gpio_config, rc);
1351 }
1352 return rc;
1353}
1354
1355void msm_snddev_tx_route_config(void)
1356{
1357 int rc;
1358
1359 pr_debug("%s()\n", __func__);
1360
1361 if (machine_is_msm7x30_fluid()) {
1362 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1363 GPIO_CFG_ENABLE);
1364 if (rc) {
1365 printk(KERN_ERR
1366 "%s: gpio_tlmm_config(%#x)=%d\n",
1367 __func__, audio_fluid_icodec_tx_config, rc);
1368 } else
1369 gpio_set_value(85, 0);
1370 }
1371}
1372
1373void msm_snddev_tx_route_deconfig(void)
1374{
1375 int rc;
1376
1377 pr_debug("%s()\n", __func__);
1378
1379 if (machine_is_msm7x30_fluid()) {
1380 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1381 GPIO_CFG_DISABLE);
1382 if (rc) {
1383 printk(KERN_ERR
1384 "%s: gpio_tlmm_config(%#x)=%d\n",
1385 __func__, audio_fluid_icodec_tx_config, rc);
1386 }
1387 }
1388}
1389
1390void msm_snddev_poweramp_on(void)
1391{
1392 gpio_set_value(82, 1); /* enable spkr poweramp */
1393 pr_info("%s: power on amplifier\n", __func__);
1394}
1395
1396void msm_snddev_poweramp_off(void)
1397{
1398 gpio_set_value(82, 0); /* disable spkr poweramp */
1399 pr_info("%s: power off amplifier\n", __func__);
1400}
1401
1402static struct vreg *snddev_vreg_ncp, *snddev_vreg_gp4;
1403
1404void msm_snddev_hsed_voltage_on(void)
1405{
1406 int rc;
1407
1408 snddev_vreg_gp4 = vreg_get(NULL, "gp4");
1409 if (IS_ERR(snddev_vreg_gp4)) {
1410 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1411 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1412 return;
1413 }
1414 rc = vreg_enable(snddev_vreg_gp4);
1415 if (rc)
1416 pr_err("%s: vreg_enable(gp4) failed (%d)\n", __func__, rc);
1417
1418 snddev_vreg_ncp = vreg_get(NULL, "ncp");
1419 if (IS_ERR(snddev_vreg_ncp)) {
1420 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1421 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1422 return;
1423 }
1424 rc = vreg_enable(snddev_vreg_ncp);
1425 if (rc)
1426 pr_err("%s: vreg_enable(ncp) failed (%d)\n", __func__, rc);
1427}
1428
1429void msm_snddev_hsed_voltage_off(void)
1430{
1431 int rc;
1432
1433 if (IS_ERR(snddev_vreg_ncp)) {
1434 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1435 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1436 return;
1437 }
1438 rc = vreg_disable(snddev_vreg_ncp);
1439 if (rc)
1440 pr_err("%s: vreg_disable(ncp) failed (%d)\n", __func__, rc);
1441 vreg_put(snddev_vreg_ncp);
1442
1443 if (IS_ERR(snddev_vreg_gp4)) {
1444 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1445 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1446 return;
1447 }
1448 rc = vreg_disable(snddev_vreg_gp4);
1449 if (rc)
1450 pr_err("%s: vreg_disable(gp4) failed (%d)\n", __func__, rc);
1451
1452 vreg_put(snddev_vreg_gp4);
1453
1454}
1455
1456static unsigned aux_pcm_gpio_on[] = {
1457 GPIO_CFG(138, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DOUT */
1458 GPIO_CFG(139, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DIN */
1459 GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_SYNC */
1460 GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_CLK */
1461};
1462
1463static int __init aux_pcm_gpio_init(void)
1464{
1465 int pin, rc;
1466
1467 pr_info("aux_pcm_gpio_init \n");
1468 for (pin = 0; pin < ARRAY_SIZE(aux_pcm_gpio_on); pin++) {
1469 rc = gpio_tlmm_config(aux_pcm_gpio_on[pin],
1470 GPIO_CFG_ENABLE);
1471 if (rc) {
1472 printk(KERN_ERR
1473 "%s: gpio_tlmm_config(%#x)=%d\n",
1474 __func__, aux_pcm_gpio_on[pin], rc);
1475 }
1476 }
1477 return rc;
1478}
1479
1480static struct msm_gpio mi2s_clk_gpios[] = {
1481 { GPIO_CFG(145, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1482 "MI2S_SCLK"},
1483 { GPIO_CFG(144, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1484 "MI2S_WS"},
1485 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1486 "MI2S_MCLK_A"},
1487};
1488
1489static struct msm_gpio mi2s_rx_data_lines_gpios[] = {
1490 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1491 "MI2S_DATA_SD0_A"},
1492 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1493 "MI2S_DATA_SD1_A"},
1494 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1495 "MI2S_DATA_SD2_A"},
1496 { GPIO_CFG(146, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1497 "MI2S_DATA_SD3"},
1498};
1499
1500static struct msm_gpio mi2s_tx_data_lines_gpios[] = {
1501 { GPIO_CFG(146, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1502 "MI2S_DATA_SD3"},
1503};
1504
1505int mi2s_config_clk_gpio(void)
1506{
1507 int rc = 0;
1508
1509 rc = msm_gpios_request_enable(mi2s_clk_gpios,
1510 ARRAY_SIZE(mi2s_clk_gpios));
1511 if (rc) {
1512 pr_err("%s: enable mi2s clk gpios failed\n",
1513 __func__);
1514 return rc;
1515 }
1516 return 0;
1517}
1518
1519int mi2s_unconfig_data_gpio(u32 direction, u8 sd_line_mask)
1520{
1521 int i, rc = 0;
1522 sd_line_mask &= MI2S_SD_LINE_MASK;
1523
1524 switch (direction) {
1525 case DIR_TX:
1526 msm_gpios_disable_free(mi2s_tx_data_lines_gpios, 1);
1527 break;
1528 case DIR_RX:
1529 i = 0;
1530 while (sd_line_mask) {
1531 if (sd_line_mask & 0x1)
1532 msm_gpios_disable_free(
1533 mi2s_rx_data_lines_gpios + i , 1);
1534 sd_line_mask = sd_line_mask >> 1;
1535 i++;
1536 }
1537 break;
1538 default:
1539 pr_err("%s: Invaild direction direction = %u\n",
1540 __func__, direction);
1541 rc = -EINVAL;
1542 break;
1543 }
1544 return rc;
1545}
1546
1547int mi2s_config_data_gpio(u32 direction, u8 sd_line_mask)
1548{
1549 int i , rc = 0;
1550 u8 sd_config_done_mask = 0;
1551
1552 sd_line_mask &= MI2S_SD_LINE_MASK;
1553
1554 switch (direction) {
1555 case DIR_TX:
1556 if ((sd_line_mask & MI2S_SD_0) || (sd_line_mask & MI2S_SD_1) ||
1557 (sd_line_mask & MI2S_SD_2) || !(sd_line_mask & MI2S_SD_3)) {
1558 pr_err("%s: can not use SD0 or SD1 or SD2 for TX"
1559 ".only can use SD3. sd_line_mask = 0x%x\n",
1560 __func__ , sd_line_mask);
1561 rc = -EINVAL;
1562 } else {
1563 rc = msm_gpios_request_enable(mi2s_tx_data_lines_gpios,
1564 1);
1565 if (rc)
1566 pr_err("%s: enable mi2s gpios for TX failed\n",
1567 __func__);
1568 }
1569 break;
1570 case DIR_RX:
1571 i = 0;
1572 while (sd_line_mask && (rc == 0)) {
1573 if (sd_line_mask & 0x1) {
1574 rc = msm_gpios_request_enable(
1575 mi2s_rx_data_lines_gpios + i , 1);
1576 if (rc) {
1577 pr_err("%s: enable mi2s gpios for"
1578 "RX failed. SD line = %s\n",
1579 __func__,
1580 (mi2s_rx_data_lines_gpios + i)->label);
1581 mi2s_unconfig_data_gpio(DIR_RX,
1582 sd_config_done_mask);
1583 } else
1584 sd_config_done_mask |= (1 << i);
1585 }
1586 sd_line_mask = sd_line_mask >> 1;
1587 i++;
1588 }
1589 break;
1590 default:
1591 pr_err("%s: Invaild direction direction = %u\n",
1592 __func__, direction);
1593 rc = -EINVAL;
1594 break;
1595 }
1596 return rc;
1597}
1598
1599int mi2s_unconfig_clk_gpio(void)
1600{
1601 msm_gpios_disable_free(mi2s_clk_gpios, ARRAY_SIZE(mi2s_clk_gpios));
1602 return 0;
1603}
1604
1605#endif /* CONFIG_MSM7KV2_AUDIO */
1606
1607static int __init buses_init(void)
1608{
1609 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 1, GPIO_CFG_INPUT,
1610 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
1611 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
1612 __func__, PMIC_GPIO_INT);
1613
1614 if (machine_is_msm7x30_fluid()) {
1615 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1616 = &fluid_keypad_data;
1617 } else {
1618 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1619 = &surf_keypad_data;
1620 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
1621 = sizeof(surf_keypad_data);
1622 }
1623
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001624 return 0;
1625}
1626
1627#define TIMPANI_RESET_GPIO 1
1628
1629struct bahama_config_register{
1630 u8 reg;
1631 u8 value;
1632 u8 mask;
1633};
1634
1635enum version{
1636 VER_1_0,
1637 VER_2_0,
1638 VER_UNSUPPORTED = 0xFF
1639};
1640
1641
1642static struct vreg *vreg_marimba_1;
1643static struct vreg *vreg_marimba_2;
1644static struct vreg *vreg_marimba_3;
1645
1646static struct msm_gpio timpani_reset_gpio_cfg[] = {
1647{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
1648 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
1649
1650static u8 read_bahama_ver(void)
1651{
1652 int rc;
1653 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1654 u8 bahama_version;
1655
1656 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
1657 if (rc < 0) {
1658 printk(KERN_ERR
1659 "%s: version read failed: %d\n",
1660 __func__, rc);
1661 return rc;
1662 } else {
1663 printk(KERN_INFO
1664 "%s: version read got: 0x%x\n",
1665 __func__, bahama_version);
1666 }
1667
1668 switch (bahama_version) {
1669 case 0x08: /* varient of bahama v1 */
1670 case 0x10:
1671 case 0x00:
1672 return VER_1_0;
1673 case 0x09: /* variant of bahama v2 */
1674 return VER_2_0;
1675 default:
1676 return VER_UNSUPPORTED;
1677 }
1678}
1679
1680static int config_timpani_reset(void)
1681{
1682 int rc;
1683
1684 rc = msm_gpios_request_enable(timpani_reset_gpio_cfg,
1685 ARRAY_SIZE(timpani_reset_gpio_cfg));
1686 if (rc < 0) {
1687 printk(KERN_ERR
1688 "%s: msm_gpios_request_enable failed (%d)\n",
1689 __func__, rc);
1690 }
1691 return rc;
1692}
1693
1694static unsigned int msm_timpani_setup_power(void)
1695{
1696 int rc;
1697
1698 rc = config_timpani_reset();
1699 if (rc < 0)
1700 goto out;
1701
1702 rc = vreg_enable(vreg_marimba_1);
1703 if (rc) {
1704 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1705 __func__, rc);
1706 goto out;
1707 }
1708 rc = vreg_enable(vreg_marimba_2);
1709 if (rc) {
1710 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1711 __func__, rc);
1712 goto fail_disable_vreg_marimba_1;
1713 }
1714
1715 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 1);
1716 if (rc < 0) {
1717 printk(KERN_ERR
1718 "%s: gpio_direction_output failed (%d)\n",
1719 __func__, rc);
1720 msm_gpios_free(timpani_reset_gpio_cfg,
1721 ARRAY_SIZE(timpani_reset_gpio_cfg));
1722 vreg_disable(vreg_marimba_2);
1723 } else
1724 goto out;
1725
1726
1727fail_disable_vreg_marimba_1:
1728 vreg_disable(vreg_marimba_1);
1729
1730out:
1731 return rc;
1732};
1733
1734static void msm_timpani_shutdown_power(void)
1735{
1736 int rc;
1737
1738 rc = vreg_disable(vreg_marimba_1);
1739 if (rc) {
1740 printk(KERN_ERR "%s: return val: %d\n",
1741 __func__, rc);
1742 }
1743 rc = vreg_disable(vreg_marimba_2);
1744 if (rc) {
1745 printk(KERN_ERR "%s: return val: %d\n",
1746 __func__, rc);
1747 }
1748
1749 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 0);
1750 if (rc < 0) {
1751 printk(KERN_ERR
1752 "%s: gpio_direction_output failed (%d)\n",
1753 __func__, rc);
1754 }
1755
1756 msm_gpios_free(timpani_reset_gpio_cfg,
1757 ARRAY_SIZE(timpani_reset_gpio_cfg));
1758};
1759
1760static unsigned int msm_bahama_core_config(int type)
1761{
1762 int rc = 0;
1763
1764 if (type == BAHAMA_ID) {
1765
1766 int i;
1767 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1768
1769 const struct bahama_config_register v20_init[] = {
1770 /* reg, value, mask */
1771 { 0xF4, 0x84, 0xFF }, /* AREG */
1772 { 0xF0, 0x04, 0xFF } /* DREG */
1773 };
1774
1775 if (read_bahama_ver() == VER_2_0) {
1776 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
1777 u8 value = v20_init[i].value;
1778 rc = marimba_write_bit_mask(&config,
1779 v20_init[i].reg,
1780 &value,
1781 sizeof(v20_init[i].value),
1782 v20_init[i].mask);
1783 if (rc < 0) {
1784 printk(KERN_ERR
1785 "%s: reg %d write failed: %d\n",
1786 __func__, v20_init[i].reg, rc);
1787 return rc;
1788 }
1789 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
1790 " mask 0x%02x\n",
1791 __func__, v20_init[i].reg,
1792 v20_init[i].value, v20_init[i].mask);
1793 }
1794 }
1795 }
1796 printk(KERN_INFO "core type: %d\n", type);
1797
1798 return rc;
1799}
1800
1801static unsigned int msm_bahama_setup_power(void)
1802{
1803 int rc;
1804
1805 rc = vreg_enable(vreg_marimba_3);
1806 if (rc) {
1807 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1808 __func__, rc);
1809 }
1810
1811 return rc;
1812};
1813
1814static unsigned int msm_bahama_shutdown_power(int value)
1815{
1816 int rc = 0;
1817
1818 if (value != BAHAMA_ID) {
1819 rc = vreg_disable(vreg_marimba_3);
1820 if (rc) {
1821 printk(KERN_ERR "%s: return val: %d\n",
1822 __func__, rc);
1823 }
1824 }
1825
1826 return rc;
1827};
1828
1829static struct msm_gpio marimba_svlte_config_clock[] = {
1830 { GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1831 "MARIMBA_SVLTE_CLOCK_ENABLE" },
1832};
1833
1834static unsigned int msm_marimba_gpio_config_svlte(int gpio_cfg_marimba)
1835{
1836 if (machine_is_msm8x55_svlte_surf() ||
1837 machine_is_msm8x55_svlte_ffa()) {
1838 if (gpio_cfg_marimba)
1839 gpio_set_value(GPIO_PIN
1840 (marimba_svlte_config_clock->gpio_cfg), 1);
1841 else
1842 gpio_set_value(GPIO_PIN
1843 (marimba_svlte_config_clock->gpio_cfg), 0);
1844 }
1845
1846 return 0;
1847};
1848
1849static unsigned int msm_marimba_setup_power(void)
1850{
1851 int rc;
1852
1853 rc = vreg_enable(vreg_marimba_1);
1854 if (rc) {
1855 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1856 __func__, rc);
1857 goto out;
1858 }
1859 rc = vreg_enable(vreg_marimba_2);
1860 if (rc) {
1861 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1862 __func__, rc);
1863 goto out;
1864 }
1865
1866 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
1867 rc = msm_gpios_request_enable(marimba_svlte_config_clock,
1868 ARRAY_SIZE(marimba_svlte_config_clock));
1869 if (rc < 0) {
1870 printk(KERN_ERR
1871 "%s: msm_gpios_request_enable failed (%d)\n",
1872 __func__, rc);
1873 return rc;
1874 }
1875
1876 rc = gpio_direction_output(GPIO_PIN
1877 (marimba_svlte_config_clock->gpio_cfg), 0);
1878 if (rc < 0) {
1879 printk(KERN_ERR
1880 "%s: gpio_direction_output failed (%d)\n",
1881 __func__, rc);
1882 return rc;
1883 }
1884 }
1885
1886out:
1887 return rc;
1888};
1889
1890static void msm_marimba_shutdown_power(void)
1891{
1892 int rc;
1893
1894 rc = vreg_disable(vreg_marimba_1);
1895 if (rc) {
1896 printk(KERN_ERR "%s: return val: %d\n",
1897 __func__, rc);
1898 }
1899 rc = vreg_disable(vreg_marimba_2);
1900 if (rc) {
1901 printk(KERN_ERR "%s: return val: %d \n",
1902 __func__, rc);
1903 }
1904};
1905
1906static int bahama_present(void)
1907{
1908 int id;
1909 switch (id = adie_get_detected_connectivity_type()) {
1910 case BAHAMA_ID:
1911 return 1;
1912
1913 case MARIMBA_ID:
1914 return 0;
1915
1916 case TIMPANI_ID:
1917 default:
1918 printk(KERN_ERR "%s: unexpected adie connectivity type: %d\n",
1919 __func__, id);
1920 return -ENODEV;
1921 }
1922}
1923
1924struct vreg *fm_regulator;
1925static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
1926{
1927 int rc;
1928 uint32_t irqcfg;
1929 const char *id = "FMPW";
1930
1931 int bahama_not_marimba = bahama_present();
1932
1933 if (bahama_not_marimba == -1) {
1934 printk(KERN_WARNING "%s: bahama_present: %d\n",
1935 __func__, bahama_not_marimba);
1936 return -ENODEV;
1937 }
1938 if (bahama_not_marimba)
1939 fm_regulator = vreg_get(NULL, "s3");
1940 else
1941 fm_regulator = vreg_get(NULL, "s2");
1942
1943 if (IS_ERR(fm_regulator)) {
1944 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
1945 __func__, PTR_ERR(fm_regulator));
1946 return -1;
1947 }
1948 if (!bahama_not_marimba) {
1949
1950 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
1951
1952 if (rc < 0) {
1953 printk(KERN_ERR "%s: voltage level vote failed (%d)\n",
1954 __func__, rc);
1955 return rc;
1956 }
1957 }
1958 rc = vreg_enable(fm_regulator);
1959 if (rc) {
1960 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1961 __func__, rc);
1962 return rc;
1963 }
1964
1965 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1966 PMAPP_CLOCK_VOTE_ON);
1967 if (rc < 0) {
1968 printk(KERN_ERR "%s: clock vote failed (%d)\n",
1969 __func__, rc);
1970 goto fm_clock_vote_fail;
1971 }
1972 /*Request the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
1973 of svlte*/
1974 if (machine_is_msm8x55_svlte_surf() ||
1975 machine_is_msm8x55_svlte_ffa()) {
1976 rc = marimba_gpio_config(1);
1977 if (rc < 0)
1978 printk(KERN_ERR "%s: clock enable for svlte : %d\n",
1979 __func__, rc);
1980 }
1981 irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL,
1982 GPIO_CFG_2MA);
1983 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1984 if (rc) {
1985 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
1986 __func__, irqcfg, rc);
1987 rc = -EIO;
1988 goto fm_gpio_config_fail;
1989
1990 }
1991 return 0;
1992fm_gpio_config_fail:
1993 pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1994 PMAPP_CLOCK_VOTE_OFF);
1995fm_clock_vote_fail:
1996 vreg_disable(fm_regulator);
1997 return rc;
1998
1999};
2000
2001static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
2002{
2003 int rc;
2004 const char *id = "FMPW";
2005 uint32_t irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
2006 GPIO_CFG_2MA);
2007
2008 int bahama_not_marimba = bahama_present();
2009 if (bahama_not_marimba == -1) {
2010 printk(KERN_WARNING "%s: bahama_present: %d\n",
2011 __func__, bahama_not_marimba);
2012 return;
2013 }
2014
2015 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
2016 if (rc) {
2017 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
2018 __func__, irqcfg, rc);
2019 }
2020 if (fm_regulator != NULL) {
2021 rc = vreg_disable(fm_regulator);
2022
2023 if (rc) {
2024 printk(KERN_ERR "%s: return val: %d\n",
2025 __func__, rc);
2026 }
2027 fm_regulator = NULL;
2028 }
2029 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
2030 PMAPP_CLOCK_VOTE_OFF);
2031 if (rc < 0)
2032 printk(KERN_ERR "%s: clock_vote return val: %d\n",
2033 __func__, rc);
2034
2035 /*Disable the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
2036 of svlte*/
2037 if (machine_is_msm8x55_svlte_surf() ||
2038 machine_is_msm8x55_svlte_ffa()) {
2039 rc = marimba_gpio_config(0);
2040 if (rc < 0)
2041 printk(KERN_ERR "%s: clock disable for svlte : %d\n",
2042 __func__, rc);
2043 }
2044
2045
2046 if (!bahama_not_marimba) {
2047 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
2048
2049 if (rc < 0)
2050 printk(KERN_ERR "%s: vreg level vote return val: %d\n",
2051 __func__, rc);
2052 }
2053}
2054
2055static struct marimba_fm_platform_data marimba_fm_pdata = {
2056 .fm_setup = fm_radio_setup,
2057 .fm_shutdown = fm_radio_shutdown,
2058 .irq = MSM_GPIO_TO_INT(147),
2059 .vreg_s2 = NULL,
2060 .vreg_xo_out = NULL,
2061 .is_fm_soc_i2s_master = false,
2062 .config_i2s_gpio = NULL,
2063};
2064
2065
2066/* Slave id address for FM/CDC/QMEMBIST
2067 * Values can be programmed using Marimba slave id 0
2068 * should there be a conflict with other I2C devices
2069 * */
2070#define MARIMBA_SLAVE_ID_FM_ADDR 0x2A
2071#define MARIMBA_SLAVE_ID_CDC_ADDR 0x77
2072#define MARIMBA_SLAVE_ID_QMEMBIST_ADDR 0X66
2073
2074#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
2075#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
2076
2077static const char *tsadc_id = "MADC";
2078static const char *vregs_tsadc_name[] = {
2079 "gp12",
2080 "s2",
2081};
2082static struct vreg *vregs_tsadc[ARRAY_SIZE(vregs_tsadc_name)];
2083
2084static const char *vregs_timpani_tsadc_name[] = {
2085 "s3",
2086 "gp12",
2087 "gp16"
2088};
2089static struct vreg *vregs_timpani_tsadc[ARRAY_SIZE(vregs_timpani_tsadc_name)];
2090
2091static int marimba_tsadc_power(int vreg_on)
2092{
2093 int i, rc = 0;
2094 int tsadc_adie_type = adie_get_detected_codec_type();
2095
2096 if (tsadc_adie_type == TIMPANI_ID) {
2097 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2098 if (!vregs_timpani_tsadc[i]) {
2099 pr_err("%s: vreg_get %s failed(%d)\n",
2100 __func__, vregs_timpani_tsadc_name[i], rc);
2101 goto vreg_fail;
2102 }
2103
2104 rc = vreg_on ? vreg_enable(vregs_timpani_tsadc[i]) :
2105 vreg_disable(vregs_timpani_tsadc[i]);
2106 if (rc < 0) {
2107 pr_err("%s: vreg %s %s failed(%d)\n",
2108 __func__, vregs_timpani_tsadc_name[i],
2109 vreg_on ? "enable" : "disable", rc);
2110 goto vreg_fail;
2111 }
2112 }
2113 /* Vote for D0 and D1 buffer */
2114 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_D1,
2115 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2116 if (rc) {
2117 pr_err("%s: unable to %svote for d1 clk\n",
2118 __func__, vreg_on ? "" : "de-");
2119 goto do_vote_fail;
2120 }
2121 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2122 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2123 if (rc) {
2124 pr_err("%s: unable to %svote for d1 clk\n",
2125 __func__, vreg_on ? "" : "de-");
2126 goto do_vote_fail;
2127 }
2128 } else if (tsadc_adie_type == MARIMBA_ID) {
2129 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2130 if (!vregs_tsadc[i]) {
2131 pr_err("%s: vreg_get %s failed (%d)\n",
2132 __func__, vregs_tsadc_name[i], rc);
2133 goto vreg_fail;
2134 }
2135
2136 rc = vreg_on ? vreg_enable(vregs_tsadc[i]) :
2137 vreg_disable(vregs_tsadc[i]);
2138 if (rc < 0) {
2139 pr_err("%s: vreg %s %s failed (%d)\n",
2140 __func__, vregs_tsadc_name[i],
2141 vreg_on ? "enable" : "disable", rc);
2142 goto vreg_fail;
2143 }
2144 }
2145 /* If marimba vote for DO buffer */
2146 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2147 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2148 if (rc) {
2149 pr_err("%s: unable to %svote for d0 clk\n",
2150 __func__, vreg_on ? "" : "de-");
2151 goto do_vote_fail;
2152 }
2153 } else {
2154 pr_err("%s:Adie %d not supported\n",
2155 __func__, tsadc_adie_type);
2156 return -ENODEV;
2157 }
2158
2159 msleep(5); /* ensure power is stable */
2160
2161 return 0;
2162
2163do_vote_fail:
2164vreg_fail:
2165 while (i) {
2166 if (vreg_on) {
2167 if (tsadc_adie_type == TIMPANI_ID)
2168 vreg_disable(vregs_timpani_tsadc[--i]);
2169 else if (tsadc_adie_type == MARIMBA_ID)
2170 vreg_disable(vregs_tsadc[--i]);
2171 } else {
2172 if (tsadc_adie_type == TIMPANI_ID)
2173 vreg_enable(vregs_timpani_tsadc[--i]);
2174 else if (tsadc_adie_type == MARIMBA_ID)
2175 vreg_enable(vregs_tsadc[--i]);
2176 }
2177 }
2178
2179 return rc;
2180}
2181
2182static int marimba_tsadc_vote(int vote_on)
2183{
2184 int rc = 0;
2185
2186 if (adie_get_detected_codec_type() == MARIMBA_ID) {
2187 int level = vote_on ? 1300 : 0;
2188 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, level);
2189 if (rc < 0)
2190 pr_err("%s: vreg level %s failed (%d)\n",
2191 __func__, vote_on ? "on" : "off", rc);
2192 }
2193
2194 return rc;
2195}
2196
2197static int marimba_tsadc_init(void)
2198{
2199 int i, rc = 0;
2200 int tsadc_adie_type = adie_get_detected_codec_type();
2201
2202 if (tsadc_adie_type == TIMPANI_ID) {
2203 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2204 vregs_timpani_tsadc[i] = vreg_get(NULL,
2205 vregs_timpani_tsadc_name[i]);
2206 if (IS_ERR(vregs_timpani_tsadc[i])) {
2207 pr_err("%s: vreg get %s failed (%ld)\n",
2208 __func__, vregs_timpani_tsadc_name[i],
2209 PTR_ERR(vregs_timpani_tsadc[i]));
2210 rc = PTR_ERR(vregs_timpani_tsadc[i]);
2211 goto vreg_get_fail;
2212 }
2213 }
2214 } else if (tsadc_adie_type == MARIMBA_ID) {
2215 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2216 vregs_tsadc[i] = vreg_get(NULL, vregs_tsadc_name[i]);
2217 if (IS_ERR(vregs_tsadc[i])) {
2218 pr_err("%s: vreg get %s failed (%ld)\n",
2219 __func__, vregs_tsadc_name[i],
2220 PTR_ERR(vregs_tsadc[i]));
2221 rc = PTR_ERR(vregs_tsadc[i]);
2222 goto vreg_get_fail;
2223 }
2224 }
2225 } else {
2226 pr_err("%s:Adie %d not supported\n",
2227 __func__, tsadc_adie_type);
2228 return -ENODEV;
2229 }
2230
2231 return 0;
2232
2233vreg_get_fail:
2234 while (i) {
2235 if (tsadc_adie_type == TIMPANI_ID)
2236 vreg_put(vregs_timpani_tsadc[--i]);
2237 else if (tsadc_adie_type == MARIMBA_ID)
2238 vreg_put(vregs_tsadc[--i]);
2239 }
2240 return rc;
2241}
2242
2243static int marimba_tsadc_exit(void)
2244{
2245 int i, rc = 0;
2246 int tsadc_adie_type = adie_get_detected_codec_type();
2247
2248 if (tsadc_adie_type == TIMPANI_ID) {
2249 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2250 if (vregs_tsadc[i])
2251 vreg_put(vregs_timpani_tsadc[i]);
2252 }
2253 } else if (tsadc_adie_type == MARIMBA_ID) {
2254 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2255 if (vregs_tsadc[i])
2256 vreg_put(vregs_tsadc[i]);
2257 }
2258 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, 0);
2259 if (rc < 0)
2260 pr_err("%s: vreg level off failed (%d)\n",
2261 __func__, rc);
2262 } else {
2263 pr_err("%s:Adie %d not supported\n",
2264 __func__, tsadc_adie_type);
2265 rc = -ENODEV;
2266 }
2267
2268 return rc;
2269}
2270
2271
2272static struct msm_ts_platform_data msm_ts_data = {
2273 .min_x = 0,
2274 .max_x = 4096,
2275 .min_y = 0,
2276 .max_y = 4096,
2277 .min_press = 0,
2278 .max_press = 255,
2279 .inv_x = 4096,
2280 .inv_y = 4096,
2281 .can_wakeup = false,
2282};
2283
2284static struct marimba_tsadc_platform_data marimba_tsadc_pdata = {
2285 .marimba_tsadc_power = marimba_tsadc_power,
2286 .init = marimba_tsadc_init,
2287 .exit = marimba_tsadc_exit,
2288 .level_vote = marimba_tsadc_vote,
2289 .tsadc_prechg_en = true,
2290 .can_wakeup = false,
2291 .setup = {
2292 .pen_irq_en = true,
2293 .tsadc_en = true,
2294 },
2295 .params2 = {
2296 .input_clk_khz = 2400,
2297 .sample_prd = TSADC_CLK_3,
2298 },
2299 .params3 = {
2300 .prechg_time_nsecs = 6400,
2301 .stable_time_nsecs = 6400,
2302 .tsadc_test_mode = 0,
2303 },
2304 .tssc_data = &msm_ts_data,
2305};
2306
2307static struct vreg *vreg_codec_s4;
2308static int msm_marimba_codec_power(int vreg_on)
2309{
2310 int rc = 0;
2311
2312 if (!vreg_codec_s4) {
2313
2314 vreg_codec_s4 = vreg_get(NULL, "s4");
2315
2316 if (IS_ERR(vreg_codec_s4)) {
2317 printk(KERN_ERR "%s: vreg_get() failed (%ld)\n",
2318 __func__, PTR_ERR(vreg_codec_s4));
2319 rc = PTR_ERR(vreg_codec_s4);
2320 goto vreg_codec_s4_fail;
2321 }
2322 }
2323
2324 if (vreg_on) {
2325 rc = vreg_enable(vreg_codec_s4);
2326 if (rc)
2327 printk(KERN_ERR "%s: vreg_enable() = %d \n",
2328 __func__, rc);
2329 goto vreg_codec_s4_fail;
2330 } else {
2331 rc = vreg_disable(vreg_codec_s4);
2332 if (rc)
2333 printk(KERN_ERR "%s: vreg_disable() = %d \n",
2334 __func__, rc);
2335 goto vreg_codec_s4_fail;
2336 }
2337
2338vreg_codec_s4_fail:
2339 return rc;
2340}
2341
2342static struct marimba_codec_platform_data mariba_codec_pdata = {
2343 .marimba_codec_power = msm_marimba_codec_power,
2344#ifdef CONFIG_MARIMBA_CODEC
2345 .snddev_profile_init = msm_snddev_init,
2346#endif
2347};
2348
2349static struct marimba_platform_data marimba_pdata = {
2350 .slave_id[MARIMBA_SLAVE_ID_FM] = MARIMBA_SLAVE_ID_FM_ADDR,
2351 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2352 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2353 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
2354 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
2355 .marimba_setup = msm_marimba_setup_power,
2356 .marimba_shutdown = msm_marimba_shutdown_power,
2357 .bahama_setup = msm_bahama_setup_power,
2358 .bahama_shutdown = msm_bahama_shutdown_power,
2359 .marimba_gpio_config = msm_marimba_gpio_config_svlte,
2360 .bahama_core_config = msm_bahama_core_config,
2361 .fm = &marimba_fm_pdata,
2362 .codec = &mariba_codec_pdata,
2363 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2364};
2365
2366static void __init msm7x30_init_marimba(void)
2367{
2368 int rc;
2369
2370 vreg_marimba_1 = vreg_get(NULL, "s3");
2371 if (IS_ERR(vreg_marimba_1)) {
2372 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2373 __func__, PTR_ERR(vreg_marimba_1));
2374 return;
2375 }
2376 rc = vreg_set_level(vreg_marimba_1, 1800);
2377
2378 vreg_marimba_2 = vreg_get(NULL, "gp16");
2379 if (IS_ERR(vreg_marimba_1)) {
2380 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2381 __func__, PTR_ERR(vreg_marimba_1));
2382 return;
2383 }
2384 rc = vreg_set_level(vreg_marimba_2, 1200);
2385
2386 vreg_marimba_3 = vreg_get(NULL, "usb2");
2387 if (IS_ERR(vreg_marimba_3)) {
2388 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2389 __func__, PTR_ERR(vreg_marimba_3));
2390 return;
2391 }
2392 rc = vreg_set_level(vreg_marimba_3, 1800);
2393}
2394
2395static struct marimba_codec_platform_data timpani_codec_pdata = {
2396 .marimba_codec_power = msm_marimba_codec_power,
2397#ifdef CONFIG_TIMPANI_CODEC
2398 .snddev_profile_init = msm_snddev_init_timpani,
2399#endif
2400};
2401
2402static struct marimba_platform_data timpani_pdata = {
2403 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2404 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2405 .marimba_setup = msm_timpani_setup_power,
2406 .marimba_shutdown = msm_timpani_shutdown_power,
2407 .codec = &timpani_codec_pdata,
2408 .tsadc = &marimba_tsadc_pdata,
2409 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2410};
2411
2412#define TIMPANI_I2C_SLAVE_ADDR 0xD
2413
2414static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
2415 {
2416 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
2417 .platform_data = &timpani_pdata,
2418 },
2419};
2420
2421#ifdef CONFIG_MSM7KV2_AUDIO
2422static struct resource msm_aictl_resources[] = {
2423 {
2424 .name = "aictl",
2425 .start = 0xa5000100,
2426 .end = 0xa5000100,
2427 .flags = IORESOURCE_MEM,
2428 }
2429};
2430
2431static struct resource msm_mi2s_resources[] = {
2432 {
2433 .name = "hdmi",
2434 .start = 0xac900000,
2435 .end = 0xac900038,
2436 .flags = IORESOURCE_MEM,
2437 },
2438 {
2439 .name = "codec_rx",
2440 .start = 0xac940040,
2441 .end = 0xac940078,
2442 .flags = IORESOURCE_MEM,
2443 },
2444 {
2445 .name = "codec_tx",
2446 .start = 0xac980080,
2447 .end = 0xac9800B8,
2448 .flags = IORESOURCE_MEM,
2449 }
2450
2451};
2452
2453static struct msm_lpa_platform_data lpa_pdata = {
2454 .obuf_hlb_size = 0x2BFF8,
2455 .dsp_proc_id = 0,
2456 .app_proc_id = 2,
2457 .nosb_config = {
2458 .llb_min_addr = 0,
2459 .llb_max_addr = 0x3ff8,
2460 .sb_min_addr = 0,
2461 .sb_max_addr = 0,
2462 },
2463 .sb_config = {
2464 .llb_min_addr = 0,
2465 .llb_max_addr = 0x37f8,
2466 .sb_min_addr = 0x3800,
2467 .sb_max_addr = 0x3ff8,
2468 }
2469};
2470
2471static struct resource msm_lpa_resources[] = {
2472 {
2473 .name = "lpa",
2474 .start = 0xa5000000,
2475 .end = 0xa50000a0,
2476 .flags = IORESOURCE_MEM,
2477 }
2478};
2479
2480static struct resource msm_aux_pcm_resources[] = {
2481
2482 {
2483 .name = "aux_codec_reg_addr",
2484 .start = 0xac9c00c0,
2485 .end = 0xac9c00c8,
2486 .flags = IORESOURCE_MEM,
2487 },
2488 {
2489 .name = "aux_pcm_dout",
2490 .start = 138,
2491 .end = 138,
2492 .flags = IORESOURCE_IO,
2493 },
2494 {
2495 .name = "aux_pcm_din",
2496 .start = 139,
2497 .end = 139,
2498 .flags = IORESOURCE_IO,
2499 },
2500 {
2501 .name = "aux_pcm_syncout",
2502 .start = 140,
2503 .end = 140,
2504 .flags = IORESOURCE_IO,
2505 },
2506 {
2507 .name = "aux_pcm_clkin_a",
2508 .start = 141,
2509 .end = 141,
2510 .flags = IORESOURCE_IO,
2511 },
2512};
2513
2514static struct platform_device msm_aux_pcm_device = {
2515 .name = "msm_aux_pcm",
2516 .id = 0,
2517 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
2518 .resource = msm_aux_pcm_resources,
2519};
2520
2521struct platform_device msm_aictl_device = {
2522 .name = "audio_interct",
2523 .id = 0,
2524 .num_resources = ARRAY_SIZE(msm_aictl_resources),
2525 .resource = msm_aictl_resources,
2526};
2527
2528struct platform_device msm_mi2s_device = {
2529 .name = "mi2s",
2530 .id = 0,
2531 .num_resources = ARRAY_SIZE(msm_mi2s_resources),
2532 .resource = msm_mi2s_resources,
2533};
2534
2535struct platform_device msm_lpa_device = {
2536 .name = "lpa",
2537 .id = 0,
2538 .num_resources = ARRAY_SIZE(msm_lpa_resources),
2539 .resource = msm_lpa_resources,
2540 .dev = {
2541 .platform_data = &lpa_pdata,
2542 },
2543};
2544#endif /* CONFIG_MSM7KV2_AUDIO */
2545
2546#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2547 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2548 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2549 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2550 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2551 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2552#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2553 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2554 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2555 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2556 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2557 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2558 #define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2559 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2560 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2561 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2562 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2563 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2564 #define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2565 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2566 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2567 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2568 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2569 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2570#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
2571
2572static unsigned int dec_concurrency_table[] = {
2573 /* Audio LP */
2574 0,
2575 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2576 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2577 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2578 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_MODE_LP)|
2579 (1<<MSM_ADSP_OP_DM)),
2580
2581 /* Concurrency 1 */
2582 (DEC4_FORMAT),
2583 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2584 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2585 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2586 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2587
2588 /* Concurrency 2 */
2589 (DEC4_FORMAT),
2590 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2591 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2592 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2593 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2594
2595 /* Concurrency 3 */
2596 (DEC4_FORMAT),
2597 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2598 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2599 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2600 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2601
2602 /* Concurrency 4 */
2603 (DEC4_FORMAT),
2604 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2605 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2606 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2607 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2608
2609 /* Concurrency 5 */
2610 (DEC4_FORMAT),
2611 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2612 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2613 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2614 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2615
2616 /* Concurrency 6 */
2617 (DEC4_FORMAT),
2618 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2619 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2620 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2621 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2622};
2623
2624#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
2625 .module_queueid = queueid, .module_decid = decid, \
2626 .nr_codec_support = nr_codec}
2627
2628#define DEC_INSTANCE(max_instance_same, max_instance_diff) { \
2629 .max_instances_same_dec = max_instance_same, \
2630 .max_instances_diff_dec = max_instance_diff}
2631
2632static struct msm_adspdec_info dec_info_list[] = {
2633 DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
2634 DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
2635 DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
2636 DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
2637 DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
2638};
2639
2640static struct dec_instance_table dec_instance_list[][MSM_MAX_DEC_CNT] = {
2641 /* Non Turbo Mode */
2642 {
2643 DEC_INSTANCE(4, 3), /* WAV */
2644 DEC_INSTANCE(4, 3), /* ADPCM */
2645 DEC_INSTANCE(4, 2), /* MP3 */
2646 DEC_INSTANCE(0, 0), /* Real Audio */
2647 DEC_INSTANCE(4, 2), /* WMA */
2648 DEC_INSTANCE(3, 2), /* AAC */
2649 DEC_INSTANCE(0, 0), /* Reserved */
2650 DEC_INSTANCE(0, 0), /* MIDI */
2651 DEC_INSTANCE(4, 3), /* YADPCM */
2652 DEC_INSTANCE(4, 3), /* QCELP */
2653 DEC_INSTANCE(4, 3), /* AMRNB */
2654 DEC_INSTANCE(1, 1), /* AMRWB/WB+ */
2655 DEC_INSTANCE(4, 3), /* EVRC */
2656 DEC_INSTANCE(1, 1), /* WMAPRO */
2657 },
2658 /* Turbo Mode */
2659 {
2660 DEC_INSTANCE(4, 3), /* WAV */
2661 DEC_INSTANCE(4, 3), /* ADPCM */
2662 DEC_INSTANCE(4, 3), /* MP3 */
2663 DEC_INSTANCE(0, 0), /* Real Audio */
2664 DEC_INSTANCE(4, 3), /* WMA */
2665 DEC_INSTANCE(4, 3), /* AAC */
2666 DEC_INSTANCE(0, 0), /* Reserved */
2667 DEC_INSTANCE(0, 0), /* MIDI */
2668 DEC_INSTANCE(4, 3), /* YADPCM */
2669 DEC_INSTANCE(4, 3), /* QCELP */
2670 DEC_INSTANCE(4, 3), /* AMRNB */
2671 DEC_INSTANCE(2, 3), /* AMRWB/WB+ */
2672 DEC_INSTANCE(4, 3), /* EVRC */
2673 DEC_INSTANCE(1, 2), /* WMAPRO */
2674 },
2675};
2676
2677static struct msm_adspdec_database msm_device_adspdec_database = {
2678 .num_dec = ARRAY_SIZE(dec_info_list),
2679 .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
2680 ARRAY_SIZE(dec_info_list)),
2681 .dec_concurrency_table = dec_concurrency_table,
2682 .dec_info_list = dec_info_list,
2683 .dec_instance_list = &dec_instance_list[0][0],
2684};
2685
2686static struct platform_device msm_device_adspdec = {
2687 .name = "msm_adspdec",
2688 .id = -1,
2689 .dev = {
2690 .platform_data = &msm_device_adspdec_database
2691 },
2692};
2693
2694static struct resource smc91x_resources[] = {
2695 [0] = {
2696 .start = 0x8A000300,
2697 .end = 0x8A0003ff,
2698 .flags = IORESOURCE_MEM,
2699 },
2700 [1] = {
2701 .start = MSM_GPIO_TO_INT(156),
2702 .end = MSM_GPIO_TO_INT(156),
2703 .flags = IORESOURCE_IRQ,
2704 },
2705};
2706
2707static struct platform_device smc91x_device = {
2708 .name = "smc91x",
2709 .id = 0,
2710 .num_resources = ARRAY_SIZE(smc91x_resources),
2711 .resource = smc91x_resources,
2712};
2713
2714static struct smsc911x_platform_config smsc911x_config = {
2715 .phy_interface = PHY_INTERFACE_MODE_MII,
2716 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
2717 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
2718 .flags = SMSC911X_USE_32BIT,
2719};
2720
2721static struct resource smsc911x_resources[] = {
2722 [0] = {
2723 .start = 0x8D000000,
2724 .end = 0x8D000100,
2725 .flags = IORESOURCE_MEM,
2726 },
2727 [1] = {
2728 .start = MSM_GPIO_TO_INT(88),
2729 .end = MSM_GPIO_TO_INT(88),
2730 .flags = IORESOURCE_IRQ,
2731 },
2732};
2733
2734static struct platform_device smsc911x_device = {
2735 .name = "smsc911x",
2736 .id = -1,
2737 .num_resources = ARRAY_SIZE(smsc911x_resources),
2738 .resource = smsc911x_resources,
2739 .dev = {
2740 .platform_data = &smsc911x_config,
2741 },
2742};
2743
2744static struct msm_gpio smsc911x_gpios[] = {
2745 { GPIO_CFG(172, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr6" },
2746 { GPIO_CFG(173, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr5" },
2747 { GPIO_CFG(174, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr4" },
2748 { GPIO_CFG(175, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr3" },
2749 { GPIO_CFG(176, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr2" },
2750 { GPIO_CFG(177, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr1" },
2751 { GPIO_CFG(178, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr0" },
2752 { GPIO_CFG(88, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "smsc911x_irq" },
2753};
2754
2755static void msm7x30_cfg_smsc911x(void)
2756{
2757 int rc;
2758
2759 rc = msm_gpios_request_enable(smsc911x_gpios,
2760 ARRAY_SIZE(smsc911x_gpios));
2761 if (rc)
2762 pr_err("%s: unable to enable gpios\n", __func__);
2763}
2764
2765#ifdef CONFIG_USB_G_ANDROID
2766static struct android_usb_platform_data android_usb_pdata = {
2767 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
2768};
2769
2770static struct platform_device android_usb_device = {
2771 .name = "android_usb",
2772 .id = -1,
2773 .dev = {
2774 .platform_data = &android_usb_pdata,
2775 },
2776};
2777#endif
2778
2779static struct msm_gpio optnav_config_data[] = {
2780 { GPIO_CFG(OPTNAV_CHIP_SELECT, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA),
2781 "optnav_chip_select" },
2782};
2783
2784static void __iomem *virtual_optnav;
2785
2786static int optnav_gpio_setup(void)
2787{
2788 int rc = -ENODEV;
2789 rc = msm_gpios_request_enable(optnav_config_data,
2790 ARRAY_SIZE(optnav_config_data));
2791
2792 /* Configure the FPGA for GPIOs */
2793 virtual_optnav = ioremap(FPGA_OPTNAV_GPIO_ADDR, 0x4);
2794 if (!virtual_optnav) {
2795 pr_err("%s:Could not ioremap region\n", __func__);
2796 return -ENOMEM;
2797 }
2798 /*
2799 * Configure the FPGA to set GPIO 19 as
2800 * normal, active(enabled), output(MSM to SURF)
2801 */
2802 writew(0x311E, virtual_optnav);
2803 return rc;
2804}
2805
2806static void optnav_gpio_release(void)
2807{
2808 msm_gpios_disable_free(optnav_config_data,
2809 ARRAY_SIZE(optnav_config_data));
2810 iounmap(virtual_optnav);
2811}
2812
2813static struct vreg *vreg_gp7;
2814static struct vreg *vreg_gp4;
2815static struct vreg *vreg_gp9;
2816static struct vreg *vreg_usb3_3;
2817
2818static int optnav_enable(void)
2819{
2820 int rc;
2821 /*
2822 * Enable the VREGs L8(gp7), L10(gp4), L12(gp9), L6(usb)
2823 * for I2C communication with keyboard.
2824 */
2825 vreg_gp7 = vreg_get(NULL, "gp7");
2826 rc = vreg_set_level(vreg_gp7, 1800);
2827 if (rc) {
2828 pr_err("%s: vreg_set_level failed \n", __func__);
2829 goto fail_vreg_gp7;
2830 }
2831
2832 rc = vreg_enable(vreg_gp7);
2833 if (rc) {
2834 pr_err("%s: vreg_enable failed \n", __func__);
2835 goto fail_vreg_gp7;
2836 }
2837
2838 vreg_gp4 = vreg_get(NULL, "gp4");
2839 rc = vreg_set_level(vreg_gp4, 2600);
2840 if (rc) {
2841 pr_err("%s: vreg_set_level failed \n", __func__);
2842 goto fail_vreg_gp4;
2843 }
2844
2845 rc = vreg_enable(vreg_gp4);
2846 if (rc) {
2847 pr_err("%s: vreg_enable failed \n", __func__);
2848 goto fail_vreg_gp4;
2849 }
2850
2851 vreg_gp9 = vreg_get(NULL, "gp9");
2852 rc = vreg_set_level(vreg_gp9, 1800);
2853 if (rc) {
2854 pr_err("%s: vreg_set_level failed \n", __func__);
2855 goto fail_vreg_gp9;
2856 }
2857
2858 rc = vreg_enable(vreg_gp9);
2859 if (rc) {
2860 pr_err("%s: vreg_enable failed \n", __func__);
2861 goto fail_vreg_gp9;
2862 }
2863
2864 vreg_usb3_3 = vreg_get(NULL, "usb");
2865 rc = vreg_set_level(vreg_usb3_3, 3300);
2866 if (rc) {
2867 pr_err("%s: vreg_set_level failed \n", __func__);
2868 goto fail_vreg_3_3;
2869 }
2870
2871 rc = vreg_enable(vreg_usb3_3);
2872 if (rc) {
2873 pr_err("%s: vreg_enable failed \n", __func__);
2874 goto fail_vreg_3_3;
2875 }
2876
2877 /* Enable the chip select GPIO */
2878 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2879 gpio_set_value(OPTNAV_CHIP_SELECT, 0);
2880
2881 return 0;
2882
2883fail_vreg_3_3:
2884 vreg_disable(vreg_gp9);
2885fail_vreg_gp9:
2886 vreg_disable(vreg_gp4);
2887fail_vreg_gp4:
2888 vreg_disable(vreg_gp7);
2889fail_vreg_gp7:
2890 return rc;
2891}
2892
2893static void optnav_disable(void)
2894{
2895 vreg_disable(vreg_usb3_3);
2896 vreg_disable(vreg_gp9);
2897 vreg_disable(vreg_gp4);
2898 vreg_disable(vreg_gp7);
2899
2900 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2901}
2902
2903static struct ofn_atlab_platform_data optnav_data = {
2904 .gpio_setup = optnav_gpio_setup,
2905 .gpio_release = optnav_gpio_release,
2906 .optnav_on = optnav_enable,
2907 .optnav_off = optnav_disable,
2908 .rotate_xy = 0,
2909 .function1 = {
2910 .no_motion1_en = true,
2911 .touch_sensor_en = true,
2912 .ofn_en = true,
2913 .clock_select_khz = 1500,
2914 .cpi_selection = 1200,
2915 },
2916 .function2 = {
2917 .invert_y = false,
2918 .invert_x = true,
2919 .swap_x_y = false,
2920 .hold_a_b_en = true,
2921 .motion_filter_en = true,
2922 },
2923};
2924
2925static int hdmi_comm_power(int on, int show);
2926static int hdmi_init_irq(void);
2927static int hdmi_enable_5v(int on);
2928static int hdmi_core_power(int on, int show);
2929static int hdmi_cec_power(int on);
2930static bool hdmi_check_hdcp_hw_support(void);
2931
2932static struct msm_hdmi_platform_data adv7520_hdmi_data = {
2933 .irq = MSM_GPIO_TO_INT(18),
2934 .comm_power = hdmi_comm_power,
2935 .init_irq = hdmi_init_irq,
2936 .enable_5v = hdmi_enable_5v,
2937 .core_power = hdmi_core_power,
2938 .cec_power = hdmi_cec_power,
2939 .check_hdcp_hw_support = hdmi_check_hdcp_hw_support,
2940};
2941
2942#ifdef CONFIG_BOSCH_BMA150
2943static struct vreg *vreg_gp6;
2944static int sensors_ldo_enable(void)
2945{
2946 int rc;
2947
2948 /*
2949 * Enable the VREGs L8(gp7), L15(gp6)
2950 * for I2C communication with sensors.
2951 */
2952 pr_info("sensors_ldo_enable called!!\n");
2953 vreg_gp7 = vreg_get(NULL, "gp7");
2954 if (IS_ERR(vreg_gp7)) {
2955 pr_err("%s: vreg_get gp7 failed\n", __func__);
2956 rc = PTR_ERR(vreg_gp7);
2957 goto fail_gp7_get;
2958 }
2959
2960 rc = vreg_set_level(vreg_gp7, 1800);
2961 if (rc) {
2962 pr_err("%s: vreg_set_level gp7 failed\n", __func__);
2963 goto fail_gp7_level;
2964 }
2965
2966 rc = vreg_enable(vreg_gp7);
2967 if (rc) {
2968 pr_err("%s: vreg_enable gp7 failed\n", __func__);
2969 goto fail_gp7_level;
2970 }
2971
2972 vreg_gp6 = vreg_get(NULL, "gp6");
2973 if (IS_ERR(vreg_gp6)) {
2974 pr_err("%s: vreg_get gp6 failed\n", __func__);
2975 rc = PTR_ERR(vreg_gp6);
2976 goto fail_gp6_get;
2977 }
2978
2979 rc = vreg_set_level(vreg_gp6, 3050);
2980 if (rc) {
2981 pr_err("%s: vreg_set_level gp6 failed\n", __func__);
2982 goto fail_gp6_level;
2983 }
2984
2985 rc = vreg_enable(vreg_gp6);
2986 if (rc) {
2987 pr_err("%s: vreg_enable gp6 failed\n", __func__);
2988 goto fail_gp6_level;
2989 }
2990
2991 return 0;
2992
2993fail_gp6_level:
2994 vreg_put(vreg_gp6);
2995fail_gp6_get:
2996 vreg_disable(vreg_gp7);
2997fail_gp7_level:
2998 vreg_put(vreg_gp7);
2999fail_gp7_get:
3000 return rc;
3001}
3002
3003static void sensors_ldo_disable(void)
3004{
3005 pr_info("sensors_ldo_disable called!!\n");
3006 vreg_disable(vreg_gp6);
3007 vreg_put(vreg_gp6);
3008 vreg_disable(vreg_gp7);
3009 vreg_put(vreg_gp7);
3010}
3011static struct bma150_platform_data bma150_data = {
3012 .power_on = sensors_ldo_enable,
3013 .power_off = sensors_ldo_disable,
3014};
3015
3016static struct i2c_board_info bma150_board_info[] __initdata = {
3017 {
3018 I2C_BOARD_INFO("bma150", 0x38),
3019 .flags = I2C_CLIENT_WAKE,
3020 .irq = MSM_GPIO_TO_INT(BMA150_GPIO_INT),
3021 .platform_data = &bma150_data,
3022 },
3023};
3024#endif
3025
3026static struct i2c_board_info msm_i2c_board_info[] = {
3027 {
3028 I2C_BOARD_INFO("m33c01", OPTNAV_I2C_SLAVE_ADDR),
3029 .irq = MSM_GPIO_TO_INT(OPTNAV_IRQ),
3030 .platform_data = &optnav_data,
3031 },
3032 {
3033 I2C_BOARD_INFO("adv7520", ADV7520_I2C_ADDR),
3034 .platform_data = &adv7520_hdmi_data,
3035 },
3036};
3037
3038static struct i2c_board_info msm_marimba_board_info[] = {
3039 {
3040 I2C_BOARD_INFO("marimba", 0xc),
3041 .platform_data = &marimba_pdata,
3042 }
3043};
3044
3045
3046static struct msm_handset_platform_data hs_platform_data = {
3047 .hs_name = "7k_handset",
3048 .pwr_key_delay_ms = 500, /* 0 will disable end key */
3049};
3050
3051static struct platform_device hs_device = {
3052 .name = "msm-handset",
3053 .id = -1,
3054 .dev = {
3055 .platform_data = &hs_platform_data,
3056 },
3057};
3058
3059static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR] = {
3060 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = {
3061 .idle_supported = 1,
3062 .suspend_supported = 1,
3063 .idle_enabled = 1,
3064 .suspend_enabled = 1,
3065 .latency = 8594,
3066 .residency = 23740,
3067 },
3068 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN] = {
3069 .idle_supported = 1,
3070 .suspend_supported = 1,
3071 .idle_enabled = 1,
3072 .suspend_enabled = 1,
3073 .latency = 4594,
3074 .residency = 23740,
3075 },
3076 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] = {
3077#ifdef CONFIG_MSM_STANDALONE_POWER_COLLAPSE
3078 .idle_supported = 1,
3079 .suspend_supported = 1,
3080 .idle_enabled = 1,
3081 .suspend_enabled = 0,
3082#else /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3083 .idle_supported = 0,
3084 .suspend_supported = 0,
3085 .idle_enabled = 0,
3086 .suspend_enabled = 0,
3087#endif /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3088 .latency = 500,
3089 .residency = 6000,
3090 },
3091 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT] = {
3092 .idle_supported = 1,
3093 .suspend_supported = 1,
3094 .idle_enabled = 0,
3095 .suspend_enabled = 1,
3096 .latency = 443,
3097 .residency = 1098,
3098 },
3099 [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = {
3100 .idle_supported = 1,
3101 .suspend_supported = 1,
3102 .idle_enabled = 1,
3103 .suspend_enabled = 1,
3104 .latency = 2,
3105 .residency = 0,
3106 },
3107};
3108
3109static struct resource qsd_spi_resources[] = {
3110 {
3111 .name = "spi_irq_in",
3112 .start = INT_SPI_INPUT,
3113 .end = INT_SPI_INPUT,
3114 .flags = IORESOURCE_IRQ,
3115 },
3116 {
3117 .name = "spi_irq_out",
3118 .start = INT_SPI_OUTPUT,
3119 .end = INT_SPI_OUTPUT,
3120 .flags = IORESOURCE_IRQ,
3121 },
3122 {
3123 .name = "spi_irq_err",
3124 .start = INT_SPI_ERROR,
3125 .end = INT_SPI_ERROR,
3126 .flags = IORESOURCE_IRQ,
3127 },
3128 {
3129 .name = "spi_base",
3130 .start = 0xA8000000,
3131 .end = 0xA8000000 + SZ_4K - 1,
3132 .flags = IORESOURCE_MEM,
3133 },
3134 {
3135 .name = "spidm_channels",
3136 .flags = IORESOURCE_DMA,
3137 },
3138 {
3139 .name = "spidm_crci",
3140 .flags = IORESOURCE_DMA,
3141 },
3142};
3143
3144#define AMDH0_BASE_PHYS 0xAC200000
3145#define ADMH0_GP_CTL (ct_adm_base + 0x3D8)
3146static int msm_qsd_spi_dma_config(void)
3147{
3148 void __iomem *ct_adm_base = 0;
3149 u32 spi_mux = 0;
3150 int ret = 0;
3151
3152 ct_adm_base = ioremap(AMDH0_BASE_PHYS, PAGE_SIZE);
3153 if (!ct_adm_base) {
3154 pr_err("%s: Could not remap %x\n", __func__, AMDH0_BASE_PHYS);
3155 return -ENOMEM;
3156 }
3157
3158 spi_mux = (ioread32(ADMH0_GP_CTL) & (0x3 << 12)) >> 12;
3159
3160 qsd_spi_resources[4].start = DMOV_USB_CHAN;
3161 qsd_spi_resources[4].end = DMOV_TSIF_CHAN;
3162
3163 switch (spi_mux) {
3164 case (1):
3165 qsd_spi_resources[5].start = DMOV_HSUART1_RX_CRCI;
3166 qsd_spi_resources[5].end = DMOV_HSUART1_TX_CRCI;
3167 break;
3168 case (2):
3169 qsd_spi_resources[5].start = DMOV_HSUART2_RX_CRCI;
3170 qsd_spi_resources[5].end = DMOV_HSUART2_TX_CRCI;
3171 break;
3172 case (3):
3173 qsd_spi_resources[5].start = DMOV_CE_OUT_CRCI;
3174 qsd_spi_resources[5].end = DMOV_CE_IN_CRCI;
3175 break;
3176 default:
3177 ret = -ENOENT;
3178 }
3179
3180 iounmap(ct_adm_base);
3181
3182 return ret;
3183}
3184
3185static struct platform_device qsd_device_spi = {
3186 .name = "spi_qsd",
3187 .id = 0,
3188 .num_resources = ARRAY_SIZE(qsd_spi_resources),
3189 .resource = qsd_spi_resources,
3190};
3191
3192#ifdef CONFIG_SPI_QSD
3193static struct spi_board_info lcdc_sharp_spi_board_info[] __initdata = {
3194 {
3195 .modalias = "lcdc_sharp_ls038y7dx01",
3196 .mode = SPI_MODE_1,
3197 .bus_num = 0,
3198 .chip_select = 0,
3199 .max_speed_hz = 26331429,
3200 }
3201};
3202static struct spi_board_info lcdc_toshiba_spi_board_info[] __initdata = {
3203 {
3204 .modalias = "lcdc_toshiba_ltm030dd40",
3205 .mode = SPI_MODE_3|SPI_CS_HIGH,
3206 .bus_num = 0,
3207 .chip_select = 0,
3208 .max_speed_hz = 9963243,
3209 }
3210};
3211#endif
3212
3213static struct msm_gpio qsd_spi_gpio_config_data[] = {
3214 { GPIO_CFG(45, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3215 { GPIO_CFG(46, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3216 { GPIO_CFG(47, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "spi_mosi" },
3217 { GPIO_CFG(48, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3218};
3219
3220static int msm_qsd_spi_gpio_config(void)
3221{
3222 return msm_gpios_request_enable(qsd_spi_gpio_config_data,
3223 ARRAY_SIZE(qsd_spi_gpio_config_data));
3224}
3225
3226static void msm_qsd_spi_gpio_release(void)
3227{
3228 msm_gpios_disable_free(qsd_spi_gpio_config_data,
3229 ARRAY_SIZE(qsd_spi_gpio_config_data));
3230}
3231
3232static struct msm_spi_platform_data qsd_spi_pdata = {
3233 .max_clock_speed = 26331429,
3234 .gpio_config = msm_qsd_spi_gpio_config,
3235 .gpio_release = msm_qsd_spi_gpio_release,
3236 .dma_config = msm_qsd_spi_dma_config,
3237};
3238
3239static void __init msm_qsd_spi_init(void)
3240{
3241 qsd_device_spi.dev.platform_data = &qsd_spi_pdata;
3242}
3243
3244#ifdef CONFIG_USB_EHCI_MSM_72K
3245static void msm_hsusb_vbus_power(unsigned phy_info, int on)
3246{
3247 int rc;
3248 static int vbus_is_on;
3249 struct pm8058_gpio usb_vbus = {
3250 .direction = PM_GPIO_DIR_OUT,
3251 .pull = PM_GPIO_PULL_NO,
3252 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
3253 .output_value = 1,
3254 .vin_sel = 2,
3255 .out_strength = PM_GPIO_STRENGTH_MED,
3256 .function = PM_GPIO_FUNC_NORMAL,
3257 .inv_int_pol = 0,
3258 };
3259
3260 /* If VBUS is already on (or off), do nothing. */
3261 if (unlikely(on == vbus_is_on))
3262 return;
3263
3264 if (on) {
3265 rc = pm8058_gpio_config(36, &usb_vbus);
3266 if (rc) {
3267 pr_err("%s PMIC GPIO 36 write failed\n", __func__);
3268 return;
3269 }
3270 } else {
3271 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(36), 0);
3272 }
3273
3274 vbus_is_on = on;
3275}
3276
3277static struct msm_usb_host_platform_data msm_usb_host_pdata = {
3278 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
3279 .vbus_power = msm_hsusb_vbus_power,
3280 .power_budget = 180,
3281};
3282#endif
3283
3284#ifdef CONFIG_USB_MSM_OTG_72K
3285static int hsusb_rpc_connect(int connect)
3286{
3287 if (connect)
3288 return msm_hsusb_rpc_connect();
3289 else
3290 return msm_hsusb_rpc_close();
3291}
3292#endif
3293
3294#ifdef CONFIG_USB_MSM_OTG_72K
3295static struct vreg *vreg_3p3;
3296static int msm_hsusb_ldo_init(int init)
3297{
3298 uint32_t version = 0;
3299 int def_vol = 3400;
3300
3301 version = socinfo_get_version();
3302
3303 if (SOCINFO_VERSION_MAJOR(version) >= 2 &&
3304 SOCINFO_VERSION_MINOR(version) >= 1) {
3305 def_vol = 3075;
3306 pr_debug("%s: default voltage:%d\n", __func__, def_vol);
3307 }
3308
3309 if (init) {
3310 vreg_3p3 = vreg_get(NULL, "usb");
3311 if (IS_ERR(vreg_3p3))
3312 return PTR_ERR(vreg_3p3);
3313 vreg_set_level(vreg_3p3, def_vol);
3314 } else
3315 vreg_put(vreg_3p3);
3316
3317 return 0;
3318}
3319
3320static int msm_hsusb_ldo_enable(int enable)
3321{
3322 static int ldo_status;
3323
3324 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3325 return -ENODEV;
3326
3327 if (ldo_status == enable)
3328 return 0;
3329
3330 ldo_status = enable;
3331
3332 if (enable)
3333 return vreg_enable(vreg_3p3);
3334
3335 return vreg_disable(vreg_3p3);
3336}
3337
3338static int msm_hsusb_ldo_set_voltage(int mV)
3339{
3340 static int cur_voltage = 3400;
3341
3342 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3343 return -ENODEV;
3344
3345 if (cur_voltage == mV)
3346 return 0;
3347
3348 cur_voltage = mV;
3349
3350 pr_debug("%s: (%d)\n", __func__, mV);
3351
3352 return vreg_set_level(vreg_3p3, mV);
3353}
3354#endif
3355
3356#ifndef CONFIG_USB_EHCI_MSM_72K
3357static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init);
3358#endif
3359static struct msm_otg_platform_data msm_otg_pdata = {
3360 .rpc_connect = hsusb_rpc_connect,
3361
3362#ifndef CONFIG_USB_EHCI_MSM_72K
3363 .pmic_vbus_notif_init = msm_hsusb_pmic_notif_init,
3364#else
3365 .vbus_power = msm_hsusb_vbus_power,
3366#endif
3367 .core_clk = 1,
3368 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
3369 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
3370 .drv_ampl = HS_DRV_AMPLITUDE_DEFAULT,
3371 .se1_gating = SE1_GATING_DISABLE,
3372 .chg_vbus_draw = hsusb_chg_vbus_draw,
3373 .chg_connected = hsusb_chg_connected,
3374 .chg_init = hsusb_chg_init,
3375 .ldo_enable = msm_hsusb_ldo_enable,
3376 .ldo_init = msm_hsusb_ldo_init,
3377 .ldo_set_voltage = msm_hsusb_ldo_set_voltage,
3378};
3379
3380#ifdef CONFIG_USB_GADGET
3381static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
3382 .is_phy_status_timer_on = 1,
3383};
3384#endif
3385#ifndef CONFIG_USB_EHCI_MSM_72K
3386typedef void (*notify_vbus_state) (int);
3387notify_vbus_state notify_vbus_state_func_ptr;
3388int vbus_on_irq;
3389static irqreturn_t pmic_vbus_on_irq(int irq, void *data)
3390{
3391 pr_info("%s: vbus notification from pmic\n", __func__);
3392
3393 (*notify_vbus_state_func_ptr) (1);
3394
3395 return IRQ_HANDLED;
3396}
3397static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init)
3398{
3399 int ret;
3400
3401 if (init) {
3402 if (!callback)
3403 return -ENODEV;
3404
3405 notify_vbus_state_func_ptr = callback;
3406 vbus_on_irq = platform_get_irq_byname(&msm_device_otg,
3407 "vbus_on");
3408 if (vbus_on_irq <= 0) {
3409 pr_err("%s: unable to get vbus on irq\n", __func__);
3410 return -ENODEV;
3411 }
3412
3413 ret = request_any_context_irq(vbus_on_irq, pmic_vbus_on_irq,
3414 IRQF_TRIGGER_RISING, "msm_otg_vbus_on", NULL);
3415 if (ret < 0) {
3416 pr_info("%s: request_irq for vbus_on"
3417 "interrupt failed\n", __func__);
3418 return ret;
3419 }
3420 msm_otg_pdata.pmic_vbus_irq = vbus_on_irq;
3421 return 0;
3422 } else {
3423 free_irq(vbus_on_irq, 0);
3424 notify_vbus_state_func_ptr = NULL;
3425 return 0;
3426 }
3427}
3428#endif
3429
3430static struct android_pmem_platform_data android_pmem_pdata = {
3431 .name = "pmem",
3432 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
3433 .cached = 1,
3434 .memory_type = MEMTYPE_EBI0,
3435};
3436
3437static struct platform_device android_pmem_device = {
3438 .name = "android_pmem",
3439 .id = 0,
3440 .dev = { .platform_data = &android_pmem_pdata },
3441};
3442
3443#ifndef CONFIG_SPI_QSD
3444static int lcdc_gpio_array_num[] = {
3445 45, /* spi_clk */
3446 46, /* spi_cs */
3447 47, /* spi_mosi */
3448 48, /* spi_miso */
3449 };
3450
3451static struct msm_gpio lcdc_gpio_config_data[] = {
3452 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3453 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3454 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
3455 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3456};
3457
3458static void lcdc_config_gpios(int enable)
3459{
3460 if (enable) {
3461 msm_gpios_request_enable(lcdc_gpio_config_data,
3462 ARRAY_SIZE(
3463 lcdc_gpio_config_data));
3464 } else
3465 msm_gpios_disable_free(lcdc_gpio_config_data,
3466 ARRAY_SIZE(
3467 lcdc_gpio_config_data));
3468}
3469#endif
3470
3471static struct msm_panel_common_pdata lcdc_sharp_panel_data = {
3472#ifndef CONFIG_SPI_QSD
3473 .panel_config_gpio = lcdc_config_gpios,
3474 .gpio_num = lcdc_gpio_array_num,
3475#endif
3476 .gpio = 2, /* LPG PMIC_GPIO26 channel number */
3477};
3478
3479static struct platform_device lcdc_sharp_panel_device = {
3480 .name = "lcdc_sharp_wvga",
3481 .id = 0,
3482 .dev = {
3483 .platform_data = &lcdc_sharp_panel_data,
3484 }
3485};
3486
3487static struct msm_gpio dtv_panel_irq_gpios[] = {
3488 { GPIO_CFG(18, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA),
3489 "hdmi_int" },
3490};
3491
3492static struct msm_gpio dtv_panel_gpios[] = {
3493 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_mclk" },
3494 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd0" },
3495 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd1" },
3496 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd2" },
3497 { GPIO_CFG(124, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "dtv_pclk" },
3498 { GPIO_CFG(125, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_en" },
3499 { GPIO_CFG(126, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_vsync" },
3500 { GPIO_CFG(127, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_hsync" },
3501 { GPIO_CFG(128, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data0" },
3502 { GPIO_CFG(129, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data1" },
3503 { GPIO_CFG(130, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data2" },
3504 { GPIO_CFG(131, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data3" },
3505 { GPIO_CFG(132, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data4" },
3506 { GPIO_CFG(160, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data5" },
3507 { GPIO_CFG(161, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data6" },
3508 { GPIO_CFG(162, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data7" },
3509 { GPIO_CFG(163, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data8" },
3510 { GPIO_CFG(164, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data9" },
3511 { GPIO_CFG(165, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat10" },
3512 { GPIO_CFG(166, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat11" },
3513 { GPIO_CFG(167, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat12" },
3514 { GPIO_CFG(168, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat13" },
3515 { GPIO_CFG(169, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat14" },
3516 { GPIO_CFG(170, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat15" },
3517 { GPIO_CFG(171, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat16" },
3518 { GPIO_CFG(172, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat17" },
3519 { GPIO_CFG(173, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat18" },
3520 { GPIO_CFG(174, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat19" },
3521 { GPIO_CFG(175, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat20" },
3522 { GPIO_CFG(176, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat21" },
3523 { GPIO_CFG(177, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat22" },
3524 { GPIO_CFG(178, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat23" },
3525};
3526
3527
3528#ifdef HDMI_RESET
3529static unsigned dtv_reset_gpio =
3530 GPIO_CFG(37, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
3531#endif
3532
3533static int gpio_set(const char *label, const char *name, int level, int on)
3534{
3535 struct vreg *vreg = vreg_get(NULL, label);
3536 int rc;
3537
3538 if (IS_ERR(vreg)) {
3539 rc = PTR_ERR(vreg);
3540 pr_err("%s: vreg %s get failed (%d)\n",
3541 __func__, name, rc);
3542 return rc;
3543 }
3544
3545 rc = vreg_set_level(vreg, level);
3546 if (rc) {
3547 pr_err("%s: vreg %s set level failed (%d)\n",
3548 __func__, name, rc);
3549 return rc;
3550 }
3551
3552 if (on)
3553 rc = vreg_enable(vreg);
3554 else
3555 rc = vreg_disable(vreg);
3556 if (rc)
3557 pr_err("%s: vreg %s enable failed (%d)\n",
3558 __func__, name, rc);
3559 return rc;
3560}
3561
3562#if defined(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) || defined(CONFIG_BOSCH_BMA150)
3563/* there is an i2c address conflict between adv7520 and bma150 sensor after
3564 * power up on fluid. As a solution, the default address of adv7520's packet
3565 * memory is changed as soon as possible
3566 */
3567static int __init fluid_i2c_address_fixup(void)
3568{
3569 unsigned char wBuff[16];
3570 unsigned char rBuff[16];
3571 struct i2c_msg msgs[3];
3572 int res;
3573 int rc = -EINVAL;
3574 struct vreg *vreg_ldo8;
3575 struct i2c_adapter *adapter;
3576
3577 if (machine_is_msm7x30_fluid()) {
3578 adapter = i2c_get_adapter(0);
3579 if (!adapter) {
3580 pr_err("%s: invalid i2c adapter\n", __func__);
3581 return PTR_ERR(adapter);
3582 }
3583
3584 /* turn on LDO8 */
3585 vreg_ldo8 = vreg_get(NULL, "gp7");
3586 if (!vreg_ldo8) {
3587 pr_err("%s: VREG L8 get failed\n", __func__);
3588 goto adapter_put;
3589 }
3590
3591 rc = vreg_set_level(vreg_ldo8, 1800);
3592 if (rc) {
3593 pr_err("%s: VREG L8 set failed\n", __func__);
3594 goto ldo8_put;
3595 }
3596
3597 rc = vreg_enable(vreg_ldo8);
3598 if (rc) {
3599 pr_err("%s: VREG L8 enable failed\n", __func__);
3600 goto ldo8_put;
3601 }
3602
3603 /* change packet memory address to 0x74 */
3604 wBuff[0] = 0x45;
3605 wBuff[1] = 0x74;
3606
3607 msgs[0].addr = ADV7520_I2C_ADDR;
3608 msgs[0].flags = 0;
3609 msgs[0].buf = (unsigned char *) wBuff;
3610 msgs[0].len = 2;
3611
3612 res = i2c_transfer(adapter, msgs, 1);
3613 if (res != 1) {
3614 pr_err("%s: error writing adv7520\n", __func__);
3615 goto ldo8_disable;
3616 }
3617
3618 /* powerdown adv7520 using bit 6 */
3619 /* i2c read first */
3620 wBuff[0] = 0x41;
3621
3622 msgs[0].addr = ADV7520_I2C_ADDR;
3623 msgs[0].flags = 0;
3624 msgs[0].buf = (unsigned char *) wBuff;
3625 msgs[0].len = 1;
3626
3627 msgs[1].addr = ADV7520_I2C_ADDR;
3628 msgs[1].flags = I2C_M_RD;
3629 msgs[1].buf = rBuff;
3630 msgs[1].len = 1;
3631 res = i2c_transfer(adapter, msgs, 2);
3632 if (res != 2) {
3633 pr_err("%s: error reading adv7520\n", __func__);
3634 goto ldo8_disable;
3635 }
3636
3637 /* i2c write back */
3638 wBuff[0] = 0x41;
3639 wBuff[1] = rBuff[0] | 0x40;
3640
3641 msgs[0].addr = ADV7520_I2C_ADDR;
3642 msgs[0].flags = 0;
3643 msgs[0].buf = (unsigned char *) wBuff;
3644 msgs[0].len = 2;
3645
3646 res = i2c_transfer(adapter, msgs, 1);
3647 if (res != 1) {
3648 pr_err("%s: error writing adv7520\n", __func__);
3649 goto ldo8_disable;
3650 }
3651
3652 /* for successful fixup, we release the i2c adapter */
3653 /* but leave ldo8 on so that the adv7520 is not repowered */
3654 i2c_put_adapter(adapter);
3655 pr_info("%s: fluid i2c address conflict resolved\n", __func__);
3656 }
3657 return 0;
3658
3659ldo8_disable:
3660 vreg_disable(vreg_ldo8);
3661ldo8_put:
3662 vreg_put(vreg_ldo8);
3663adapter_put:
3664 i2c_put_adapter(adapter);
3665 return rc;
3666}
3667fs_initcall_sync(fluid_i2c_address_fixup);
3668#endif
3669
3670static int hdmi_comm_power(int on, int show)
3671{
3672 int rc = gpio_set("gp7", "LDO8", 1800, on);
3673 if (rc) {
3674 pr_warning("hdmi_comm_power: LDO8 gpio failed: rc=%d\n", rc);
3675 return rc;
3676 }
3677 rc = gpio_set("gp4", "LDO10", 2600, on);
3678 if (rc)
3679 pr_warning("hdmi_comm_power: LDO10 gpio failed: rc=%d\n", rc);
3680 if (show)
3681 pr_info("%s: i2c comm: %d <LDO8+LDO10>\n", __func__, on);
3682 return rc;
3683}
3684
3685static int hdmi_init_irq(void)
3686{
3687 int rc = msm_gpios_enable(dtv_panel_irq_gpios,
3688 ARRAY_SIZE(dtv_panel_irq_gpios));
3689 if (rc < 0) {
3690 pr_err("%s: gpio enable failed: %d\n", __func__, rc);
3691 return rc;
3692 }
3693 pr_info("%s\n", __func__);
3694
3695 return 0;
3696}
3697
3698static int hdmi_enable_5v(int on)
3699{
3700 int pmic_gpio_hdmi_5v_en ;
3701
3702 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
3703 machine_is_msm7x30_fluid())
3704 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
3705 else
3706 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
3707
3708 pr_info("%s: %d\n", __func__, on);
3709 if (on) {
3710 int rc;
3711 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en),
3712 "hdmi_5V_en");
3713 if (rc) {
3714 pr_err("%s PMIC_GPIO_HDMI_5V_EN gpio_request failed\n",
3715 __func__);
3716 return rc;
3717 }
3718 gpio_set_value_cansleep(
3719 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 1);
3720 } else {
3721 gpio_set_value_cansleep(
3722 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 0);
3723 gpio_free(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en));
3724 }
3725 return 0;
3726}
3727
3728static int hdmi_core_power(int on, int show)
3729{
3730 if (show)
3731 pr_info("%s: %d <LDO8>\n", __func__, on);
3732 return gpio_set("gp7", "LDO8", 1800, on);
3733}
3734
3735static int hdmi_cec_power(int on)
3736{
3737 pr_info("%s: %d <LDO17>\n", __func__, on);
3738 return gpio_set("gp11", "LDO17", 2600, on);
3739}
3740
3741static bool hdmi_check_hdcp_hw_support(void)
3742{
3743 if (machine_is_msm7x30_fluid())
3744 return false;
3745 else
3746 return true;
3747}
3748
3749static int dtv_panel_power(int on)
3750{
3751 int flag_on = !!on;
3752 static int dtv_power_save_on;
3753 int rc;
3754
3755 if (dtv_power_save_on == flag_on)
3756 return 0;
3757
3758 dtv_power_save_on = flag_on;
3759 pr_info("%s: %d\n", __func__, on);
3760
3761#ifdef HDMI_RESET
3762 if (on) {
3763 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
3764 rc = gpio_tlmm_config(dtv_reset_gpio, GPIO_CFG_ENABLE);
3765 if (rc) {
3766 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
3767 __func__, dtv_reset_gpio, rc);
3768 return rc;
3769 }
3770
3771 /* bring reset line low to hold reset*/
3772 gpio_set_value(37, 0);
3773 }
3774#endif
3775
3776 if (on) {
3777 rc = msm_gpios_enable(dtv_panel_gpios,
3778 ARRAY_SIZE(dtv_panel_gpios));
3779 if (rc < 0) {
3780 printk(KERN_ERR "%s: gpio enable failed: %d\n",
3781 __func__, rc);
3782 return rc;
3783 }
3784 } else {
3785 rc = msm_gpios_disable(dtv_panel_gpios,
3786 ARRAY_SIZE(dtv_panel_gpios));
3787 if (rc < 0) {
3788 printk(KERN_ERR "%s: gpio disable failed: %d\n",
3789 __func__, rc);
3790 return rc;
3791 }
3792 }
3793
3794 mdelay(5); /* ensure power is stable */
3795
3796#ifdef HDMI_RESET
3797 if (on) {
3798 gpio_set_value(37, 1); /* bring reset line high */
3799 mdelay(10); /* 10 msec before IO can be accessed */
3800 }
3801#endif
3802
3803 return rc;
3804}
3805
3806static struct lcdc_platform_data dtv_pdata = {
3807 .lcdc_power_save = dtv_panel_power,
3808};
3809
3810static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3811 .inject_rx_on_wakeup = 1,
3812 .rx_to_inject = 0xFD,
3813};
3814
3815static struct resource msm_fb_resources[] = {
3816 {
3817 .flags = IORESOURCE_DMA,
3818 }
3819};
3820
3821static int msm_fb_detect_panel(const char *name)
3822{
3823 if (machine_is_msm7x30_fluid()) {
3824 if (!strcmp(name, "lcdc_sharp_wvga_pt"))
3825 return 0;
3826 } else {
3827 if (!strncmp(name, "mddi_toshiba_wvga_pt", 20))
3828 return -EPERM;
3829 else if (!strncmp(name, "lcdc_toshiba_wvga_pt", 20))
3830 return 0;
3831 else if (!strcmp(name, "mddi_orise"))
3832 return -EPERM;
3833 else if (!strcmp(name, "mddi_quickvx"))
3834 return -EPERM;
3835 }
3836 return -ENODEV;
3837}
3838
3839static struct msm_fb_platform_data msm_fb_pdata = {
3840 .detect_client = msm_fb_detect_panel,
3841 .mddi_prescan = 1,
3842};
3843
3844static struct platform_device msm_fb_device = {
3845 .name = "msm_fb",
3846 .id = 0,
3847 .num_resources = ARRAY_SIZE(msm_fb_resources),
3848 .resource = msm_fb_resources,
3849 .dev = {
3850 .platform_data = &msm_fb_pdata,
3851 }
3852};
3853
3854static struct platform_device msm_migrate_pages_device = {
3855 .name = "msm_migrate_pages",
3856 .id = -1,
3857};
3858
3859static struct android_pmem_platform_data android_pmem_adsp_pdata = {
3860 .name = "pmem_adsp",
3861 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3862 .cached = 0,
3863 .memory_type = MEMTYPE_EBI0,
3864};
3865
3866static struct android_pmem_platform_data android_pmem_audio_pdata = {
3867 .name = "pmem_audio",
3868 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3869 .cached = 0,
3870 .memory_type = MEMTYPE_EBI0,
3871};
3872
3873static struct platform_device android_pmem_adsp_device = {
3874 .name = "android_pmem",
3875 .id = 2,
3876 .dev = { .platform_data = &android_pmem_adsp_pdata },
3877};
3878
3879static struct platform_device android_pmem_audio_device = {
3880 .name = "android_pmem",
3881 .id = 4,
3882 .dev = { .platform_data = &android_pmem_audio_pdata },
3883};
3884
3885#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3886 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
3887 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3888 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3889
3890#define QCE_SIZE 0x10000
3891#define QCE_0_BASE 0xA8400000
3892
3893#define QCE_HW_KEY_SUPPORT 1
3894#define QCE_SHA_HMAC_SUPPORT 0
3895#define QCE_SHARE_CE_RESOURCE 0
3896#define QCE_CE_SHARED 0
3897
3898static struct resource qcrypto_resources[] = {
3899 [0] = {
3900 .start = QCE_0_BASE,
3901 .end = QCE_0_BASE + QCE_SIZE - 1,
3902 .flags = IORESOURCE_MEM,
3903 },
3904 [1] = {
3905 .name = "crypto_channels",
3906 .start = DMOV_CE_IN_CHAN,
3907 .end = DMOV_CE_OUT_CHAN,
3908 .flags = IORESOURCE_DMA,
3909 },
3910 [2] = {
3911 .name = "crypto_crci_in",
3912 .start = DMOV_CE_IN_CRCI,
3913 .end = DMOV_CE_IN_CRCI,
3914 .flags = IORESOURCE_DMA,
3915 },
3916 [3] = {
3917 .name = "crypto_crci_out",
3918 .start = DMOV_CE_OUT_CRCI,
3919 .end = DMOV_CE_OUT_CRCI,
3920 .flags = IORESOURCE_DMA,
3921 },
3922 [4] = {
3923 .name = "crypto_crci_hash",
3924 .start = DMOV_CE_HASH_CRCI,
3925 .end = DMOV_CE_HASH_CRCI,
3926 .flags = IORESOURCE_DMA,
3927 },
3928};
3929
3930static struct resource qcedev_resources[] = {
3931 [0] = {
3932 .start = QCE_0_BASE,
3933 .end = QCE_0_BASE + QCE_SIZE - 1,
3934 .flags = IORESOURCE_MEM,
3935 },
3936 [1] = {
3937 .name = "crypto_channels",
3938 .start = DMOV_CE_IN_CHAN,
3939 .end = DMOV_CE_OUT_CHAN,
3940 .flags = IORESOURCE_DMA,
3941 },
3942 [2] = {
3943 .name = "crypto_crci_in",
3944 .start = DMOV_CE_IN_CRCI,
3945 .end = DMOV_CE_IN_CRCI,
3946 .flags = IORESOURCE_DMA,
3947 },
3948 [3] = {
3949 .name = "crypto_crci_out",
3950 .start = DMOV_CE_OUT_CRCI,
3951 .end = DMOV_CE_OUT_CRCI,
3952 .flags = IORESOURCE_DMA,
3953 },
3954 [4] = {
3955 .name = "crypto_crci_hash",
3956 .start = DMOV_CE_HASH_CRCI,
3957 .end = DMOV_CE_HASH_CRCI,
3958 .flags = IORESOURCE_DMA,
3959 },
3960};
3961
3962#endif
3963
3964#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3965 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
3966
3967static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
3968 .ce_shared = QCE_CE_SHARED,
3969 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3970 .hw_key_support = QCE_HW_KEY_SUPPORT,
3971 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3972};
3973
3974static struct platform_device qcrypto_device = {
3975 .name = "qcrypto",
3976 .id = 0,
3977 .num_resources = ARRAY_SIZE(qcrypto_resources),
3978 .resource = qcrypto_resources,
3979 .dev = {
3980 .coherent_dma_mask = DMA_BIT_MASK(32),
3981 .platform_data = &qcrypto_ce_hw_suppport,
3982 },
3983};
3984#endif
3985
3986#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3987 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3988
3989static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
3990 .ce_shared = QCE_CE_SHARED,
3991 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3992 .hw_key_support = QCE_HW_KEY_SUPPORT,
3993 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3994};
3995static struct platform_device qcedev_device = {
3996 .name = "qce",
3997 .id = 0,
3998 .num_resources = ARRAY_SIZE(qcedev_resources),
3999 .resource = qcedev_resources,
4000 .dev = {
4001 .coherent_dma_mask = DMA_BIT_MASK(32),
4002 .platform_data = &qcedev_ce_hw_suppport,
4003 },
4004};
4005#endif
4006
4007static int mddi_toshiba_pmic_bl(int level)
4008{
4009 int ret = -EPERM;
4010
4011 ret = pmic_set_led_intensity(LED_LCD, level);
4012
4013 if (ret)
4014 printk(KERN_WARNING "%s: can't set lcd backlight!\n",
4015 __func__);
4016 return ret;
4017}
4018
4019static struct msm_panel_common_pdata mddi_toshiba_pdata = {
4020 .pmic_backlight = mddi_toshiba_pmic_bl,
4021};
4022
4023static struct platform_device mddi_toshiba_device = {
4024 .name = "mddi_toshiba",
4025 .id = 0,
4026 .dev = {
4027 .platform_data = &mddi_toshiba_pdata,
4028 }
4029};
4030
4031static unsigned wega_reset_gpio =
4032 GPIO_CFG(180, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4033
4034static struct msm_gpio fluid_vee_reset_gpio[] = {
4035 { GPIO_CFG(20, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "vee_reset" },
4036};
4037
4038static unsigned char quickvx_mddi_client = 1, other_mddi_client = 1;
4039static unsigned char quickvx_ldo_enabled;
4040
4041static unsigned quickvx_vlp_gpio =
4042 GPIO_CFG(97, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4043
4044static struct pm8058_gpio pmic_quickvx_clk_gpio = {
4045 .direction = PM_GPIO_DIR_OUT,
4046 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
4047 .output_value = 1,
4048 .pull = PM_GPIO_PULL_NO,
4049 .vin_sel = PM_GPIO_VIN_S3,
4050 .out_strength = PM_GPIO_STRENGTH_HIGH,
4051 .function = PM_GPIO_FUNC_2,
4052};
4053
4054static int display_common_power(int on)
4055{
4056 int rc = 0, flag_on = !!on;
4057 static int display_common_power_save_on;
4058 struct vreg *vreg_ldo12, *vreg_ldo15 = NULL, *vreg_ldo6;
4059 struct vreg *vreg_ldo20, *vreg_ldo16, *vreg_ldo8 = NULL;
4060
4061 if (display_common_power_save_on == flag_on)
4062 return 0;
4063
4064 display_common_power_save_on = flag_on;
4065
4066 if (on) {
4067 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
4068 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_CFG_ENABLE);
4069 if (rc) {
4070 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4071 __func__, wega_reset_gpio, rc);
4072 return rc;
4073 }
4074
4075 /* bring reset line low to hold reset*/
4076 gpio_set_value(180, 0);
4077
4078 if (quickvx_mddi_client) {
4079 /* QuickVX chip -- VLP pin -- gpio 97 */
4080 rc = gpio_tlmm_config(quickvx_vlp_gpio,
4081 GPIO_CFG_ENABLE);
4082 if (rc) {
4083 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4084 __func__, quickvx_vlp_gpio, rc);
4085 return rc;
4086 }
4087
4088 /* bring QuickVX VLP line low */
4089 gpio_set_value(97, 0);
4090
4091 rc = pm8058_gpio_config(PMIC_GPIO_QUICKVX_CLK,
4092 &pmic_quickvx_clk_gpio);
4093 if (rc) {
4094 pr_err("%s: pm8058_gpio_config(%#x)=%d\n",
4095 __func__, PMIC_GPIO_QUICKVX_CLK + 1,
4096 rc);
4097 return rc;
4098 }
4099
4100 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4101 PMIC_GPIO_QUICKVX_CLK), 0);
4102 }
4103 }
4104
4105 /* Toshiba WeGA power -- has 3 power source */
4106 /* 1.5V -- LDO20*/
4107 vreg_ldo20 = vreg_get(NULL, "gp13");
4108
4109 if (IS_ERR(vreg_ldo20)) {
4110 rc = PTR_ERR(vreg_ldo20);
4111 pr_err("%s: gp13 vreg get failed (%d)\n",
4112 __func__, rc);
4113 return rc;
4114 }
4115
4116 /* 1.8V -- LDO12 */
4117 vreg_ldo12 = vreg_get(NULL, "gp9");
4118
4119 if (IS_ERR(vreg_ldo12)) {
4120 rc = PTR_ERR(vreg_ldo12);
4121 pr_err("%s: gp9 vreg get failed (%d)\n",
4122 __func__, rc);
4123 return rc;
4124 }
4125
4126 /* 2.6V -- LDO16 */
4127 vreg_ldo16 = vreg_get(NULL, "gp10");
4128
4129 if (IS_ERR(vreg_ldo16)) {
4130 rc = PTR_ERR(vreg_ldo16);
4131 pr_err("%s: gp10 vreg get failed (%d)\n",
4132 __func__, rc);
4133 return rc;
4134 }
4135
4136 /* 3.075V -- LDO6 */
4137 vreg_ldo6 = vreg_get(NULL, "usb");
4138
4139 if (IS_ERR(vreg_ldo6)) {
4140 rc = PTR_ERR(vreg_ldo6);
4141 pr_err("%s: usb vreg get failed (%d)\n",
4142 __func__, rc);
4143 return rc;
4144 }
4145
4146 if (machine_is_msm7x30_fluid()) {
4147 /* 1.8V -- LDO8 */
4148 vreg_ldo8 = vreg_get(NULL, "gp7");
4149
4150 if (IS_ERR(vreg_ldo8)) {
4151 rc = PTR_ERR(vreg_ldo8);
4152 pr_err("%s: gp7 vreg get failed (%d)\n",
4153 __func__, rc);
4154 return rc;
4155 }
4156 } else {
4157 /* lcd panel power */
4158 /* 3.1V -- LDO15 */
4159 vreg_ldo15 = vreg_get(NULL, "gp6");
4160
4161 if (IS_ERR(vreg_ldo15)) {
4162 rc = PTR_ERR(vreg_ldo15);
4163 pr_err("%s: gp6 vreg get failed (%d)\n",
4164 __func__, rc);
4165 return rc;
4166 }
4167 }
4168
4169 /* For QuickLogic chip, LDO20 requires 1.8V */
4170 /* Toshiba chip requires 1.5V, but can tolerate 1.8V since max is 3V */
4171 if (quickvx_mddi_client)
4172 rc = vreg_set_level(vreg_ldo20, 1800);
4173 else
4174 rc = vreg_set_level(vreg_ldo20, 1500);
4175 if (rc) {
4176 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4177 __func__, rc);
4178 return rc;
4179 }
4180
4181 rc = vreg_set_level(vreg_ldo12, 1800);
4182 if (rc) {
4183 pr_err("%s: vreg LDO12 set level failed (%d)\n",
4184 __func__, rc);
4185 return rc;
4186 }
4187
4188 if (other_mddi_client) {
4189 rc = vreg_set_level(vreg_ldo16, 2600);
4190 if (rc) {
4191 pr_err("%s: vreg LDO16 set level failed (%d)\n",
4192 __func__, rc);
4193 return rc;
4194 }
4195 }
4196
4197 if (quickvx_mddi_client) {
4198 rc = vreg_set_level(vreg_ldo6, 3075);
4199 if (rc) {
4200 pr_err("%s: vreg LDO6 set level failed (%d)\n",
4201 __func__, rc);
4202 return rc;
4203 }
4204 }
4205
4206 if (machine_is_msm7x30_fluid()) {
4207 rc = vreg_set_level(vreg_ldo8, 1800);
4208 if (rc) {
4209 pr_err("%s: vreg LDO8 set level failed (%d)\n",
4210 __func__, rc);
4211 return rc;
4212 }
4213 } else {
4214 rc = vreg_set_level(vreg_ldo15, 3100);
4215 if (rc) {
4216 pr_err("%s: vreg LDO15 set level failed (%d)\n",
4217 __func__, rc);
4218 return rc;
4219 }
4220 }
4221
4222 if (on) {
4223 rc = vreg_enable(vreg_ldo20);
4224 if (rc) {
4225 pr_err("%s: LDO20 vreg enable failed (%d)\n",
4226 __func__, rc);
4227 return rc;
4228 }
4229
4230 rc = vreg_enable(vreg_ldo12);
4231 if (rc) {
4232 pr_err("%s: LDO12 vreg enable failed (%d)\n",
4233 __func__, rc);
4234 return rc;
4235 }
4236
4237 if (other_mddi_client) {
4238 rc = vreg_enable(vreg_ldo16);
4239 if (rc) {
4240 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4241 __func__, rc);
4242 return rc;
4243 }
4244 }
4245
4246 if (quickvx_mddi_client && quickvx_ldo_enabled) {
4247 /* Disable LDO6 during display ON */
4248 rc = vreg_disable(vreg_ldo6);
4249 if (rc) {
4250 pr_err("%s: LDO6 vreg disable failed (%d)\n",
4251 __func__, rc);
4252 return rc;
4253 }
4254 quickvx_ldo_enabled = 0;
4255 }
4256
4257 if (machine_is_msm7x30_fluid()) {
4258 rc = vreg_enable(vreg_ldo8);
4259 if (rc) {
4260 pr_err("%s: LDO8 vreg enable failed (%d)\n",
4261 __func__, rc);
4262 return rc;
4263 }
4264 } else {
4265 rc = vreg_enable(vreg_ldo15);
4266 if (rc) {
4267 pr_err("%s: LDO15 vreg enable failed (%d)\n",
4268 __func__, rc);
4269 return rc;
4270 }
4271 }
4272
4273 mdelay(5); /* ensure power is stable */
4274
4275 if (machine_is_msm7x30_fluid()) {
4276 rc = msm_gpios_request_enable(fluid_vee_reset_gpio,
4277 ARRAY_SIZE(fluid_vee_reset_gpio));
4278 if (rc)
4279 pr_err("%s gpio_request_enable failed rc=%d\n",
4280 __func__, rc);
4281 else {
4282 /* assert vee reset_n */
4283 gpio_set_value(20, 1);
4284 gpio_set_value(20, 0);
4285 mdelay(1);
4286 gpio_set_value(20, 1);
4287 }
4288 }
4289
4290 gpio_set_value(180, 1); /* bring reset line high */
4291 mdelay(10); /* 10 msec before IO can be accessed */
4292
4293 if (quickvx_mddi_client) {
4294 gpio_set_value(97, 1);
4295 msleep(2);
4296 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4297 PMIC_GPIO_QUICKVX_CLK), 1);
4298 msleep(2);
4299 }
4300
4301 rc = pmapp_display_clock_config(1);
4302 if (rc) {
4303 pr_err("%s pmapp_display_clock_config rc=%d\n",
4304 __func__, rc);
4305 return rc;
4306 }
4307
4308 } else {
4309 rc = vreg_disable(vreg_ldo20);
4310 if (rc) {
4311 pr_err("%s: LDO20 vreg disable failed (%d)\n",
4312 __func__, rc);
4313 return rc;
4314 }
4315
4316
4317 if (other_mddi_client) {
4318 rc = vreg_disable(vreg_ldo16);
4319 if (rc) {
4320 pr_err("%s: LDO16 vreg disable failed (%d)\n",
4321 __func__, rc);
4322 return rc;
4323 }
4324 }
4325
4326 if (quickvx_mddi_client && !quickvx_ldo_enabled) {
4327 /* Enable LDO6 during display OFF for
4328 Quicklogic chip to sleep with data retention */
4329 rc = vreg_enable(vreg_ldo6);
4330 if (rc) {
4331 pr_err("%s: LDO6 vreg enable failed (%d)\n",
4332 __func__, rc);
4333 return rc;
4334 }
4335 quickvx_ldo_enabled = 1;
4336 }
4337
4338 gpio_set_value(180, 0); /* bring reset line low */
4339
4340 if (quickvx_mddi_client) {
4341 gpio_set_value(97, 0);
4342 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4343 PMIC_GPIO_QUICKVX_CLK), 0);
4344 }
4345
4346 if (machine_is_msm7x30_fluid()) {
4347 rc = vreg_disable(vreg_ldo8);
4348 if (rc) {
4349 pr_err("%s: LDO8 vreg disable failed (%d)\n",
4350 __func__, rc);
4351 return rc;
4352 }
4353 } else {
4354 rc = vreg_disable(vreg_ldo15);
4355 if (rc) {
4356 pr_err("%s: LDO15 vreg disable failed (%d)\n",
4357 __func__, rc);
4358 return rc;
4359 }
4360 }
4361
4362 mdelay(5); /* ensure power is stable */
4363
4364 rc = vreg_disable(vreg_ldo12);
4365 if (rc) {
4366 pr_err("%s: LDO12 vreg disable failed (%d)\n",
4367 __func__, rc);
4368 return rc;
4369 }
4370
4371 if (machine_is_msm7x30_fluid()) {
4372 msm_gpios_disable_free(fluid_vee_reset_gpio,
4373 ARRAY_SIZE(fluid_vee_reset_gpio));
4374 }
4375
4376 rc = pmapp_display_clock_config(0);
4377 if (rc) {
4378 pr_err("%s pmapp_display_clock_config rc=%d\n",
4379 __func__, rc);
4380 return rc;
4381 }
4382 }
4383
4384 return rc;
4385}
4386
4387static int msm_fb_mddi_sel_clk(u32 *clk_rate)
4388{
4389 *clk_rate *= 2;
4390 return 0;
4391}
4392
4393static int msm_fb_mddi_client_power(u32 client_id)
4394{
4395 struct vreg *vreg_ldo20, *vreg_ldo16;
4396 int rc;
4397
4398 printk(KERN_NOTICE "\n client_id = 0x%x", client_id);
4399 /* Check if it is Quicklogic client */
4400 if (client_id == 0xc5835800) {
4401 printk(KERN_NOTICE "\n Quicklogic MDDI client");
4402 other_mddi_client = 0;
4403 vreg_ldo16 = vreg_get(NULL, "gp10");
4404
4405 if (IS_ERR(vreg_ldo16)) {
4406 rc = PTR_ERR(vreg_ldo16);
4407 pr_err("%s: gp10 vreg get failed (%d)\n",
4408 __func__, rc);
4409 return rc;
4410 }
4411
4412 rc = vreg_disable(vreg_ldo16);
4413 if (rc) {
4414 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4415 __func__, rc);
4416 return rc;
4417 }
4418 } else {
4419 printk(KERN_NOTICE "\n Non-Quicklogic MDDI client");
4420 quickvx_mddi_client = 0;
4421 gpio_set_value(97, 0);
4422 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4423 PMIC_GPIO_QUICKVX_CLK), 0);
4424
4425 vreg_ldo20 = vreg_get(NULL, "gp13");
4426
4427 if (IS_ERR(vreg_ldo20)) {
4428 rc = PTR_ERR(vreg_ldo20);
4429 pr_err("%s: gp13 vreg get failed (%d)\n",
4430 __func__, rc);
4431 return rc;
4432 }
4433 rc = vreg_set_level(vreg_ldo20, 1500);
4434 if (rc) {
4435 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4436 __func__, rc);
4437 return rc;
4438 }
4439 }
4440 return 0;
4441}
4442
4443static struct mddi_platform_data mddi_pdata = {
4444 .mddi_power_save = display_common_power,
4445 .mddi_sel_clk = msm_fb_mddi_sel_clk,
4446 .mddi_client_power = msm_fb_mddi_client_power,
4447};
4448
4449int mdp_core_clk_rate_table[] = {
4450 122880000,
4451 122880000,
Pradeep Jilagam3cc12f92011-07-26 22:25:18 +05304452 192000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004453 192000000,
4454};
4455
4456static struct msm_panel_common_pdata mdp_pdata = {
4457 .hw_revision_addr = 0xac001270,
4458 .gpio = 30,
4459 .mdp_core_clk_rate = 122880000,
4460 .mdp_core_clk_table = mdp_core_clk_rate_table,
4461 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
Ravishangar Kalyanam07ef7882011-08-09 15:50:48 -07004462 .mdp_rev = MDP_REV_40,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004463};
4464
4465static int lcd_panel_spi_gpio_num[] = {
4466 45, /* spi_clk */
4467 46, /* spi_cs */
4468 47, /* spi_mosi */
4469 48, /* spi_miso */
4470 };
4471
4472static struct msm_gpio lcd_panel_gpios[] = {
4473/* Workaround, since HDMI_INT is using the same GPIO line (18), and is used as
4474 * input. if there is a hardware revision; we should reassign this GPIO to a
4475 * new open line; and removing it will just ensure that this will be missed in
4476 * the future.
4477 { GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn0" },
4478 */
4479 { GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn1" },
4480 { GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu0" },
4481 { GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu1" },
4482 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4483 { GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red0" },
4484 { GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red1" },
4485 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4486#ifndef CONFIG_SPI_QSD
4487 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
4488 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
4489 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
4490 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
4491#endif
4492 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4493 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4494 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4495 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4496 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4497 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4498 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4499 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4500 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4501 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4502 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4503 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4504 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4505 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4506 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4507 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4508 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4509 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4510 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4511 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4512};
4513
4514static struct msm_gpio lcd_sharp_panel_gpios[] = {
4515 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4516 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4517 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4518 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4519 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4520 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4521 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4522 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4523 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4524 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4525 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4526 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4527 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4528 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4529 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4530 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4531 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4532 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4533 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4534 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4535 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4536 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4537};
4538
4539static int lcdc_toshiba_panel_power(int on)
4540{
4541 int rc, i;
4542 struct msm_gpio *gp;
4543
4544 rc = display_common_power(on);
4545 if (rc < 0) {
4546 printk(KERN_ERR "%s display_common_power failed: %d\n",
4547 __func__, rc);
4548 return rc;
4549 }
4550
4551 if (on) {
4552 rc = msm_gpios_enable(lcd_panel_gpios,
4553 ARRAY_SIZE(lcd_panel_gpios));
4554 if (rc < 0) {
4555 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4556 __func__, rc);
4557 }
4558 } else { /* off */
4559 gp = lcd_panel_gpios;
4560 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
4561 /* ouput low */
4562 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4563 gp++;
4564 }
4565 }
4566
4567 return rc;
4568}
4569
4570static int lcdc_sharp_panel_power(int on)
4571{
4572 int rc, i;
4573 struct msm_gpio *gp;
4574
4575 rc = display_common_power(on);
4576 if (rc < 0) {
4577 printk(KERN_ERR "%s display_common_power failed: %d\n",
4578 __func__, rc);
4579 return rc;
4580 }
4581
4582 if (on) {
4583 rc = msm_gpios_enable(lcd_sharp_panel_gpios,
4584 ARRAY_SIZE(lcd_sharp_panel_gpios));
4585 if (rc < 0) {
4586 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4587 __func__, rc);
4588 }
4589 } else { /* off */
4590 gp = lcd_sharp_panel_gpios;
4591 for (i = 0; i < ARRAY_SIZE(lcd_sharp_panel_gpios); i++) {
4592 /* ouput low */
4593 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4594 gp++;
4595 }
4596 }
4597
4598 return rc;
4599}
4600
4601static int lcdc_panel_power(int on)
4602{
4603 int flag_on = !!on;
4604 static int lcdc_power_save_on;
4605
4606 if (lcdc_power_save_on == flag_on)
4607 return 0;
4608
4609 lcdc_power_save_on = flag_on;
4610 quickvx_mddi_client = 0;
4611
4612 if (machine_is_msm7x30_fluid())
4613 return lcdc_sharp_panel_power(on);
4614 else
4615 return lcdc_toshiba_panel_power(on);
4616}
4617
4618static struct lcdc_platform_data lcdc_pdata = {
4619 .lcdc_power_save = lcdc_panel_power,
4620};
4621
4622static int atv_dac_power(int on)
4623{
4624 int rc = 0;
4625 struct vreg *vreg_s4, *vreg_ldo9;
4626
4627 vreg_s4 = vreg_get(NULL, "s4");
4628 if (IS_ERR(vreg_s4)) {
4629 rc = PTR_ERR(vreg_s4);
4630 pr_err("%s: s4 vreg get failed (%d)\n",
4631 __func__, rc);
4632 return -1;
4633 }
4634 vreg_ldo9 = vreg_get(NULL, "gp1");
4635 if (IS_ERR(vreg_ldo9)) {
4636 rc = PTR_ERR(vreg_ldo9);
4637 pr_err("%s: ldo9 vreg get failed (%d)\n",
4638 __func__, rc);
4639 return rc;
4640 }
4641
4642 if (on) {
4643 rc = vreg_enable(vreg_s4);
4644 if (rc) {
4645 pr_err("%s: s4 vreg enable failed (%d)\n",
4646 __func__, rc);
4647 return rc;
4648 }
4649 rc = vreg_enable(vreg_ldo9);
4650 if (rc) {
4651 pr_err("%s: ldo9 vreg enable failed (%d)\n",
4652 __func__, rc);
4653 return rc;
4654 }
4655 } else {
4656 rc = vreg_disable(vreg_ldo9);
4657 if (rc) {
4658 pr_err("%s: ldo9 vreg disable failed (%d)\n",
4659 __func__, rc);
4660 return rc;
4661 }
4662 rc = vreg_disable(vreg_s4);
4663 if (rc) {
4664 pr_err("%s: s4 vreg disable failed (%d)\n",
4665 __func__, rc);
4666 return rc;
4667 }
4668 }
4669 return rc;
4670}
4671
4672static struct tvenc_platform_data atv_pdata = {
4673 .poll = 1,
4674 .pm_vid_en = atv_dac_power,
4675};
4676
4677static void __init msm_fb_add_devices(void)
4678{
4679 msm_fb_register_device("mdp", &mdp_pdata);
4680 msm_fb_register_device("pmdh", &mddi_pdata);
4681 msm_fb_register_device("lcdc", &lcdc_pdata);
4682 msm_fb_register_device("dtv", &dtv_pdata);
4683 msm_fb_register_device("tvenc", &atv_pdata);
4684#ifdef CONFIG_FB_MSM_TVOUT
4685 msm_fb_register_device("tvout_device", NULL);
4686#endif
4687}
4688
4689static struct msm_panel_common_pdata lcdc_toshiba_panel_data = {
4690 .gpio_num = lcd_panel_spi_gpio_num,
4691};
4692
4693static struct platform_device lcdc_toshiba_panel_device = {
4694 .name = "lcdc_toshiba_wvga",
4695 .id = 0,
4696 .dev = {
4697 .platform_data = &lcdc_toshiba_panel_data,
4698 }
4699};
4700
4701#if defined(CONFIG_MARIMBA_CORE) && \
4702 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4703static struct platform_device msm_bt_power_device = {
4704 .name = "bt_power",
4705 .id = -1
4706};
4707
4708enum {
4709 BT_RFR,
4710 BT_CTS,
4711 BT_RX,
4712 BT_TX,
4713};
4714
4715static struct msm_gpio bt_config_power_on[] = {
4716 { GPIO_CFG(134, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4717 "UART1DM_RFR" },
4718 { GPIO_CFG(135, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4719 "UART1DM_CTS" },
4720 { GPIO_CFG(136, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4721 "UART1DM_Rx" },
4722 { GPIO_CFG(137, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4723 "UART1DM_Tx" }
4724};
4725
4726static struct msm_gpio bt_config_power_off[] = {
4727 { GPIO_CFG(134, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4728 "UART1DM_RFR" },
4729 { GPIO_CFG(135, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4730 "UART1DM_CTS" },
4731 { GPIO_CFG(136, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4732 "UART1DM_Rx" },
4733 { GPIO_CFG(137, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4734 "UART1DM_Tx" }
4735};
4736
4737static const char *vregs_bt_marimba_name[] = {
4738 "s3",
4739 "s2",
4740 "gp16",
4741 "wlan"
4742};
4743static struct vreg *vregs_bt_marimba[ARRAY_SIZE(vregs_bt_marimba_name)];
4744
4745static const char *vregs_bt_bahama_name[] = {
4746 "s3",
4747 "usb2",
4748 "s2",
4749 "wlan"
4750};
4751static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
4752
4753static u8 bahama_version;
4754
4755static int marimba_bt(int on)
4756{
4757 int rc;
4758 int i;
4759 struct marimba config = { .mod_id = MARIMBA_SLAVE_ID_MARIMBA };
4760
4761 struct marimba_config_register {
4762 u8 reg;
4763 u8 value;
4764 u8 mask;
4765 };
4766
4767 struct marimba_variant_register {
4768 const size_t size;
4769 const struct marimba_config_register *set;
4770 };
4771
4772 const struct marimba_config_register *p;
4773
4774 u8 version;
4775
4776 const struct marimba_config_register v10_bt_on[] = {
4777 { 0xE5, 0x0B, 0x0F },
4778 { 0x05, 0x02, 0x07 },
4779 { 0x06, 0x88, 0xFF },
4780 { 0xE7, 0x21, 0x21 },
4781 { 0xE3, 0x38, 0xFF },
4782 { 0xE4, 0x06, 0xFF },
4783 };
4784
4785 const struct marimba_config_register v10_bt_off[] = {
4786 { 0xE5, 0x0B, 0x0F },
4787 { 0x05, 0x08, 0x0F },
4788 { 0x06, 0x88, 0xFF },
4789 { 0xE7, 0x00, 0x21 },
4790 { 0xE3, 0x00, 0xFF },
4791 { 0xE4, 0x00, 0xFF },
4792 };
4793
4794 const struct marimba_config_register v201_bt_on[] = {
4795 { 0x05, 0x08, 0x07 },
4796 { 0x06, 0x88, 0xFF },
4797 { 0xE7, 0x21, 0x21 },
4798 { 0xE3, 0x38, 0xFF },
4799 { 0xE4, 0x06, 0xFF },
4800 };
4801
4802 const struct marimba_config_register v201_bt_off[] = {
4803 { 0x05, 0x08, 0x07 },
4804 { 0x06, 0x88, 0xFF },
4805 { 0xE7, 0x00, 0x21 },
4806 { 0xE3, 0x00, 0xFF },
4807 { 0xE4, 0x00, 0xFF },
4808 };
4809
4810 const struct marimba_config_register v210_bt_on[] = {
4811 { 0xE9, 0x01, 0x01 },
4812 { 0x06, 0x88, 0xFF },
4813 { 0xE7, 0x21, 0x21 },
4814 { 0xE3, 0x38, 0xFF },
4815 { 0xE4, 0x06, 0xFF },
4816 };
4817
4818 const struct marimba_config_register v210_bt_off[] = {
4819 { 0x06, 0x88, 0xFF },
4820 { 0xE7, 0x00, 0x21 },
4821 { 0xE9, 0x00, 0x01 },
4822 { 0xE3, 0x00, 0xFF },
4823 { 0xE4, 0x00, 0xFF },
4824 };
4825
4826 const struct marimba_variant_register bt_marimba[2][4] = {
4827 {
4828 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4829 { 0, NULL },
4830 { ARRAY_SIZE(v201_bt_off), v201_bt_off },
4831 { ARRAY_SIZE(v210_bt_off), v210_bt_off }
4832 },
4833 {
4834 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4835 { 0, NULL },
4836 { ARRAY_SIZE(v201_bt_on), v201_bt_on },
4837 { ARRAY_SIZE(v210_bt_on), v210_bt_on }
4838 }
4839 };
4840
4841 on = on ? 1 : 0;
4842
4843 rc = marimba_read_bit_mask(&config, 0x11, &version, 1, 0x1F);
4844 if (rc < 0) {
4845 printk(KERN_ERR
4846 "%s: version read failed: %d\n",
4847 __func__, rc);
4848 return rc;
4849 }
4850
4851 if ((version >= ARRAY_SIZE(bt_marimba[on])) ||
4852 (bt_marimba[on][version].size == 0)) {
4853 printk(KERN_ERR
4854 "%s: unsupported version\n",
4855 __func__);
4856 return -EIO;
4857 }
4858
4859 p = bt_marimba[on][version].set;
4860
4861 printk(KERN_INFO "%s: found version %d\n", __func__, version);
4862
4863 for (i = 0; i < bt_marimba[on][version].size; i++) {
4864 u8 value = (p+i)->value;
4865 rc = marimba_write_bit_mask(&config,
4866 (p+i)->reg,
4867 &value,
4868 sizeof((p+i)->value),
4869 (p+i)->mask);
4870 if (rc < 0) {
4871 printk(KERN_ERR
4872 "%s: reg %d write failed: %d\n",
4873 __func__, (p+i)->reg, rc);
4874 return rc;
4875 }
4876 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x mask 0x%02x\n",
4877 __func__, (p+i)->reg,
4878 value, (p+i)->mask);
4879 }
4880 return 0;
4881}
4882
4883static int bahama_bt(int on)
4884{
4885 int rc;
4886 int i;
4887 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
4888
4889 struct bahama_variant_register {
4890 const size_t size;
4891 const struct bahama_config_register *set;
4892 };
4893
4894 const struct bahama_config_register *p;
4895
4896
4897 const struct bahama_config_register v10_bt_on[] = {
4898 { 0xE9, 0x00, 0xFF },
4899 { 0xF4, 0x80, 0xFF },
4900 { 0xF0, 0x06, 0xFF },
4901 { 0xE4, 0x00, 0xFF },
4902 { 0xE5, 0x00, 0x0F },
4903#ifdef CONFIG_WLAN
4904 { 0xE6, 0x38, 0x7F },
4905 { 0xE7, 0x06, 0xFF },
4906#endif
4907 { 0x11, 0x13, 0xFF },
4908 { 0xE9, 0x21, 0xFF },
4909 { 0x01, 0x0C, 0x1F },
4910 { 0x01, 0x08, 0x1F },
4911 };
4912
4913 const struct bahama_config_register v20_bt_on_fm_off[] = {
4914 { 0x11, 0x0C, 0xFF },
4915 { 0x13, 0x01, 0xFF },
4916 { 0xF4, 0x80, 0xFF },
4917 { 0xF0, 0x00, 0xFF },
4918 { 0xE9, 0x00, 0xFF },
4919#ifdef CONFIG_WLAN
4920 { 0x81, 0x00, 0xFF },
4921 { 0x82, 0x00, 0xFF },
4922 { 0xE6, 0x38, 0x7F },
4923 { 0xE7, 0x06, 0xFF },
4924#endif
4925 { 0xE9, 0x21, 0xFF }
4926 };
4927
4928 const struct bahama_config_register v20_bt_on_fm_on[] = {
4929 { 0x11, 0x0C, 0xFF },
4930 { 0x13, 0x01, 0xFF },
4931 { 0xF4, 0x86, 0xFF },
4932 { 0xF0, 0x06, 0xFF },
4933 { 0xE9, 0x00, 0xFF },
4934#ifdef CONFIG_WLAN
4935 { 0x81, 0x00, 0xFF },
4936 { 0x82, 0x00, 0xFF },
4937 { 0xE6, 0x38, 0x7F },
4938 { 0xE7, 0x06, 0xFF },
4939#endif
4940 { 0xE9, 0x21, 0xFF }
4941 };
4942
4943 const struct bahama_config_register v10_bt_off[] = {
4944 { 0xE9, 0x00, 0xFF },
4945 };
4946
4947 const struct bahama_config_register v20_bt_off_fm_off[] = {
4948 { 0xF4, 0x84, 0xFF },
4949 { 0xF0, 0x04, 0xFF },
4950 { 0xE9, 0x00, 0xFF }
4951 };
4952
4953 const struct bahama_config_register v20_bt_off_fm_on[] = {
4954 { 0xF4, 0x86, 0xFF },
4955 { 0xF0, 0x06, 0xFF },
4956 { 0xE9, 0x00, 0xFF }
4957 };
4958
4959 const struct bahama_variant_register bt_bahama[2][3] = {
4960 {
4961 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4962 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
4963 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
4964 },
4965 {
4966 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4967 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
4968 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
4969 }
4970 };
4971
4972 u8 offset = 0; /* index into bahama configs */
4973
4974 on = on ? 1 : 0;
4975
4976 bahama_version = read_bahama_ver();
4977
4978 if (((int)bahama_version) < 0 ||
4979 bahama_version == VER_UNSUPPORTED) {
4980 dev_err(&msm_bt_power_device.dev,
4981 "%s: i2c failure or unsupported version: %d\n",
4982 __func__, bahama_version);
4983 return -EIO;
4984 }
4985
4986 if (bahama_version == VER_2_0) {
4987 if (marimba_get_fm_status(&config))
4988 offset = 0x01;
4989 }
4990
4991 p = bt_bahama[on][bahama_version + offset].set;
4992
4993 dev_info(&msm_bt_power_device.dev,
4994 "%s: found version %d\n", __func__, bahama_version);
4995
4996 for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
4997 u8 value = (p+i)->value;
4998 rc = marimba_write_bit_mask(&config,
4999 (p+i)->reg,
5000 &value,
5001 sizeof((p+i)->value),
5002 (p+i)->mask);
5003 if (rc < 0) {
5004 dev_err(&msm_bt_power_device.dev,
5005 "%s: reg %d write failed: %d\n",
5006 __func__, (p+i)->reg, rc);
5007 return rc;
5008 }
5009 dev_info(&msm_bt_power_device.dev,
5010 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
5011 __func__, (p+i)->reg,
5012 value, (p+i)->mask);
5013 }
5014 /* Update BT status */
5015 if (on)
5016 marimba_set_bt_status(&config, true);
5017 else
5018 marimba_set_bt_status(&config, false);
5019
5020 if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
5021 /* Disable s2 as bahama v2 uses internal LDO regulator */
5022 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5023 if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
5024 rc = vreg_disable(vregs_bt_bahama[i]);
5025 if (rc < 0) {
5026 printk(KERN_ERR
5027 "%s: vreg %s disable "
5028 "failed (%d)\n",
5029 __func__,
5030 vregs_bt_bahama_name[i], rc);
5031 return -EIO;
5032 }
5033 rc = pmapp_vreg_level_vote("BTPW",
5034 PMAPP_VREG_S2,
5035 0);
5036 if (rc < 0) {
5037 printk(KERN_ERR "%s: vreg "
5038 "level off failed (%d)\n",
5039 __func__, rc);
5040 return -EIO;
5041 }
5042 printk(KERN_INFO "%s: vreg disable & "
5043 "level off successful (%d)\n",
5044 __func__, rc);
5045 }
5046 }
5047 }
5048
5049 return 0;
5050}
5051
5052static int bluetooth_power_regulators(int on, int bahama_not_marimba)
5053{
5054 int i, rc;
5055 const char **vregs_name;
5056 struct vreg **vregs;
5057 int vregs_size;
5058
5059 if (bahama_not_marimba) {
5060 vregs_name = vregs_bt_bahama_name;
5061 vregs = vregs_bt_bahama;
5062 vregs_size = ARRAY_SIZE(vregs_bt_bahama_name);
5063 } else {
5064 vregs_name = vregs_bt_marimba_name;
5065 vregs = vregs_bt_marimba;
5066 vregs_size = ARRAY_SIZE(vregs_bt_marimba_name);
5067 }
5068
5069 for (i = 0; i < vregs_size; i++) {
5070 if (bahama_not_marimba && (bahama_version == VER_2_0) &&
5071 !on && !strcmp(vregs_bt_bahama_name[i], "s2"))
5072 continue;
5073 rc = on ? vreg_enable(vregs[i]) :
5074 vreg_disable(vregs[i]);
5075 if (rc < 0) {
5076 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
5077 __func__, vregs_name[i],
5078 on ? "enable" : "disable", rc);
5079 return -EIO;
5080 }
5081 }
5082 return 0;
5083}
5084
5085static int bluetooth_power(int on)
5086{
5087 int rc;
5088 const char *id = "BTPW";
5089
5090 int bahama_not_marimba = bahama_present();
5091
5092 if (bahama_not_marimba == -1) {
5093 printk(KERN_WARNING "%s: bahama_present: %d\n",
5094 __func__, bahama_not_marimba);
5095 return -ENODEV;
5096 }
5097
5098 if (on) {
5099 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
5100 if (rc < 0) {
5101 printk(KERN_ERR "%s: vreg level on failed (%d)\n",
5102 __func__, rc);
5103 return rc;
5104 }
5105
5106 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5107 if (rc < 0)
5108 return -EIO;
5109
5110 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5111 PMAPP_CLOCK_VOTE_ON);
5112 if (rc < 0)
5113 return -EIO;
5114
5115 if (machine_is_msm8x55_svlte_surf() ||
5116 machine_is_msm8x55_svlte_ffa()) {
5117 rc = marimba_gpio_config(1);
5118 if (rc < 0)
5119 return -EIO;
5120 }
5121
5122 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5123 if (rc < 0)
5124 return -EIO;
5125
5126 msleep(10);
5127
5128 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5129 PMAPP_CLOCK_VOTE_PIN_CTRL);
5130 if (rc < 0)
5131 return -EIO;
5132
5133 if (machine_is_msm8x55_svlte_surf() ||
5134 machine_is_msm8x55_svlte_ffa()) {
5135 rc = marimba_gpio_config(0);
5136 if (rc < 0)
5137 return -EIO;
5138 }
5139
5140 rc = msm_gpios_enable(bt_config_power_on,
5141 ARRAY_SIZE(bt_config_power_on));
5142
5143 if (rc < 0)
5144 return rc;
5145
5146 } else {
5147 rc = msm_gpios_enable(bt_config_power_off,
5148 ARRAY_SIZE(bt_config_power_off));
5149 if (rc < 0)
5150 return rc;
5151
5152 /* check for initial RFKILL block (power off) */
5153 if (platform_get_drvdata(&msm_bt_power_device) == NULL)
5154 goto out;
5155
5156 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5157 if (rc < 0)
5158 return -EIO;
5159
5160 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5161 PMAPP_CLOCK_VOTE_OFF);
5162 if (rc < 0)
5163 return -EIO;
5164
5165 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5166 if (rc < 0)
5167 return -EIO;
5168
5169 if (bahama_version == VER_1_0) {
5170 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
5171 if (rc < 0) {
5172 printk(KERN_ERR "%s: vreg level off failed "
5173 "(%d)\n", __func__, rc);
5174 return -EIO;
5175 }
5176 }
5177 }
5178
5179out:
5180 printk(KERN_DEBUG "Bluetooth power switch: %d\n", on);
5181
5182 return 0;
5183}
5184
5185static void __init bt_power_init(void)
5186{
5187 int i;
5188
5189 for (i = 0; i < ARRAY_SIZE(vregs_bt_marimba_name); i++) {
5190 vregs_bt_marimba[i] = vreg_get(NULL, vregs_bt_marimba_name[i]);
5191 if (IS_ERR(vregs_bt_marimba[i])) {
5192 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5193 __func__, vregs_bt_marimba_name[i],
5194 PTR_ERR(vregs_bt_marimba[i]));
5195 return;
5196 }
5197 }
5198
5199 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5200 vregs_bt_bahama[i] = vreg_get(NULL, vregs_bt_bahama_name[i]);
5201 if (IS_ERR(vregs_bt_bahama[i])) {
5202 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5203 __func__, vregs_bt_bahama_name[i],
5204 PTR_ERR(vregs_bt_bahama[i]));
5205 return;
5206 }
5207 }
5208
5209 msm_bt_power_device.dev.platform_data = &bluetooth_power;
5210}
5211#else
5212#define bt_power_init(x) do {} while (0)
5213#endif
5214
5215static struct msm_psy_batt_pdata msm_psy_batt_data = {
5216 .voltage_min_design = 2800,
5217 .voltage_max_design = 4300,
5218 .avail_chg_sources = AC_CHG | USB_CHG ,
5219 .batt_technology = POWER_SUPPLY_TECHNOLOGY_LION,
5220};
5221
5222static struct platform_device msm_batt_device = {
5223 .name = "msm-battery",
5224 .id = -1,
5225 .dev.platform_data = &msm_psy_batt_data,
5226};
5227
5228static char *msm_adc_fluid_device_names[] = {
5229 "LTC_ADC1",
5230 "LTC_ADC2",
5231 "LTC_ADC3",
5232};
5233
5234static char *msm_adc_surf_device_names[] = {
5235 "XO_ADC",
5236};
5237
5238static struct msm_adc_platform_data msm_adc_pdata;
5239
5240static struct platform_device msm_adc_device = {
5241 .name = "msm_adc",
5242 .id = -1,
5243 .dev = {
5244 .platform_data = &msm_adc_pdata,
5245 },
5246};
5247
5248#ifdef CONFIG_MSM_SDIO_AL
5249static struct msm_gpio mdm2ap_status = {
5250 GPIO_CFG(77, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5251 "mdm2ap_status"
5252};
5253
5254
5255static int configure_mdm2ap_status(int on)
5256{
5257 if (on)
5258 return msm_gpios_request_enable(&mdm2ap_status, 1);
5259 else {
5260 msm_gpios_disable_free(&mdm2ap_status, 1);
5261 return 0;
5262 }
5263}
5264
5265static int get_mdm2ap_status(void)
5266{
5267 return gpio_get_value(GPIO_PIN(mdm2ap_status.gpio_cfg));
5268}
5269
5270static struct sdio_al_platform_data sdio_al_pdata = {
5271 .config_mdm2ap_status = configure_mdm2ap_status,
5272 .get_mdm2ap_status = get_mdm2ap_status,
5273 .allow_sdioc_version_major_2 = 1,
5274 .peer_sdioc_version_minor = 0x0001,
5275 .peer_sdioc_version_major = 0x0003,
5276 .peer_sdioc_boot_version_minor = 0x0001,
5277 .peer_sdioc_boot_version_major = 0x0003,
5278};
5279
5280struct platform_device msm_device_sdio_al = {
5281 .name = "msm_sdio_al",
5282 .id = -1,
5283 .dev = {
5284 .platform_data = &sdio_al_pdata,
5285 },
5286};
5287
5288#endif /* CONFIG_MSM_SDIO_AL */
5289
Daniel Walker8d747cd2010-02-25 11:37:43 -08005290static struct platform_device *devices[] __initdata = {
Daniel Walker90e37c52010-05-12 14:24:15 -07005291#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005292 &msm_device_uart2,
5293#endif
Justin Paupore637a25d2011-07-14 17:11:04 -07005294#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
5295 &msm_proccomm_regulator_dev,
5296#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005297 &asoc_msm_pcm,
5298 &asoc_msm_dai0,
5299 &asoc_msm_dai1,
5300#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
5301 &asoc_msm_mvs,
5302 &asoc_mvs_dai0,
5303 &asoc_mvs_dai1,
Daniel Walker90e37c52010-05-12 14:24:15 -07005304#endif
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -07005305 &msm_device_smd,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005306 &msm_device_dmov,
5307 &smc91x_device,
5308 &smsc911x_device,
5309 &msm_device_nand,
5310#ifdef CONFIG_USB_MSM_OTG_72K
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05305311 &msm_device_otg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005312#ifdef CONFIG_USB_GADGET
5313 &msm_device_gadget_peripheral,
5314#endif
5315#endif
5316#ifdef CONFIG_USB_G_ANDROID
5317 &android_usb_device,
5318#endif
5319 &qsd_device_spi,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05305320
5321#ifdef CONFIG_MSM_SSBI
5322 &msm_device_ssbi_pmic1,
5323#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005324#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005325 &msm_device_ssbi7,
5326#endif
5327 &android_pmem_device,
5328 &msm_fb_device,
5329 &msm_migrate_pages_device,
5330 &mddi_toshiba_device,
5331 &lcdc_toshiba_panel_device,
5332#ifdef CONFIG_MSM_ROTATOR
5333 &msm_rotator_device,
5334#endif
5335 &lcdc_sharp_panel_device,
5336 &android_pmem_adsp_device,
5337 &android_pmem_audio_device,
5338 &msm_device_i2c,
5339 &msm_device_i2c_2,
5340 &msm_device_uart_dm1,
5341 &hs_device,
5342#ifdef CONFIG_MSM7KV2_AUDIO
5343 &msm_aictl_device,
5344 &msm_mi2s_device,
5345 &msm_lpa_device,
5346 &msm_aux_pcm_device,
5347#endif
5348 &msm_device_adspdec,
5349 &qup_device_i2c,
5350#if defined(CONFIG_MARIMBA_CORE) && \
5351 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5352 &msm_bt_power_device,
5353#endif
5354 &msm_kgsl_3d0,
5355 &msm_kgsl_2d0,
5356#ifdef CONFIG_MT9T013
5357 &msm_camera_sensor_mt9t013,
5358#endif
5359#ifdef CONFIG_MT9D112
5360 &msm_camera_sensor_mt9d112,
5361#endif
5362#ifdef CONFIG_WEBCAM_OV9726
5363 &msm_camera_sensor_ov9726,
5364#endif
5365#ifdef CONFIG_S5K3E2FX
5366 &msm_camera_sensor_s5k3e2fx,
5367#endif
5368#ifdef CONFIG_MT9P012
5369 &msm_camera_sensor_mt9p012,
5370#endif
5371#ifdef CONFIG_MT9E013
5372 &msm_camera_sensor_mt9e013,
5373#endif
5374#ifdef CONFIG_VX6953
5375 &msm_camera_sensor_vx6953,
5376#endif
5377#ifdef CONFIG_SN12M0PZ
5378 &msm_camera_sensor_sn12m0pz,
5379#endif
5380 &msm_device_vidc_720p,
5381#ifdef CONFIG_MSM_GEMINI
5382 &msm_gemini_device,
5383#endif
5384#ifdef CONFIG_MSM_VPE
5385 &msm_vpe_device,
5386#endif
5387#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5388 &msm_device_tsif,
5389#endif
5390#ifdef CONFIG_MSM_SDIO_AL
5391 &msm_device_sdio_al,
5392#endif
5393
5394#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5395 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5396 &qcrypto_device,
5397#endif
5398
5399#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5400 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5401 &qcedev_device,
5402#endif
5403
5404 &msm_batt_device,
5405 &msm_adc_device,
5406 &msm_ebi0_thermal,
5407 &msm_ebi1_thermal
5408};
5409
5410static struct msm_gpio msm_i2c_gpios_hw[] = {
5411 { GPIO_CFG(70, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5412 { GPIO_CFG(71, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5413};
5414
5415static struct msm_gpio msm_i2c_gpios_io[] = {
5416 { GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5417 { GPIO_CFG(71, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5418};
5419
5420static struct msm_gpio qup_i2c_gpios_io[] = {
5421 { GPIO_CFG(16, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5422 { GPIO_CFG(17, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5423};
5424static struct msm_gpio qup_i2c_gpios_hw[] = {
5425 { GPIO_CFG(16, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5426 { GPIO_CFG(17, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5427};
5428
5429static void
5430msm_i2c_gpio_config(int adap_id, int config_type)
5431{
5432 struct msm_gpio *msm_i2c_table;
5433
5434 /* Each adapter gets 2 lines from the table */
5435 if (adap_id > 0)
5436 return;
5437 if (config_type)
5438 msm_i2c_table = &msm_i2c_gpios_hw[adap_id*2];
5439 else
5440 msm_i2c_table = &msm_i2c_gpios_io[adap_id*2];
5441 msm_gpios_enable(msm_i2c_table, 2);
5442}
5443/*This needs to be enabled only for OEMS*/
5444#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5445static struct vreg *qup_vreg;
5446#endif
5447static void
5448qup_i2c_gpio_config(int adap_id, int config_type)
5449{
5450 int rc = 0;
5451 struct msm_gpio *qup_i2c_table;
5452 /* Each adapter gets 2 lines from the table */
5453 if (adap_id != 4)
5454 return;
5455 if (config_type)
5456 qup_i2c_table = qup_i2c_gpios_hw;
5457 else
5458 qup_i2c_table = qup_i2c_gpios_io;
5459 rc = msm_gpios_enable(qup_i2c_table, 2);
5460 if (rc < 0)
5461 printk(KERN_ERR "QUP GPIO enable failed: %d\n", rc);
5462 /*This needs to be enabled only for OEMS*/
5463#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5464 if (qup_vreg) {
5465 int rc = vreg_set_level(qup_vreg, 1800);
5466 if (rc) {
5467 pr_err("%s: vreg LVS1 set level failed (%d)\n",
5468 __func__, rc);
5469 }
5470 rc = vreg_enable(qup_vreg);
5471 if (rc) {
5472 pr_err("%s: vreg_enable() = %d \n",
5473 __func__, rc);
5474 }
5475 }
5476#endif
5477}
5478
5479static struct msm_i2c_platform_data msm_i2c_pdata = {
5480 .clk_freq = 100000,
5481 .pri_clk = 70,
5482 .pri_dat = 71,
5483 .rmutex = 1,
5484 .rsl_id = "D:I2C02000021",
5485 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5486};
5487
5488static void __init msm_device_i2c_init(void)
5489{
5490 if (msm_gpios_request(msm_i2c_gpios_hw, ARRAY_SIZE(msm_i2c_gpios_hw)))
5491 pr_err("failed to request I2C gpios\n");
5492
5493 msm_device_i2c.dev.platform_data = &msm_i2c_pdata;
5494}
5495
5496static struct msm_i2c_platform_data msm_i2c_2_pdata = {
5497 .clk_freq = 100000,
5498 .rmutex = 1,
5499 .rsl_id = "D:I2C02000022",
5500 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5501};
5502
5503static void __init msm_device_i2c_2_init(void)
5504{
5505 msm_device_i2c_2.dev.platform_data = &msm_i2c_2_pdata;
5506}
5507
5508static struct msm_i2c_platform_data qup_i2c_pdata = {
5509 .clk_freq = 384000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005510 .msm_i2c_config_gpio = qup_i2c_gpio_config,
5511};
5512
5513static void __init qup_device_i2c_init(void)
5514{
5515 if (msm_gpios_request(qup_i2c_gpios_hw, ARRAY_SIZE(qup_i2c_gpios_hw)))
5516 pr_err("failed to request I2C gpios\n");
5517
5518 qup_device_i2c.dev.platform_data = &qup_i2c_pdata;
5519 /*This needs to be enabled only for OEMS*/
5520#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5521 qup_vreg = vreg_get(NULL, "lvsw1");
5522 if (IS_ERR(qup_vreg)) {
5523 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
5524 __func__, PTR_ERR(qup_vreg));
5525 }
5526#endif
5527}
5528
5529#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005530static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
5531 .rsl_id = "D:CODEC_SSBI",
5532 .controller_type = MSM_SBI_CTRL_SSBI,
5533};
5534#endif
5535
Daniel Walker8d747cd2010-02-25 11:37:43 -08005536static void __init msm7x30_init_irq(void)
5537{
5538 msm_init_irq();
5539}
5540
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005541static struct msm_gpio msm_nand_ebi2_cfg_data[] = {
5542 {GPIO_CFG(86, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_cs1"},
5543 {GPIO_CFG(115, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_busy1"},
5544};
5545
5546struct vreg *vreg_s3;
5547struct vreg *vreg_mmc;
5548
5549#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
5550 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
5551 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
5552 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT))
5553
5554struct sdcc_gpio {
5555 struct msm_gpio *cfg_data;
5556 uint32_t size;
5557 struct msm_gpio *sleep_cfg_data;
5558};
5559#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
5560static struct msm_gpio sdc1_lvlshft_cfg_data[] = {
5561 {GPIO_CFG(35, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_16MA), "sdc1_lvlshft"},
5562};
5563#endif
5564static struct msm_gpio sdc1_cfg_data[] = {
5565 {GPIO_CFG(38, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc1_clk"},
5566 {GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_cmd"},
5567 {GPIO_CFG(40, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_3"},
5568 {GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_2"},
5569 {GPIO_CFG(42, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_1"},
5570 {GPIO_CFG(43, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_0"},
5571};
5572
5573static struct msm_gpio sdc2_cfg_data[] = {
5574 {GPIO_CFG(64, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc2_clk"},
5575 {GPIO_CFG(65, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_cmd"},
5576 {GPIO_CFG(66, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_3"},
5577 {GPIO_CFG(67, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_2"},
5578 {GPIO_CFG(68, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_1"},
5579 {GPIO_CFG(69, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_0"},
5580
5581#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
5582 {GPIO_CFG(115, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_4"},
5583 {GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_5"},
5584 {GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_6"},
5585 {GPIO_CFG(112, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_7"},
5586#endif
5587};
5588
5589static struct msm_gpio sdc3_cfg_data[] = {
5590 {GPIO_CFG(110, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc3_clk"},
5591 {GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_cmd"},
5592 {GPIO_CFG(116, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_3"},
5593 {GPIO_CFG(117, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_2"},
5594 {GPIO_CFG(118, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_1"},
5595 {GPIO_CFG(119, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_0"},
5596};
5597
5598static struct msm_gpio sdc3_sleep_cfg_data[] = {
5599 {GPIO_CFG(110, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5600 "sdc3_clk"},
5601 {GPIO_CFG(111, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5602 "sdc3_cmd"},
5603 {GPIO_CFG(116, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5604 "sdc3_dat_3"},
5605 {GPIO_CFG(117, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5606 "sdc3_dat_2"},
5607 {GPIO_CFG(118, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5608 "sdc3_dat_1"},
5609 {GPIO_CFG(119, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5610 "sdc3_dat_0"},
5611};
5612
5613static struct msm_gpio sdc4_cfg_data[] = {
5614 {GPIO_CFG(58, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc4_clk"},
5615 {GPIO_CFG(59, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_cmd"},
5616 {GPIO_CFG(60, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_3"},
5617 {GPIO_CFG(61, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_2"},
5618 {GPIO_CFG(62, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_1"},
5619 {GPIO_CFG(63, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_0"},
5620};
5621
5622static struct sdcc_gpio sdcc_cfg_data[] = {
5623 {
5624 .cfg_data = sdc1_cfg_data,
5625 .size = ARRAY_SIZE(sdc1_cfg_data),
5626 .sleep_cfg_data = NULL,
5627 },
5628 {
5629 .cfg_data = sdc2_cfg_data,
5630 .size = ARRAY_SIZE(sdc2_cfg_data),
5631 .sleep_cfg_data = NULL,
5632 },
5633 {
5634 .cfg_data = sdc3_cfg_data,
5635 .size = ARRAY_SIZE(sdc3_cfg_data),
5636 .sleep_cfg_data = sdc3_sleep_cfg_data,
5637 },
5638 {
5639 .cfg_data = sdc4_cfg_data,
5640 .size = ARRAY_SIZE(sdc4_cfg_data),
5641 .sleep_cfg_data = NULL,
5642 },
5643};
5644
5645struct sdcc_vreg {
5646 struct vreg *vreg_data;
5647 unsigned level;
5648};
5649
5650static struct sdcc_vreg sdcc_vreg_data[4];
5651
5652static unsigned long vreg_sts, gpio_sts;
5653
5654static uint32_t msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
5655{
5656 int rc = 0;
5657 struct sdcc_gpio *curr;
5658
5659 curr = &sdcc_cfg_data[dev_id - 1];
5660
5661 if (!(test_bit(dev_id, &gpio_sts)^enable))
5662 return rc;
5663
5664 if (enable) {
5665 set_bit(dev_id, &gpio_sts);
5666 rc = msm_gpios_request_enable(curr->cfg_data, curr->size);
5667 if (rc)
5668 printk(KERN_ERR "%s: Failed to turn on GPIOs for slot %d\n",
5669 __func__, dev_id);
5670 } else {
5671 clear_bit(dev_id, &gpio_sts);
5672 if (curr->sleep_cfg_data) {
5673 msm_gpios_enable(curr->sleep_cfg_data, curr->size);
5674 msm_gpios_free(curr->sleep_cfg_data, curr->size);
5675 } else {
5676 msm_gpios_disable_free(curr->cfg_data, curr->size);
5677 }
5678 }
5679
5680 return rc;
5681}
5682
5683static uint32_t msm_sdcc_setup_vreg(int dev_id, unsigned int enable)
5684{
5685 int rc = 0;
5686 struct sdcc_vreg *curr;
5687 static int enabled_once[] = {0, 0, 0, 0};
5688
5689 curr = &sdcc_vreg_data[dev_id - 1];
5690
5691 if (!(test_bit(dev_id, &vreg_sts)^enable))
5692 return rc;
5693
5694 if (!enable || enabled_once[dev_id - 1])
5695 return 0;
5696
5697 if (enable) {
5698 set_bit(dev_id, &vreg_sts);
5699 rc = vreg_set_level(curr->vreg_data, curr->level);
5700 if (rc) {
5701 printk(KERN_ERR "%s: vreg_set_level() = %d \n",
5702 __func__, rc);
5703 }
5704 rc = vreg_enable(curr->vreg_data);
5705 if (rc) {
5706 printk(KERN_ERR "%s: vreg_enable() = %d \n",
5707 __func__, rc);
5708 }
5709 enabled_once[dev_id - 1] = 1;
5710 } else {
5711 clear_bit(dev_id, &vreg_sts);
5712 rc = vreg_disable(curr->vreg_data);
5713 if (rc) {
5714 printk(KERN_ERR "%s: vreg_disable() = %d \n",
5715 __func__, rc);
5716 }
5717 }
5718 return rc;
5719}
5720
5721static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
5722{
5723 int rc = 0;
5724 struct platform_device *pdev;
5725
5726 pdev = container_of(dv, struct platform_device, dev);
5727 rc = msm_sdcc_setup_gpio(pdev->id, (vdd ? 1 : 0));
5728 if (rc)
5729 goto out;
5730
5731 if (pdev->id == 4) /* S3 is always ON and cannot be disabled */
5732 rc = msm_sdcc_setup_vreg(pdev->id, (vdd ? 1 : 0));
5733out:
5734 return rc;
5735}
5736
5737#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) && \
5738 defined(CONFIG_CSDIO_VENDOR_ID) && \
5739 defined(CONFIG_CSDIO_DEVICE_ID) && \
5740 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
5741
5742#define MBP_ON 1
5743#define MBP_OFF 0
5744
5745#define MBP_RESET_N \
5746 GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA)
5747#define MBP_INT0 \
5748 GPIO_CFG(46, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA)
5749
5750#define MBP_MODE_CTRL_0 \
5751 GPIO_CFG(35, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5752#define MBP_MODE_CTRL_1 \
5753 GPIO_CFG(36, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5754#define MBP_MODE_CTRL_2 \
5755 GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5756#define TSIF_EN \
5757 GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5758#define TSIF_DATA \
5759 GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5760#define TSIF_CLK \
5761 GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5762
5763static struct msm_gpio mbp_cfg_data[] = {
5764 {GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5765 "mbp_reset"},
5766 {GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5767 "mbp_io_voltage"},
5768};
5769
5770static int mbp_config_gpios_pre_init(int enable)
5771{
5772 int rc = 0;
5773
5774 if (enable) {
5775 rc = msm_gpios_request_enable(mbp_cfg_data,
5776 ARRAY_SIZE(mbp_cfg_data));
5777 if (rc) {
5778 printk(KERN_ERR
5779 "%s: Failed to turnon GPIOs for mbp chip(%d)\n",
5780 __func__, rc);
5781 }
5782 } else
5783 msm_gpios_disable_free(mbp_cfg_data, ARRAY_SIZE(mbp_cfg_data));
5784 return rc;
5785}
5786
5787static int mbp_setup_rf_vregs(int state)
5788{
5789 struct vreg *vreg_rf = NULL;
5790 struct vreg *vreg_rf_switch = NULL;
5791 int rc;
5792
5793 vreg_rf = vreg_get(NULL, "s2");
5794 if (IS_ERR(vreg_rf)) {
5795 pr_err("%s: s2 vreg get failed (%ld)",
5796 __func__, PTR_ERR(vreg_rf));
5797 return -EFAULT;
5798 }
5799 vreg_rf_switch = vreg_get(NULL, "rf");
5800 if (IS_ERR(vreg_rf_switch)) {
5801 pr_err("%s: rf vreg get failed (%ld)",
5802 __func__, PTR_ERR(vreg_rf_switch));
5803 return -EFAULT;
5804 }
5805
5806 if (state) {
5807 rc = vreg_set_level(vreg_rf, 1300);
5808 if (rc) {
5809 pr_err("%s: vreg s2 set level failed (%d)\n",
5810 __func__, rc);
5811 return rc;
5812 }
5813
5814 rc = vreg_enable(vreg_rf);
5815 if (rc) {
5816 printk(KERN_ERR "%s: vreg_enable(s2) = %d\n",
5817 __func__, rc);
5818 }
5819
5820 rc = vreg_set_level(vreg_rf_switch, 2600);
5821 if (rc) {
5822 pr_err("%s: vreg rf switch set level failed (%d)\n",
5823 __func__, rc);
5824 return rc;
5825 }
5826 rc = vreg_enable(vreg_rf_switch);
5827 if (rc) {
5828 printk(KERN_ERR "%s: vreg_enable(rf) = %d\n",
5829 __func__, rc);
5830 }
5831 } else {
5832 (void) vreg_disable(vreg_rf);
5833 (void) vreg_disable(vreg_rf_switch);
5834 }
5835 return 0;
5836}
5837
5838static int mbp_setup_vregs(int state)
5839{
5840 struct vreg *vreg_analog = NULL;
5841 struct vreg *vreg_io = NULL;
5842 int rc;
5843
5844 vreg_analog = vreg_get(NULL, "gp4");
5845 if (IS_ERR(vreg_analog)) {
5846 pr_err("%s: gp4 vreg get failed (%ld)",
5847 __func__, PTR_ERR(vreg_analog));
5848 return -EFAULT;
5849 }
5850 vreg_io = vreg_get(NULL, "s3");
5851 if (IS_ERR(vreg_io)) {
5852 pr_err("%s: s3 vreg get failed (%ld)",
5853 __func__, PTR_ERR(vreg_io));
5854 return -EFAULT;
5855 }
5856 if (state) {
5857 rc = vreg_set_level(vreg_analog, 2600);
5858 if (rc) {
5859 pr_err("%s: vreg_set_level failed (%d)",
5860 __func__, rc);
5861 }
5862 rc = vreg_enable(vreg_analog);
5863 if (rc) {
5864 pr_err("%s: analog vreg enable failed (%d)",
5865 __func__, rc);
5866 }
5867 rc = vreg_set_level(vreg_io, 1800);
5868 if (rc) {
5869 pr_err("%s: vreg_set_level failed (%d)",
5870 __func__, rc);
5871 }
5872 rc = vreg_enable(vreg_io);
5873 if (rc) {
5874 pr_err("%s: io vreg enable failed (%d)",
5875 __func__, rc);
5876 }
5877 } else {
5878 rc = vreg_disable(vreg_analog);
5879 if (rc) {
5880 pr_err("%s: analog vreg disable failed (%d)",
5881 __func__, rc);
5882 }
5883 rc = vreg_disable(vreg_io);
5884 if (rc) {
5885 pr_err("%s: io vreg disable failed (%d)",
5886 __func__, rc);
5887 }
5888 }
5889 return rc;
5890}
5891
5892static int mbp_set_tcxo_en(int enable)
5893{
5894 int rc;
5895 const char *id = "UBMC";
5896 struct vreg *vreg_analog = NULL;
5897
5898 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_A1,
5899 enable ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
5900 if (rc < 0) {
5901 printk(KERN_ERR "%s: unable to %svote for a1 clk\n",
5902 __func__, enable ? "" : "de-");
5903 return -EIO;
5904 }
5905 if (!enable) {
5906 vreg_analog = vreg_get(NULL, "gp4");
5907 if (IS_ERR(vreg_analog)) {
5908 pr_err("%s: gp4 vreg get failed (%ld)",
5909 __func__, PTR_ERR(vreg_analog));
5910 return -EFAULT;
5911 }
5912
5913 (void) vreg_disable(vreg_analog);
5914 }
5915 return rc;
5916}
5917
5918static void mbp_set_freeze_io(int state)
5919{
5920 if (state)
5921 gpio_set_value(85, 0);
5922 else
5923 gpio_set_value(85, 1);
5924}
5925
5926static int mbp_set_core_voltage_en(int enable)
5927{
5928 int rc;
5929 struct vreg *vreg_core1p2 = NULL;
5930
5931 vreg_core1p2 = vreg_get(NULL, "gp16");
5932 if (IS_ERR(vreg_core1p2)) {
5933 pr_err("%s: gp16 vreg get failed (%ld)",
5934 __func__, PTR_ERR(vreg_core1p2));
5935 return -EFAULT;
5936 }
5937 if (enable) {
5938 rc = vreg_set_level(vreg_core1p2, 1200);
5939 if (rc) {
5940 pr_err("%s: vreg_set_level failed (%d)",
5941 __func__, rc);
5942 }
5943 (void) vreg_enable(vreg_core1p2);
5944
5945 return 80;
5946 } else {
5947 gpio_set_value(85, 1);
5948 return 0;
5949 }
5950 return rc;
5951}
5952
5953static void mbp_set_reset(int state)
5954{
5955 if (state)
5956 gpio_set_value(GPIO_PIN(MBP_RESET_N), 0);
5957 else
5958 gpio_set_value(GPIO_PIN(MBP_RESET_N), 1);
5959}
5960
5961static int mbp_config_interface_mode(int state)
5962{
5963 if (state) {
5964 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_ENABLE);
5965 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_ENABLE);
5966 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_ENABLE);
5967 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_0), 0);
5968 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_1), 1);
5969 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_2), 0);
5970 } else {
5971 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_DISABLE);
5972 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_DISABLE);
5973 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_DISABLE);
5974 }
5975 return 0;
5976}
5977
5978static int mbp_setup_adc_vregs(int state)
5979{
5980 struct vreg *vreg_adc = NULL;
5981 int rc;
5982
5983 vreg_adc = vreg_get(NULL, "s4");
5984 if (IS_ERR(vreg_adc)) {
5985 pr_err("%s: s4 vreg get failed (%ld)",
5986 __func__, PTR_ERR(vreg_adc));
5987 return -EFAULT;
5988 }
5989 if (state) {
5990 rc = vreg_set_level(vreg_adc, 2200);
5991 if (rc) {
5992 pr_err("%s: vreg_set_level failed (%d)",
5993 __func__, rc);
5994 }
5995 rc = vreg_enable(vreg_adc);
5996 if (rc) {
5997 pr_err("%s: enable vreg adc failed (%d)",
5998 __func__, rc);
5999 }
6000 } else {
6001 rc = vreg_disable(vreg_adc);
6002 if (rc) {
6003 pr_err("%s: disable vreg adc failed (%d)",
6004 __func__, rc);
6005 }
6006 }
6007 return rc;
6008}
6009
6010static int mbp_power_up(void)
6011{
6012 int rc;
6013
6014 rc = mbp_config_gpios_pre_init(MBP_ON);
6015 if (rc)
6016 goto exit;
6017 pr_debug("%s: mbp_config_gpios_pre_init() done\n", __func__);
6018
6019 rc = mbp_setup_vregs(MBP_ON);
6020 if (rc)
6021 goto exit;
6022 pr_debug("%s: gp4 (2.6) and s3 (1.8) done\n", __func__);
6023
6024 rc = mbp_set_tcxo_en(MBP_ON);
6025 if (rc)
6026 goto exit;
6027 pr_debug("%s: tcxo clock done\n", __func__);
6028
6029 mbp_set_freeze_io(MBP_OFF);
6030 pr_debug("%s: set gpio 85 to 1 done\n", __func__);
6031
6032 udelay(100);
6033 mbp_set_reset(MBP_ON);
6034
6035 udelay(300);
6036 rc = mbp_config_interface_mode(MBP_ON);
6037 if (rc)
6038 goto exit;
6039 pr_debug("%s: mbp_config_interface_mode() done\n", __func__);
6040
6041 udelay(100 + mbp_set_core_voltage_en(MBP_ON));
6042 pr_debug("%s: power gp16 1.2V done\n", __func__);
6043
6044 mbp_set_freeze_io(MBP_ON);
6045 pr_debug("%s: set gpio 85 to 0 done\n", __func__);
6046
6047 udelay(100);
6048
6049 rc = mbp_setup_rf_vregs(MBP_ON);
6050 if (rc)
6051 goto exit;
6052 pr_debug("%s: s2 1.3V and rf 2.6V done\n", __func__);
6053
6054 rc = mbp_setup_adc_vregs(MBP_ON);
6055 if (rc)
6056 goto exit;
6057 pr_debug("%s: s4 2.2V done\n", __func__);
6058
6059 udelay(200);
6060
6061 mbp_set_reset(MBP_OFF);
6062 pr_debug("%s: close gpio 44 done\n", __func__);
6063
6064 msleep(20);
6065exit:
6066 return rc;
6067}
6068
6069static int mbp_power_down(void)
6070{
6071 int rc;
6072 struct vreg *vreg_adc = NULL;
6073
6074 vreg_adc = vreg_get(NULL, "s4");
6075 if (IS_ERR(vreg_adc)) {
6076 pr_err("%s: s4 vreg get failed (%ld)",
6077 __func__, PTR_ERR(vreg_adc));
6078 return -EFAULT;
6079 }
6080
6081 mbp_set_reset(MBP_ON);
6082 pr_debug("%s: mbp_set_reset(MBP_ON) done\n", __func__);
6083
6084 udelay(100);
6085
6086 rc = mbp_setup_adc_vregs(MBP_OFF);
6087 if (rc)
6088 goto exit;
6089 pr_debug("%s: vreg_disable(vreg_adc) done\n", __func__);
6090
6091 udelay(5);
6092
6093 rc = mbp_setup_rf_vregs(MBP_OFF);
6094 if (rc)
6095 goto exit;
6096 pr_debug("%s: mbp_setup_rf_vregs(MBP_OFF) done\n", __func__);
6097
6098 udelay(5);
6099
6100 mbp_set_freeze_io(MBP_OFF);
6101 pr_debug("%s: mbp_set_freeze_io(MBP_OFF) done\n", __func__);
6102
6103 udelay(100);
6104 rc = mbp_set_core_voltage_en(MBP_OFF);
6105 if (rc)
6106 goto exit;
6107 pr_debug("%s: mbp_set_core_voltage_en(MBP_OFF) done\n", __func__);
6108
6109 gpio_set_value(85, 1);
6110
6111 rc = mbp_set_tcxo_en(MBP_OFF);
6112 if (rc)
6113 goto exit;
6114 pr_debug("%s: mbp_set_tcxo_en(MBP_OFF) done\n", __func__);
6115
6116 rc = mbp_config_gpios_pre_init(MBP_OFF);
6117 if (rc)
6118 goto exit;
6119exit:
6120 return rc;
6121}
6122
6123static void (*mbp_status_notify_cb)(int card_present, void *dev_id);
6124static void *mbp_status_notify_cb_devid;
6125static int mbp_power_status;
6126static int mbp_power_init_done;
6127
6128static uint32_t mbp_setup_power(struct device *dv,
6129 unsigned int power_status)
6130{
6131 int rc = 0;
6132 struct platform_device *pdev;
6133
6134 pdev = container_of(dv, struct platform_device, dev);
6135
6136 if (power_status == mbp_power_status)
6137 goto exit;
6138 if (power_status) {
6139 pr_debug("turn on power of mbp slot");
6140 rc = mbp_power_up();
6141 mbp_power_status = 1;
6142 } else {
6143 pr_debug("turn off power of mbp slot");
6144 rc = mbp_power_down();
6145 mbp_power_status = 0;
6146 }
6147exit:
6148 return rc;
6149};
6150
6151int mbp_register_status_notify(void (*callback)(int, void *),
6152 void *dev_id)
6153{
6154 mbp_status_notify_cb = callback;
6155 mbp_status_notify_cb_devid = dev_id;
6156 return 0;
6157}
6158
6159static unsigned int mbp_status(struct device *dev)
6160{
6161 return mbp_power_status;
6162}
6163
6164static uint32_t msm_sdcc_setup_power_mbp(struct device *dv, unsigned int vdd)
6165{
6166 struct platform_device *pdev;
6167 uint32_t rc = 0;
6168
6169 pdev = container_of(dv, struct platform_device, dev);
6170 rc = msm_sdcc_setup_power(dv, vdd);
6171 if (rc) {
6172 pr_err("%s: Failed to setup power (%d)\n",
6173 __func__, rc);
6174 goto out;
6175 }
6176 if (!mbp_power_init_done) {
6177 mbp_setup_power(dv, 1);
6178 mbp_setup_power(dv, 0);
6179 mbp_power_init_done = 1;
6180 }
6181 if (vdd >= 0x8000) {
6182 rc = mbp_setup_power(dv, (0x8000 == vdd) ? 0 : 1);
6183 if (rc) {
6184 pr_err("%s: Failed to config mbp chip power (%d)\n",
6185 __func__, rc);
6186 goto out;
6187 }
6188 if (mbp_status_notify_cb) {
6189 mbp_status_notify_cb(mbp_power_status,
6190 mbp_status_notify_cb_devid);
6191 }
6192 }
6193out:
6194 /* should return 0 only */
6195 return 0;
6196}
6197
6198#endif
6199
6200#endif
6201
6202#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6203#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6204static unsigned int msm7x30_sdcc_slot_status(struct device *dev)
6205{
6206 return (unsigned int)
6207 gpio_get_value_cansleep(
6208 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SD_DET - 1));
6209}
6210#endif
6211
6212static int msm_sdcc_get_wpswitch(struct device *dv)
6213{
6214 void __iomem *wp_addr = 0;
6215 uint32_t ret = 0;
6216 struct platform_device *pdev;
6217
6218 if (!(machine_is_msm7x30_surf()))
6219 return -1;
6220 pdev = container_of(dv, struct platform_device, dev);
6221
6222 wp_addr = ioremap(FPGA_SDCC_STATUS, 4);
6223 if (!wp_addr) {
6224 pr_err("%s: Could not remap %x\n", __func__, FPGA_SDCC_STATUS);
6225 return -ENOMEM;
6226 }
6227
6228 ret = (((readl(wp_addr) >> 4) >> (pdev->id-1)) & 0x01);
6229 pr_info("%s: WP Status for Slot %d = 0x%x \n", __func__,
6230 pdev->id, ret);
6231 iounmap(wp_addr);
6232
6233 return ret;
6234}
6235#endif
6236
6237#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
6238#if defined(CONFIG_CSDIO_VENDOR_ID) && \
6239 defined(CONFIG_CSDIO_DEVICE_ID) && \
6240 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
6241static struct mmc_platform_data msm7x30_sdc1_data = {
6242 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29,
6243 .translate_vdd = msm_sdcc_setup_power_mbp,
6244 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6245 .status = mbp_status,
6246 .register_status_notify = mbp_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006247 .msmsdcc_fmin = 144000,
6248 .msmsdcc_fmid = 24576000,
6249 .msmsdcc_fmax = 24576000,
6250 .nonremovable = 0,
6251};
6252#else
6253static struct mmc_platform_data msm7x30_sdc1_data = {
6254 .ocr_mask = MMC_VDD_165_195,
6255 .translate_vdd = msm_sdcc_setup_power,
6256 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006257 .msmsdcc_fmin = 144000,
6258 .msmsdcc_fmid = 24576000,
6259 .msmsdcc_fmax = 49152000,
6260 .nonremovable = 0,
6261};
6262#endif
6263#endif
6264
6265#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6266static struct mmc_platform_data msm7x30_sdc2_data = {
6267 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28,
6268 .translate_vdd = msm_sdcc_setup_power,
6269#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
6270 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
6271#else
6272 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6273#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006274 .msmsdcc_fmin = 144000,
6275 .msmsdcc_fmid = 24576000,
6276 .msmsdcc_fmax = 49152000,
6277 .nonremovable = 1,
6278};
6279#endif
6280
6281#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6282static struct mmc_platform_data msm7x30_sdc3_data = {
6283 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6284 .translate_vdd = msm_sdcc_setup_power,
6285 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6286#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
6287 .sdiowakeup_irq = MSM_GPIO_TO_INT(118),
6288#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006289 .msmsdcc_fmin = 144000,
6290 .msmsdcc_fmid = 24576000,
6291 .msmsdcc_fmax = 49152000,
6292 .nonremovable = 0,
6293};
6294#endif
6295
6296#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6297static struct mmc_platform_data msm7x30_sdc4_data = {
6298 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6299 .translate_vdd = msm_sdcc_setup_power,
6300 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6301#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6302 .status = msm7x30_sdcc_slot_status,
6303 .status_irq = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, PMIC_GPIO_SD_DET - 1),
6304 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
6305#endif
6306 .wpswitch = msm_sdcc_get_wpswitch,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006307 .msmsdcc_fmin = 144000,
6308 .msmsdcc_fmid = 24576000,
6309 .msmsdcc_fmax = 49152000,
6310 .nonremovable = 0,
6311};
6312#endif
6313
6314#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6315static void msm_sdc1_lvlshft_enable(void)
6316{
6317 int rc;
6318
6319 /* Enable LDO5, an input to the FET that powers slot 1 */
6320 rc = vreg_set_level(vreg_mmc, 2850);
6321 if (rc)
6322 printk(KERN_ERR "%s: vreg_set_level() = %d \n", __func__, rc);
6323
6324 rc = vreg_enable(vreg_mmc);
6325 if (rc)
6326 printk(KERN_ERR "%s: vreg_enable() = %d \n", __func__, rc);
6327
6328 /* Enable GPIO 35, to turn on the FET that powers slot 1 */
6329 rc = msm_gpios_request_enable(sdc1_lvlshft_cfg_data,
6330 ARRAY_SIZE(sdc1_lvlshft_cfg_data));
6331 if (rc)
6332 printk(KERN_ERR "%s: Failed to enable GPIO 35\n", __func__);
6333
6334 rc = gpio_direction_output(GPIO_PIN(sdc1_lvlshft_cfg_data[0].gpio_cfg),
6335 1);
6336 if (rc)
6337 printk(KERN_ERR "%s: Failed to turn on GPIO 35\n", __func__);
6338}
6339#endif
6340
6341static void __init msm7x30_init_mmc(void)
6342{
6343 vreg_s3 = vreg_get(NULL, "s3");
6344 if (IS_ERR(vreg_s3)) {
6345 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6346 __func__, PTR_ERR(vreg_s3));
6347 return;
6348 }
6349
6350 vreg_mmc = vreg_get(NULL, "mmc");
6351 if (IS_ERR(vreg_mmc)) {
6352 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6353 __func__, PTR_ERR(vreg_mmc));
6354 return;
6355 }
6356
6357#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6358 if (machine_is_msm7x30_fluid()) {
6359 msm7x30_sdc1_data.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29;
6360 msm_sdc1_lvlshft_enable();
6361 }
6362 sdcc_vreg_data[0].vreg_data = vreg_s3;
6363 sdcc_vreg_data[0].level = 1800;
6364 msm_add_sdcc(1, &msm7x30_sdc1_data);
6365#endif
6366#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6367 if (machine_is_msm8x55_svlte_surf())
6368 msm7x30_sdc2_data.msmsdcc_fmax = 24576000;
6369 sdcc_vreg_data[1].vreg_data = vreg_s3;
6370 sdcc_vreg_data[1].level = 1800;
6371 msm_add_sdcc(2, &msm7x30_sdc2_data);
6372#endif
6373#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6374 sdcc_vreg_data[2].vreg_data = vreg_s3;
6375 sdcc_vreg_data[2].level = 1800;
6376 msm_sdcc_setup_gpio(3, 1);
6377 msm_add_sdcc(3, &msm7x30_sdc3_data);
6378#endif
6379#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6380 sdcc_vreg_data[3].vreg_data = vreg_mmc;
6381 sdcc_vreg_data[3].level = 2850;
6382 msm_add_sdcc(4, &msm7x30_sdc4_data);
6383#endif
6384
6385}
6386
6387static void __init msm7x30_init_nand(void)
6388{
6389 char *build_id;
6390 struct flash_platform_data *plat_data;
6391
6392 build_id = socinfo_get_build_id();
6393 if (build_id == NULL) {
6394 pr_err("%s: Build ID not available from socinfo\n", __func__);
6395 return;
6396 }
6397
6398 if (build_id[8] == 'C' &&
6399 !msm_gpios_request_enable(msm_nand_ebi2_cfg_data,
6400 ARRAY_SIZE(msm_nand_ebi2_cfg_data))) {
6401 plat_data = msm_device_nand.dev.platform_data;
6402 plat_data->interleave = 1;
6403 printk(KERN_INFO "%s: Interleave mode Build ID found\n",
6404 __func__);
6405 }
6406}
6407
6408#ifdef CONFIG_SERIAL_MSM_CONSOLE
6409static struct msm_gpio uart2_config_data[] = {
6410 { GPIO_CFG(49, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_RFR"},
6411 { GPIO_CFG(50, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_CTS"},
6412 { GPIO_CFG(51, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Rx"},
6413 { GPIO_CFG(52, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Tx"},
6414};
6415
6416static void msm7x30_init_uart2(void)
6417{
6418 msm_gpios_request_enable(uart2_config_data,
6419 ARRAY_SIZE(uart2_config_data));
6420
6421}
6422#endif
6423
6424/* TSIF begin */
6425#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6426
6427#define TSIF_B_SYNC GPIO_CFG(37, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6428#define TSIF_B_DATA GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6429#define TSIF_B_EN GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6430#define TSIF_B_CLK GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6431
6432static const struct msm_gpio tsif_gpios[] = {
6433 { .gpio_cfg = TSIF_B_CLK, .label = "tsif_clk", },
6434 { .gpio_cfg = TSIF_B_EN, .label = "tsif_en", },
6435 { .gpio_cfg = TSIF_B_DATA, .label = "tsif_data", },
6436 { .gpio_cfg = TSIF_B_SYNC, .label = "tsif_sync", },
6437};
6438
6439static struct msm_tsif_platform_data tsif_platform_data = {
6440 .num_gpios = ARRAY_SIZE(tsif_gpios),
6441 .gpios = tsif_gpios,
Matt Wagantall640e5fd2011-08-17 16:08:53 -07006442 .tsif_pclk = "iface_clk",
6443 .tsif_ref_clk = "ref_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006444};
6445#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
6446/* TSIF end */
6447
6448static void __init pmic8058_leds_init(void)
6449{
6450 if (machine_is_msm7x30_surf()) {
6451 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6452 = &pm8058_surf_leds_data;
6453 } else if (!machine_is_msm7x30_fluid()) {
6454 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6455 = &pm8058_ffa_leds_data;
6456 } else if (machine_is_msm7x30_fluid()) {
6457 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6458 = &pm8058_fluid_leds_data;
6459 }
6460}
6461
6462static struct msm_spm_platform_data msm_spm_data __initdata = {
6463 .reg_base_addr = MSM_SAW_BASE,
6464
6465 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
6466 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
6467 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
6468 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
6469
6470 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
6471 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
6472 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
6473
6474 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
6475 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
6476 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
6477
6478 .awake_vlevel = 0xF2,
6479 .retention_vlevel = 0xE0,
6480 .collapse_vlevel = 0x72,
6481 .retention_mid_vlevel = 0xE0,
6482 .collapse_mid_vlevel = 0xE0,
6483
6484 .vctl_timeout_us = 50,
6485};
6486
6487#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
6488 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
6489
6490#define TSC2007_TS_PEN_INT 20
6491
6492static struct msm_gpio tsc2007_config_data[] = {
6493 { GPIO_CFG(TSC2007_TS_PEN_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
6494 "tsc2007_irq" },
6495};
6496
6497static struct vreg *vreg_tsc_s3;
6498static struct vreg *vreg_tsc_s2;
6499
6500static int tsc2007_init(void)
6501{
6502 int rc;
6503
6504 vreg_tsc_s3 = vreg_get(NULL, "s3");
6505 if (IS_ERR(vreg_tsc_s3)) {
6506 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6507 __func__, PTR_ERR(vreg_tsc_s3));
6508 return -ENODEV;
6509 }
6510
6511 rc = vreg_set_level(vreg_tsc_s3, 1800);
6512 if (rc) {
6513 pr_err("%s: vreg_set_level failed \n", __func__);
6514 goto fail_vreg_set_level;
6515 }
6516
6517 rc = vreg_enable(vreg_tsc_s3);
6518 if (rc) {
6519 pr_err("%s: vreg_enable failed \n", __func__);
6520 goto fail_vreg_set_level;
6521 }
6522
6523 vreg_tsc_s2 = vreg_get(NULL, "s2");
6524 if (IS_ERR(vreg_tsc_s2)) {
6525 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6526 __func__, PTR_ERR(vreg_tsc_s2));
6527 goto fail_vreg_get;
6528 }
6529
6530 rc = vreg_set_level(vreg_tsc_s2, 1300);
6531 if (rc) {
6532 pr_err("%s: vreg_set_level failed \n", __func__);
6533 goto fail_vreg_s2_level;
6534 }
6535
6536 rc = vreg_enable(vreg_tsc_s2);
6537 if (rc) {
6538 pr_err("%s: vreg_enable failed \n", __func__);
6539 goto fail_vreg_s2_level;
6540 }
6541
6542 rc = msm_gpios_request_enable(tsc2007_config_data,
6543 ARRAY_SIZE(tsc2007_config_data));
6544 if (rc) {
6545 pr_err("%s: Unable to request gpios\n", __func__);
6546 goto fail_gpio_req;
6547 }
6548
6549 return 0;
6550
6551fail_gpio_req:
6552 vreg_disable(vreg_tsc_s2);
6553fail_vreg_s2_level:
6554 vreg_put(vreg_tsc_s2);
6555fail_vreg_get:
6556 vreg_disable(vreg_tsc_s3);
6557fail_vreg_set_level:
6558 vreg_put(vreg_tsc_s3);
6559 return rc;
6560}
6561
6562static int tsc2007_get_pendown_state(void)
6563{
6564 int rc;
6565
6566 rc = gpio_get_value(TSC2007_TS_PEN_INT);
6567 if (rc < 0) {
6568 pr_err("%s: MSM GPIO %d read failed\n", __func__,
6569 TSC2007_TS_PEN_INT);
6570 return rc;
6571 }
6572
6573 return (rc == 0 ? 1 : 0);
6574}
6575
6576static void tsc2007_exit(void)
6577{
6578 vreg_disable(vreg_tsc_s3);
6579 vreg_put(vreg_tsc_s3);
6580 vreg_disable(vreg_tsc_s2);
6581 vreg_put(vreg_tsc_s2);
6582
6583 msm_gpios_disable_free(tsc2007_config_data,
6584 ARRAY_SIZE(tsc2007_config_data));
6585}
6586
6587static int tsc2007_power_shutdown(bool enable)
6588{
6589 int rc;
6590
6591 if (enable == false) {
6592 rc = vreg_enable(vreg_tsc_s2);
6593 if (rc) {
6594 pr_err("%s: vreg_enable failed\n", __func__);
6595 return rc;
6596 }
6597 rc = vreg_enable(vreg_tsc_s3);
6598 if (rc) {
6599 pr_err("%s: vreg_enable failed\n", __func__);
6600 vreg_disable(vreg_tsc_s2);
6601 return rc;
6602 }
6603 /* Voltage settling delay */
6604 msleep(20);
6605 } else {
6606 rc = vreg_disable(vreg_tsc_s2);
6607 if (rc) {
6608 pr_err("%s: vreg_disable failed\n", __func__);
6609 return rc;
6610 }
6611 rc = vreg_disable(vreg_tsc_s3);
6612 if (rc) {
6613 pr_err("%s: vreg_disable failed\n", __func__);
6614 vreg_enable(vreg_tsc_s2);
6615 return rc;
6616 }
6617 }
6618
6619 return rc;
6620}
6621
6622static struct tsc2007_platform_data tsc2007_ts_data = {
6623 .model = 2007,
6624 .x_plate_ohms = 300,
6625 .irq_flags = IRQF_TRIGGER_LOW,
6626 .init_platform_hw = tsc2007_init,
6627 .exit_platform_hw = tsc2007_exit,
6628 .power_shutdown = tsc2007_power_shutdown,
6629 .invert_x = true,
6630 .invert_y = true,
6631 /* REVISIT: Temporary fix for reversed pressure */
6632 .invert_z1 = true,
6633 .invert_z2 = true,
6634 .get_pendown_state = tsc2007_get_pendown_state,
6635};
6636
6637static struct i2c_board_info tsc_i2c_board_info[] = {
6638 {
6639 I2C_BOARD_INFO("tsc2007", 0x48),
6640 .irq = MSM_GPIO_TO_INT(TSC2007_TS_PEN_INT),
6641 .platform_data = &tsc2007_ts_data,
6642 },
6643};
6644#endif
6645
6646static const char *vregs_isa1200_name[] = {
6647 "gp7",
6648 "gp10",
6649};
6650
6651static const int vregs_isa1200_val[] = {
6652 1800,
6653 2600,
6654};
6655static struct vreg *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
6656
6657static int isa1200_power(int vreg_on)
6658{
6659 int i, rc = 0;
6660
6661 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6662 if (!vregs_isa1200[i]) {
6663 pr_err("%s: vreg_get %s failed (%d)\n",
6664 __func__, vregs_isa1200_name[i], rc);
6665 goto vreg_fail;
6666 }
6667
6668 rc = vreg_on ? vreg_enable(vregs_isa1200[i]) :
6669 vreg_disable(vregs_isa1200[i]);
6670 if (rc < 0) {
6671 pr_err("%s: vreg %s %s failed (%d)\n",
6672 __func__, vregs_isa1200_name[i],
6673 vreg_on ? "enable" : "disable", rc);
6674 goto vreg_fail;
6675 }
6676 }
6677
6678 /* vote for DO buffer */
6679 rc = pmapp_clock_vote("VIBR", PMAPP_CLOCK_ID_DO,
6680 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
6681 if (rc) {
6682 pr_err("%s: unable to %svote for d0 clk\n",
6683 __func__, vreg_on ? "" : "de-");
6684 goto vreg_fail;
6685 }
6686
6687 return 0;
6688
6689vreg_fail:
6690 while (i)
6691 vreg_disable(vregs_isa1200[--i]);
6692 return rc;
6693}
6694
6695static int isa1200_dev_setup(bool enable)
6696{
6697 int i, rc;
6698
6699 if (enable == true) {
6700 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6701 vregs_isa1200[i] = vreg_get(NULL,
6702 vregs_isa1200_name[i]);
6703 if (IS_ERR(vregs_isa1200[i])) {
6704 pr_err("%s: vreg get %s failed (%ld)\n",
6705 __func__, vregs_isa1200_name[i],
6706 PTR_ERR(vregs_isa1200[i]));
6707 rc = PTR_ERR(vregs_isa1200[i]);
6708 goto vreg_get_fail;
6709 }
6710 rc = vreg_set_level(vregs_isa1200[i],
6711 vregs_isa1200_val[i]);
6712 if (rc) {
6713 pr_err("%s: vreg_set_level() = %d\n",
6714 __func__, rc);
6715 goto vreg_get_fail;
6716 }
6717 }
6718
6719 rc = gpio_tlmm_config(GPIO_CFG(HAP_LVL_SHFT_MSM_GPIO, 0,
6720 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL,
6721 GPIO_CFG_2MA), GPIO_CFG_ENABLE);
6722 if (rc) {
6723 pr_err("%s: Could not configure gpio %d\n",
6724 __func__, HAP_LVL_SHFT_MSM_GPIO);
6725 goto vreg_get_fail;
6726 }
6727
6728 rc = gpio_request(HAP_LVL_SHFT_MSM_GPIO, "haptics_shft_lvl_oe");
6729 if (rc) {
6730 pr_err("%s: unable to request gpio %d (%d)\n",
6731 __func__, HAP_LVL_SHFT_MSM_GPIO, rc);
6732 goto vreg_get_fail;
6733 }
6734
6735 gpio_set_value(HAP_LVL_SHFT_MSM_GPIO, 1);
6736 } else {
6737 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
6738 vreg_put(vregs_isa1200[i]);
6739
6740 gpio_free(HAP_LVL_SHFT_MSM_GPIO);
6741 }
6742
6743 return 0;
6744vreg_get_fail:
6745 while (i)
6746 vreg_put(vregs_isa1200[--i]);
6747 return rc;
6748}
6749static struct isa1200_platform_data isa1200_1_pdata = {
6750 .name = "vibrator",
6751 .power_on = isa1200_power,
6752 .dev_setup = isa1200_dev_setup,
6753 .pwm_ch_id = 1, /*channel id*/
6754 /*gpio to enable haptic*/
6755 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
Mohan Pallaka03122322011-09-09 15:15:43 +05306756 .hap_len_gpio = -1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006757 .max_timeout = 15000,
6758 .mode_ctrl = PWM_GEN_MODE,
6759 .pwm_fd = {
6760 .pwm_div = 256,
6761 },
6762 .is_erm = false,
6763 .smart_en = true,
6764 .ext_clk_en = true,
6765 .chip_en = 1,
6766};
6767
6768static struct i2c_board_info msm_isa1200_board_info[] = {
6769 {
6770 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
6771 .platform_data = &isa1200_1_pdata,
6772 },
6773};
6774
6775
6776static int kp_flip_mpp_config(void)
6777{
6778 return pm8058_mpp_config_digital_in(PM_FLIP_MPP,
6779 PM8058_MPP_DIG_LEVEL_S3, PM_MPP_DIN_TO_INT);
6780}
6781
6782static struct flip_switch_pdata flip_switch_data = {
6783 .name = "kp_flip_switch",
6784 .flip_gpio = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS) + PM_FLIP_MPP,
6785 .left_key = KEY_OPEN,
6786 .right_key = KEY_CLOSE,
6787 .active_low = 0,
6788 .wakeup = 1,
6789 .flip_mpp_config = kp_flip_mpp_config,
6790};
6791
6792static struct platform_device flip_switch_device = {
6793 .name = "kp_flip_switch",
6794 .id = -1,
6795 .dev = {
6796 .platform_data = &flip_switch_data,
6797 }
6798};
6799
6800static const char *vregs_tma300_name[] = {
6801 "gp6",
6802 "gp7",
6803};
6804
6805static const int vregs_tma300_val[] = {
6806 3050,
6807 1800,
6808};
6809static struct vreg *vregs_tma300[ARRAY_SIZE(vregs_tma300_name)];
6810
6811static int tma300_power(int vreg_on)
6812{
6813 int i, rc = -EINVAL;
6814
6815 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6816 /* Never disable gp6 for fluid as lcd has a problem with it */
6817 if (!i && !vreg_on)
6818 continue;
6819 if (!vregs_tma300[i]) {
6820 printk(KERN_ERR "%s: vreg_get %s failed (%d)\n",
6821 __func__, vregs_tma300_name[i], rc);
6822 return rc;
6823 }
6824
6825 rc = vreg_on ? vreg_enable(vregs_tma300[i]) :
6826 vreg_disable(vregs_tma300[i]);
6827 if (rc < 0) {
6828 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
6829 __func__, vregs_tma300_name[i],
6830 vreg_on ? "enable" : "disable", rc);
6831 return rc;
6832 }
6833 }
6834
6835 return 0;
6836}
6837
6838#define TS_GPIO_IRQ 150
6839
6840static int tma300_dev_setup(bool enable)
6841{
6842 int i, rc;
6843
6844 if (enable) {
6845 /* get voltage sources */
6846 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6847 vregs_tma300[i] = vreg_get(NULL, vregs_tma300_name[i]);
6848 if (IS_ERR(vregs_tma300[i])) {
6849 pr_err("%s: vreg get %s failed (%ld)\n",
6850 __func__, vregs_tma300_name[i],
6851 PTR_ERR(vregs_tma300[i]));
6852 rc = PTR_ERR(vregs_tma300[i]);
6853 goto vreg_get_fail;
6854 }
6855 rc = vreg_set_level(vregs_tma300[i],
6856 vregs_tma300_val[i]);
6857 if (rc) {
6858 pr_err("%s: vreg_set_level() = %d\n",
6859 __func__, rc);
6860 i++;
6861 goto vreg_get_fail;
6862 }
6863 }
6864
6865 /* enable interrupt gpio */
6866 rc = gpio_tlmm_config(GPIO_CFG(TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
6867 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
6868 if (rc) {
6869 pr_err("%s: Could not configure gpio %d\n",
6870 __func__, TS_GPIO_IRQ);
6871 goto vreg_get_fail;
6872 }
6873
6874 /* virtual keys */
6875 tma300_vkeys_attr.attr.name = "virtualkeys.msm_tma300_ts";
6876 properties_kobj = kobject_create_and_add("board_properties",
6877 NULL);
6878 if (!properties_kobj) {
6879 pr_err("%s: failed to create a kobject"
6880 "for board_properites\n", __func__);
6881 rc = -ENOMEM;
6882 goto vreg_get_fail;
6883 }
6884 rc = sysfs_create_group(properties_kobj,
6885 &tma300_properties_attr_group);
6886 if (rc) {
6887 pr_err("%s: failed to create a sysfs entry %s\n",
6888 __func__, tma300_vkeys_attr.attr.name);
6889 kobject_put(properties_kobj);
6890 goto vreg_get_fail;
6891 }
6892 } else {
6893 /* put voltage sources */
6894 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++)
6895 vreg_put(vregs_tma300[i]);
6896 /* destroy virtual keys */
6897 if (properties_kobj) {
6898 sysfs_remove_group(properties_kobj,
6899 &tma300_properties_attr_group);
6900 kobject_put(properties_kobj);
6901 }
6902 }
6903 return 0;
6904
6905vreg_get_fail:
6906 while (i)
6907 vreg_put(vregs_tma300[--i]);
6908 return rc;
6909}
6910
6911static struct cy8c_ts_platform_data cy8ctma300_pdata = {
6912 .power_on = tma300_power,
6913 .dev_setup = tma300_dev_setup,
6914 .ts_name = "msm_tma300_ts",
6915 .dis_min_x = 0,
6916 .dis_max_x = 479,
6917 .dis_min_y = 0,
6918 .dis_max_y = 799,
6919 .res_x = 479,
6920 .res_y = 1009,
6921 .min_tid = 1,
6922 .max_tid = 255,
6923 .min_touch = 0,
6924 .max_touch = 255,
6925 .min_width = 0,
6926 .max_width = 255,
6927 .invert_y = 1,
6928 .nfingers = 4,
6929 .irq_gpio = TS_GPIO_IRQ,
6930 .resout_gpio = -1,
6931};
6932
6933static struct i2c_board_info cy8ctma300_board_info[] = {
6934 {
6935 I2C_BOARD_INFO("cy8ctma300", 0x2),
6936 .platform_data = &cy8ctma300_pdata,
6937 }
6938};
6939
Daniel Walker8d747cd2010-02-25 11:37:43 -08006940static void __init msm7x30_init(void)
6941{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006942 int rc;
6943 unsigned smem_size;
6944 uint32_t usb_hub_gpio_cfg_value = GPIO_CFG(56,
6945 0,
6946 GPIO_CFG_OUTPUT,
6947 GPIO_CFG_NO_PULL,
6948 GPIO_CFG_2MA);
6949 uint32_t soc_version = 0;
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05306950
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006951 soc_version = socinfo_get_version();
6952
Stephen Boydbb600ae2011-08-02 20:11:40 -07006953 msm_clock_init(&msm7x30_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006954#ifdef CONFIG_SERIAL_MSM_CONSOLE
6955 msm7x30_init_uart2();
6956#endif
6957 msm_spm_init(&msm_spm_data, 1);
Matt Wagantallec57f062011-08-16 23:54:46 -07006958 acpuclk_init(&acpuclk_7x30_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006959 if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
6960 msm7x30_cfg_smsc911x();
6961
6962#ifdef CONFIG_USB_MSM_OTG_72K
6963 if (SOCINFO_VERSION_MAJOR(soc_version) >= 2 &&
6964 SOCINFO_VERSION_MINOR(soc_version) >= 1) {
6965 pr_debug("%s: SOC Version:2.(1 or more)\n", __func__);
6966 msm_otg_pdata.ldo_set_voltage = 0;
6967 }
6968
6969 msm_device_otg.dev.platform_data = &msm_otg_pdata;
6970#ifdef CONFIG_USB_GADGET
6971 msm_otg_pdata.swfi_latency =
6972 msm_pm_data
6973 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
6974 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
6975#endif
6976#endif
6977 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(136);
6978 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
6979#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6980 msm_device_tsif.dev.platform_data = &tsif_platform_data;
6981#endif
6982 if (machine_is_msm7x30_fluid()) {
6983 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
6984 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
6985 } else {
6986 msm_adc_pdata.dev_names = msm_adc_surf_device_names;
6987 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
6988 }
6989
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306990#ifdef CONFIG_MSM_SSBI
6991 msm_device_ssbi_pmic1.dev.platform_data =
6992 &msm7x30_ssbi_pm8058_pdata;
6993#endif
6994
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006995 platform_add_devices(msm_footswitch_devices,
6996 msm_num_footswitch_devices);
Daniel Walker8d747cd2010-02-25 11:37:43 -08006997 platform_add_devices(devices, ARRAY_SIZE(devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006998#ifdef CONFIG_USB_EHCI_MSM_72K
6999 msm_add_host(0, &msm_usb_host_pdata);
7000#endif
7001 msm7x30_init_mmc();
7002 msm7x30_init_nand();
7003 msm_qsd_spi_init();
7004
7005#ifdef CONFIG_SPI_QSD
7006 if (machine_is_msm7x30_fluid())
7007 spi_register_board_info(lcdc_sharp_spi_board_info,
7008 ARRAY_SIZE(lcdc_sharp_spi_board_info));
7009 else
7010 spi_register_board_info(lcdc_toshiba_spi_board_info,
7011 ARRAY_SIZE(lcdc_toshiba_spi_board_info));
7012#endif
7013
7014 msm_fb_add_devices();
7015 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -06007016 BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
7017 (uint32_t *)PAGE_OFFSET));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007018 msm_device_i2c_init();
7019 msm_device_i2c_2_init();
7020 qup_device_i2c_init();
7021 buses_init();
7022 msm7x30_init_marimba();
7023#ifdef CONFIG_MSM7KV2_AUDIO
7024 snddev_poweramp_gpio_init();
7025 aux_pcm_gpio_init();
7026#endif
7027
7028 i2c_register_board_info(0, msm_i2c_board_info,
7029 ARRAY_SIZE(msm_i2c_board_info));
7030
7031 if (!machine_is_msm8x55_svlte_ffa() && !machine_is_msm7x30_fluid())
7032 marimba_pdata.tsadc = &marimba_tsadc_pdata;
7033
7034 if (machine_is_msm7x30_fluid())
7035 i2c_register_board_info(0, cy8info,
7036 ARRAY_SIZE(cy8info));
7037#ifdef CONFIG_BOSCH_BMA150
7038 if (machine_is_msm7x30_fluid())
7039 i2c_register_board_info(0, bma150_board_info,
7040 ARRAY_SIZE(bma150_board_info));
7041#endif
7042
7043 i2c_register_board_info(2, msm_marimba_board_info,
7044 ARRAY_SIZE(msm_marimba_board_info));
7045
7046 i2c_register_board_info(2, msm_i2c_gsbi7_timpani_info,
7047 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info));
7048
7049 i2c_register_board_info(4 /* QUP ID */, msm_camera_boardinfo,
7050 ARRAY_SIZE(msm_camera_boardinfo));
7051
7052 bt_power_init();
7053#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007054 msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
7055#endif
7056 if (machine_is_msm7x30_fluid())
7057 i2c_register_board_info(0, msm_isa1200_board_info,
7058 ARRAY_SIZE(msm_isa1200_board_info));
7059
7060#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
7061 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
7062 if (machine_is_msm8x55_svlte_ffa())
7063 i2c_register_board_info(2, tsc_i2c_board_info,
7064 ARRAY_SIZE(tsc_i2c_board_info));
7065#endif
7066
7067 if (machine_is_msm7x30_surf())
7068 platform_device_register(&flip_switch_device);
7069 pmic8058_leds_init();
7070
7071 if (machine_is_msm7x30_fluid()) {
7072 /* Initialize platform data for fluid v2 hardware */
7073 if (SOCINFO_VERSION_MAJOR(
7074 socinfo_get_platform_version()) == 2) {
7075 cy8ctma300_pdata.res_y = 920;
7076 cy8ctma300_pdata.invert_y = 0;
7077 }
7078 i2c_register_board_info(0, cy8ctma300_board_info,
7079 ARRAY_SIZE(cy8ctma300_board_info));
7080 }
7081
7082 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
7083 rc = gpio_tlmm_config(usb_hub_gpio_cfg_value, GPIO_CFG_ENABLE);
7084 if (rc)
7085 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
7086 __func__, usb_hub_gpio_cfg_value, rc);
7087 }
7088
7089 boot_reason = *(unsigned int *)
7090 (smem_get_entry(SMEM_POWER_ON_STATUS_INFO, &smem_size));
7091 printk(KERN_NOTICE "Boot Reason = 0x%02x\n", boot_reason);
7092}
7093
7094static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
7095static int __init pmem_sf_size_setup(char *p)
7096{
7097 pmem_sf_size = memparse(p, NULL);
7098 return 0;
7099}
7100early_param("pmem_sf_size", pmem_sf_size_setup);
7101
7102static unsigned fb_size = MSM_FB_SIZE;
7103static int __init fb_size_setup(char *p)
7104{
7105 fb_size = memparse(p, NULL);
7106 return 0;
7107}
7108early_param("fb_size", fb_size_setup);
7109
7110static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
7111static int __init pmem_adsp_size_setup(char *p)
7112{
7113 pmem_adsp_size = memparse(p, NULL);
7114 return 0;
7115}
7116early_param("pmem_adsp_size", pmem_adsp_size_setup);
7117
7118static unsigned fluid_pmem_adsp_size = MSM_FLUID_PMEM_ADSP_SIZE;
7119static int __init fluid_pmem_adsp_size_setup(char *p)
7120{
7121 fluid_pmem_adsp_size = memparse(p, NULL);
7122 return 0;
7123}
7124early_param("fluid_pmem_adsp_size", fluid_pmem_adsp_size_setup);
7125
7126static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
7127static int __init pmem_audio_size_setup(char *p)
7128{
7129 pmem_audio_size = memparse(p, NULL);
7130 return 0;
7131}
7132early_param("pmem_audio_size", pmem_audio_size_setup);
7133
7134static unsigned pmem_kernel_ebi0_size = PMEM_KERNEL_EBI0_SIZE;
7135static int __init pmem_kernel_ebi0_size_setup(char *p)
7136{
7137 pmem_kernel_ebi0_size = memparse(p, NULL);
7138 return 0;
7139}
7140early_param("pmem_kernel_ebi0_size", pmem_kernel_ebi0_size_setup);
7141
7142static struct memtype_reserve msm7x30_reserve_table[] __initdata = {
7143 [MEMTYPE_SMI] = {
7144 },
7145 [MEMTYPE_EBI0] = {
7146 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7147 },
7148 [MEMTYPE_EBI1] = {
7149 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7150 },
7151};
7152
7153static void __init size_pmem_devices(void)
7154{
7155#ifdef CONFIG_ANDROID_PMEM
7156 unsigned long size;
7157
7158 if machine_is_msm7x30_fluid()
7159 size = fluid_pmem_adsp_size;
7160 else
7161 size = pmem_adsp_size;
7162 android_pmem_adsp_pdata.size = size;
7163 android_pmem_audio_pdata.size = pmem_audio_size;
7164 android_pmem_pdata.size = pmem_sf_size;
7165#endif
7166}
7167
7168static void __init reserve_memory_for(struct android_pmem_platform_data *p)
7169{
7170 msm7x30_reserve_table[p->memory_type].size += p->size;
7171}
7172
7173static void __init reserve_pmem_memory(void)
7174{
7175#ifdef CONFIG_ANDROID_PMEM
7176 reserve_memory_for(&android_pmem_adsp_pdata);
7177 reserve_memory_for(&android_pmem_audio_pdata);
7178 reserve_memory_for(&android_pmem_pdata);
7179 msm7x30_reserve_table[MEMTYPE_EBI0].size += pmem_kernel_ebi0_size;
7180#endif
7181}
7182
7183static void __init msm7x30_calculate_reserve_sizes(void)
7184{
7185 size_pmem_devices();
7186 reserve_pmem_memory();
7187}
7188
7189static int msm7x30_paddr_to_memtype(unsigned int paddr)
7190{
7191 if (paddr < 0x40000000)
7192 return MEMTYPE_EBI0;
7193 if (paddr >= 0x40000000 && paddr < 0x80000000)
7194 return MEMTYPE_EBI1;
7195 return MEMTYPE_NONE;
7196}
7197
7198static struct reserve_info msm7x30_reserve_info __initdata = {
7199 .memtype_reserve_table = msm7x30_reserve_table,
7200 .calculate_reserve_sizes = msm7x30_calculate_reserve_sizes,
7201 .paddr_to_memtype = msm7x30_paddr_to_memtype,
7202};
7203
7204static void __init msm7x30_reserve(void)
7205{
7206 reserve_info = &msm7x30_reserve_info;
7207 msm_reserve();
7208}
7209
7210static void __init msm7x30_allocate_memory_regions(void)
7211{
7212 void *addr;
7213 unsigned long size;
7214
7215 size = fb_size ? : MSM_FB_SIZE;
7216 addr = alloc_bootmem_align(size, 0x1000);
7217 msm_fb_resources[0].start = __pa(addr);
7218 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
7219 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
7220 size, addr, __pa(addr));
Daniel Walker8d747cd2010-02-25 11:37:43 -08007221}
7222
7223static void __init msm7x30_map_io(void)
7224{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007225 msm_shared_ram_phys = 0x00100000;
Daniel Walker8d747cd2010-02-25 11:37:43 -08007226 msm_map_msm7x30_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007227 if (socinfo_init() < 0)
7228 printk(KERN_ERR "%s: socinfo_init() failed!\n",
7229 __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007230}
7231
7232static void __init msm7x30_init_early(void)
7233{
7234 msm7x30_allocate_memory_regions();
Daniel Walker8d747cd2010-02-25 11:37:43 -08007235}
7236
7237MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
Russell Kingb75c1782011-01-04 19:03:16 +00007238 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007239 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007240 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007241 .init_irq = msm7x30_init_irq,
7242 .init_machine = msm7x30_init,
7243 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007244 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307245 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007246MACHINE_END
7247
7248MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
Russell Kingb75c1782011-01-04 19:03:16 +00007249 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007250 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007251 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007252 .init_irq = msm7x30_init_irq,
7253 .init_machine = msm7x30_init,
7254 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007255 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307256 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007257MACHINE_END
7258
7259MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
Russell Kingb75c1782011-01-04 19:03:16 +00007260 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007261 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007262 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007263 .init_irq = msm7x30_init_irq,
7264 .init_machine = msm7x30_init,
7265 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007266 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307267 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007268MACHINE_END
7269
7270MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
7271 .boot_params = PHYS_OFFSET + 0x100,
7272 .map_io = msm7x30_map_io,
7273 .reserve = msm7x30_reserve,
7274 .init_irq = msm7x30_init_irq,
7275 .init_machine = msm7x30_init,
7276 .timer = &msm_timer,
7277 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307278 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007279MACHINE_END
7280
7281MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
7282 .boot_params = PHYS_OFFSET + 0x100,
7283 .map_io = msm7x30_map_io,
7284 .reserve = msm7x30_reserve,
7285 .init_irq = msm7x30_init_irq,
7286 .init_machine = msm7x30_init,
7287 .timer = &msm_timer,
7288 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307289 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007290MACHINE_END
7291MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
7292 .boot_params = PHYS_OFFSET + 0x100,
7293 .map_io = msm7x30_map_io,
7294 .reserve = msm7x30_reserve,
7295 .init_irq = msm7x30_init_irq,
7296 .init_machine = msm7x30_init,
7297 .timer = &msm_timer,
7298 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307299 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007300MACHINE_END
7301MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
7302 .boot_params = PHYS_OFFSET + 0x100,
7303 .map_io = msm7x30_map_io,
7304 .reserve = msm7x30_reserve,
7305 .init_irq = msm7x30_init_irq,
7306 .init_machine = msm7x30_init,
7307 .timer = &msm_timer,
7308 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307309 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007310MACHINE_END