| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 1 | /******************************************************************************* | 
|  | 2 |  | 
|  | 3 | Intel 10 Gigabit PCI Express Linux driver | 
| Peter P Waskiewicz Jr | 3efac5a | 2009-02-01 01:19:20 -0800 | [diff] [blame] | 4 | Copyright(c) 1999 - 2009 Intel Corporation. | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 5 |  | 
|  | 6 | This program is free software; you can redistribute it and/or modify it | 
|  | 7 | under the terms and conditions of the GNU General Public License, | 
|  | 8 | version 2, as published by the Free Software Foundation. | 
|  | 9 |  | 
|  | 10 | This program is distributed in the hope it will be useful, but WITHOUT | 
|  | 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 
|  | 12 | FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for | 
|  | 13 | more details. | 
|  | 14 |  | 
|  | 15 | You should have received a copy of the GNU General Public License along with | 
|  | 16 | this program; if not, write to the Free Software Foundation, Inc., | 
|  | 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 
|  | 18 |  | 
|  | 19 | The full GNU General Public License is included in this distribution in | 
|  | 20 | the file called "COPYING". | 
|  | 21 |  | 
|  | 22 | Contact Information: | 
|  | 23 | Linux NICS <linux.nics@intel.com> | 
|  | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | 
|  | 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | 
|  | 26 |  | 
|  | 27 | *******************************************************************************/ | 
|  | 28 |  | 
|  | 29 |  | 
|  | 30 | #include "ixgbe.h" | 
|  | 31 | #include "ixgbe_type.h" | 
|  | 32 | #include "ixgbe_dcb.h" | 
|  | 33 | #include "ixgbe_dcb_82598.h" | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 34 | #include "ixgbe_dcb_82599.h" | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 35 |  | 
|  | 36 | /** | 
|  | 37 | * ixgbe_dcb_config - Struct containing DCB settings. | 
|  | 38 | * @dcb_config: Pointer to DCB config structure | 
|  | 39 | * | 
|  | 40 | * This function checks DCB rules for DCB settings. | 
|  | 41 | * The following rules are checked: | 
|  | 42 | * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%. | 
|  | 43 | * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth | 
|  | 44 | *    Group must total 100. | 
|  | 45 | * 3. A Traffic Class should not be set to both Link Strict Priority | 
|  | 46 | *    and Group Strict Priority. | 
|  | 47 | * 4. Link strict Bandwidth Groups can only have link strict traffic classes | 
|  | 48 | *    with zero bandwidth. | 
|  | 49 | */ | 
|  | 50 | s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *dcb_config) | 
|  | 51 | { | 
|  | 52 | struct tc_bw_alloc *p; | 
|  | 53 | s32 ret_val = 0; | 
|  | 54 | u8 i, j, bw = 0, bw_id; | 
|  | 55 | u8 bw_sum[2][MAX_BW_GROUP]; | 
|  | 56 | bool link_strict[2][MAX_BW_GROUP]; | 
|  | 57 |  | 
|  | 58 | memset(bw_sum, 0, sizeof(bw_sum)); | 
|  | 59 | memset(link_strict, 0, sizeof(link_strict)); | 
|  | 60 |  | 
|  | 61 | /* First Tx, then Rx */ | 
|  | 62 | for (i = 0; i < 2; i++) { | 
|  | 63 | /* Check each traffic class for rule violation */ | 
|  | 64 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | 
|  | 65 | p = &dcb_config->tc_config[j].path[i]; | 
|  | 66 |  | 
|  | 67 | bw = p->bwg_percent; | 
|  | 68 | bw_id = p->bwg_id; | 
|  | 69 |  | 
|  | 70 | if (bw_id >= MAX_BW_GROUP) { | 
|  | 71 | ret_val = DCB_ERR_CONFIG; | 
|  | 72 | goto err_config; | 
|  | 73 | } | 
|  | 74 | if (p->prio_type == prio_link) { | 
|  | 75 | link_strict[i][bw_id] = true; | 
|  | 76 | /* Link strict should have zero bandwidth */ | 
|  | 77 | if (bw) { | 
|  | 78 | ret_val = DCB_ERR_LS_BW_NONZERO; | 
|  | 79 | goto err_config; | 
|  | 80 | } | 
|  | 81 | } else if (!bw) { | 
|  | 82 | /* | 
|  | 83 | * Traffic classes without link strict | 
|  | 84 | * should have non-zero bandwidth. | 
|  | 85 | */ | 
|  | 86 | ret_val = DCB_ERR_TC_BW_ZERO; | 
|  | 87 | goto err_config; | 
|  | 88 | } | 
|  | 89 | bw_sum[i][bw_id] += bw; | 
|  | 90 | } | 
|  | 91 |  | 
|  | 92 | bw = 0; | 
|  | 93 |  | 
|  | 94 | /* Check each bandwidth group for rule violation */ | 
|  | 95 | for (j = 0; j < MAX_BW_GROUP; j++) { | 
|  | 96 | bw += dcb_config->bw_percentage[i][j]; | 
|  | 97 | /* | 
|  | 98 | * Sum of bandwidth percentages of all traffic classes | 
|  | 99 | * within a Bandwidth Group must total 100 except for | 
|  | 100 | * link strict group (zero bandwidth). | 
|  | 101 | */ | 
|  | 102 | if (link_strict[i][j]) { | 
|  | 103 | if (bw_sum[i][j]) { | 
|  | 104 | /* | 
|  | 105 | * Link strict group should have zero | 
|  | 106 | * bandwidth. | 
|  | 107 | */ | 
|  | 108 | ret_val = DCB_ERR_LS_BWG_NONZERO; | 
|  | 109 | goto err_config; | 
|  | 110 | } | 
|  | 111 | } else if (bw_sum[i][j] != BW_PERCENT && | 
|  | 112 | bw_sum[i][j] != 0) { | 
|  | 113 | ret_val = DCB_ERR_TC_BW; | 
|  | 114 | goto err_config; | 
|  | 115 | } | 
|  | 116 | } | 
|  | 117 |  | 
|  | 118 | if (bw != BW_PERCENT) { | 
|  | 119 | ret_val = DCB_ERR_BW_GROUP; | 
|  | 120 | goto err_config; | 
|  | 121 | } | 
|  | 122 | } | 
|  | 123 |  | 
|  | 124 | err_config: | 
|  | 125 | return ret_val; | 
|  | 126 | } | 
|  | 127 |  | 
|  | 128 | /** | 
|  | 129 | * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits | 
|  | 130 | * @ixgbe_dcb_config: Struct containing DCB settings. | 
|  | 131 | * @direction: Configuring either Tx or Rx. | 
|  | 132 | * | 
|  | 133 | * This function calculates the credits allocated to each traffic class. | 
|  | 134 | * It should be called only after the rules are checked by | 
|  | 135 | * ixgbe_dcb_check_config(). | 
|  | 136 | */ | 
|  | 137 | s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config, | 
|  | 138 | u8 direction) | 
|  | 139 | { | 
|  | 140 | struct tc_bw_alloc *p; | 
|  | 141 | s32 ret_val = 0; | 
|  | 142 | /* Initialization values default for Tx settings */ | 
|  | 143 | u32 credit_refill       = 0; | 
|  | 144 | u32 credit_max          = 0; | 
|  | 145 | u16 link_percentage     = 0; | 
|  | 146 | u8  bw_percent          = 0; | 
|  | 147 | u8  i; | 
|  | 148 |  | 
|  | 149 | if (dcb_config == NULL) { | 
|  | 150 | ret_val = DCB_ERR_CONFIG; | 
|  | 151 | goto out; | 
|  | 152 | } | 
|  | 153 |  | 
|  | 154 | /* Find out the link percentage for each TC first */ | 
|  | 155 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | 
|  | 156 | p = &dcb_config->tc_config[i].path[direction]; | 
|  | 157 | bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; | 
|  | 158 |  | 
|  | 159 | link_percentage = p->bwg_percent; | 
|  | 160 | /* Must be careful of integer division for very small nums */ | 
|  | 161 | link_percentage = (link_percentage * bw_percent) / 100; | 
|  | 162 | if (p->bwg_percent > 0 && link_percentage == 0) | 
|  | 163 | link_percentage = 1; | 
|  | 164 |  | 
|  | 165 | /* Save link_percentage for reference */ | 
|  | 166 | p->link_percent = (u8)link_percentage; | 
|  | 167 |  | 
|  | 168 | /* Calculate credit refill and save it */ | 
|  | 169 | credit_refill = link_percentage * MINIMUM_CREDIT_REFILL; | 
|  | 170 | p->data_credits_refill = (u16)credit_refill; | 
|  | 171 |  | 
|  | 172 | /* Calculate maximum credit for the TC */ | 
|  | 173 | credit_max = (link_percentage * MAX_CREDIT) / 100; | 
|  | 174 |  | 
|  | 175 | /* | 
|  | 176 | * Adjustment based on rule checking, if the percentage | 
|  | 177 | * of a TC is too small, the maximum credit may not be | 
|  | 178 | * enough to send out a jumbo frame in data plane arbitration. | 
|  | 179 | */ | 
|  | 180 | if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_JUMBO)) | 
|  | 181 | credit_max = MINIMUM_CREDIT_FOR_JUMBO; | 
|  | 182 |  | 
|  | 183 | if (direction == DCB_TX_CONFIG) { | 
|  | 184 | /* | 
|  | 185 | * Adjustment based on rule checking, if the | 
|  | 186 | * percentage of a TC is too small, the maximum | 
|  | 187 | * credit may not be enough to send out a TSO | 
|  | 188 | * packet in descriptor plane arbitration. | 
|  | 189 | */ | 
|  | 190 | if (credit_max && | 
|  | 191 | (credit_max < MINIMUM_CREDIT_FOR_TSO)) | 
|  | 192 | credit_max = MINIMUM_CREDIT_FOR_TSO; | 
|  | 193 |  | 
|  | 194 | dcb_config->tc_config[i].desc_credits_max = | 
|  | 195 | (u16)credit_max; | 
|  | 196 | } | 
|  | 197 |  | 
|  | 198 | p->data_credits_max = (u16)credit_max; | 
|  | 199 | } | 
|  | 200 |  | 
|  | 201 | out: | 
|  | 202 | return ret_val; | 
|  | 203 | } | 
|  | 204 |  | 
|  | 205 | /** | 
|  | 206 | * ixgbe_dcb_get_tc_stats - Returns status of each traffic class | 
|  | 207 | * @hw: pointer to hardware structure | 
|  | 208 | * @stats: pointer to statistics structure | 
|  | 209 | * @tc_count:  Number of elements in bwg_array. | 
|  | 210 | * | 
|  | 211 | * This function returns the status data for each of the Traffic Classes in use. | 
|  | 212 | */ | 
|  | 213 | s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, | 
|  | 214 | u8 tc_count) | 
|  | 215 | { | 
|  | 216 | s32 ret = 0; | 
|  | 217 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 218 | ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 219 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 220 | ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 221 | return ret; | 
|  | 222 | } | 
|  | 223 |  | 
|  | 224 | /** | 
|  | 225 | * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class | 
|  | 226 | * hw - pointer to hardware structure | 
|  | 227 | * stats - pointer to statistics structure | 
|  | 228 | * tc_count -  Number of elements in bwg_array. | 
|  | 229 | * | 
|  | 230 | * This function returns the CBFC status data for each of the Traffic Classes. | 
|  | 231 | */ | 
|  | 232 | s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, | 
|  | 233 | u8 tc_count) | 
|  | 234 | { | 
|  | 235 | s32 ret = 0; | 
|  | 236 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 237 | ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 238 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 239 | ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 240 | return ret; | 
|  | 241 | } | 
|  | 242 |  | 
|  | 243 | /** | 
|  | 244 | * ixgbe_dcb_config_rx_arbiter - Config Rx arbiter | 
|  | 245 | * @hw: pointer to hardware structure | 
|  | 246 | * @dcb_config: pointer to ixgbe_dcb_config structure | 
|  | 247 | * | 
|  | 248 | * Configure Rx Data Arbiter and credits for each traffic class. | 
|  | 249 | */ | 
|  | 250 | s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw, | 
|  | 251 | struct ixgbe_dcb_config *dcb_config) | 
|  | 252 | { | 
|  | 253 | s32 ret = 0; | 
|  | 254 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 255 | ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 256 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 257 | ret = ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 258 | return ret; | 
|  | 259 | } | 
|  | 260 |  | 
|  | 261 | /** | 
|  | 262 | * ixgbe_dcb_config_tx_desc_arbiter - Config Tx Desc arbiter | 
|  | 263 | * @hw: pointer to hardware structure | 
|  | 264 | * @dcb_config: pointer to ixgbe_dcb_config structure | 
|  | 265 | * | 
|  | 266 | * Configure Tx Descriptor Arbiter and credits for each traffic class. | 
|  | 267 | */ | 
|  | 268 | s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw, | 
|  | 269 | struct ixgbe_dcb_config *dcb_config) | 
|  | 270 | { | 
|  | 271 | s32 ret = 0; | 
|  | 272 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 273 | ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 274 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 275 | ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 276 | return ret; | 
|  | 277 | } | 
|  | 278 |  | 
|  | 279 | /** | 
|  | 280 | * ixgbe_dcb_config_tx_data_arbiter - Config Tx data arbiter | 
|  | 281 | * @hw: pointer to hardware structure | 
|  | 282 | * @dcb_config: pointer to ixgbe_dcb_config structure | 
|  | 283 | * | 
|  | 284 | * Configure Tx Data Arbiter and credits for each traffic class. | 
|  | 285 | */ | 
|  | 286 | s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw, | 
|  | 287 | struct ixgbe_dcb_config *dcb_config) | 
|  | 288 | { | 
|  | 289 | s32 ret = 0; | 
|  | 290 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 291 | ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 292 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 293 | ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 294 | return ret; | 
|  | 295 | } | 
|  | 296 |  | 
|  | 297 | /** | 
|  | 298 | * ixgbe_dcb_config_pfc - Config priority flow control | 
|  | 299 | * @hw: pointer to hardware structure | 
|  | 300 | * @dcb_config: pointer to ixgbe_dcb_config structure | 
|  | 301 | * | 
|  | 302 | * Configure Priority Flow Control for each traffic class. | 
|  | 303 | */ | 
|  | 304 | s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, | 
|  | 305 | struct ixgbe_dcb_config *dcb_config) | 
|  | 306 | { | 
|  | 307 | s32 ret = 0; | 
|  | 308 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 309 | ret = ixgbe_dcb_config_pfc_82598(hw, dcb_config); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 310 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 311 | ret = ixgbe_dcb_config_pfc_82599(hw, dcb_config); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 312 | return ret; | 
|  | 313 | } | 
|  | 314 |  | 
|  | 315 | /** | 
|  | 316 | * ixgbe_dcb_config_tc_stats - Config traffic class statistics | 
|  | 317 | * @hw: pointer to hardware structure | 
|  | 318 | * | 
|  | 319 | * Configure queue statistics registers, all queues belonging to same traffic | 
|  | 320 | * class uses a single set of queue statistics counters. | 
|  | 321 | */ | 
|  | 322 | s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw) | 
|  | 323 | { | 
|  | 324 | s32 ret = 0; | 
|  | 325 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 326 | ret = ixgbe_dcb_config_tc_stats_82598(hw); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 327 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 328 | ret = ixgbe_dcb_config_tc_stats_82599(hw); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 329 | return ret; | 
|  | 330 | } | 
|  | 331 |  | 
|  | 332 | /** | 
|  | 333 | * ixgbe_dcb_hw_config - Config and enable DCB | 
|  | 334 | * @hw: pointer to hardware structure | 
|  | 335 | * @dcb_config: pointer to ixgbe_dcb_config structure | 
|  | 336 | * | 
|  | 337 | * Configure dcb settings and enable dcb mode. | 
|  | 338 | */ | 
|  | 339 | s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, | 
|  | 340 | struct ixgbe_dcb_config *dcb_config) | 
|  | 341 | { | 
|  | 342 | s32 ret = 0; | 
|  | 343 | if (hw->mac.type == ixgbe_mac_82598EB) | 
|  | 344 | ret = ixgbe_dcb_hw_config_82598(hw, dcb_config); | 
| PJ Waskiewicz | 235ea82 | 2009-02-27 15:44:48 +0000 | [diff] [blame] | 345 | else if (hw->mac.type == ixgbe_mac_82599EB) | 
|  | 346 | ret = ixgbe_dcb_hw_config_82599(hw, dcb_config); | 
| Alexander Duyck | 2f90b86 | 2008-11-20 20:52:10 -0800 | [diff] [blame] | 347 | return ret; | 
|  | 348 | } | 
|  | 349 |  |