| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver | 
|  | 3 | * | 
|  | 4 | *   Copyright (C) 2000 Wolfgang Grandegger (wolfgang@ces.ch) | 
|  | 5 | * | 
|  | 6 | *   This program is free software; you can redistribute it and/or modify | 
|  | 7 | *   it under the terms of the GNU General Public License as published by | 
|  | 8 | *   the Free Software Foundation; either version 2 of the License, or | 
|  | 9 | *   (at your option) any later version. | 
|  | 10 | * | 
|  | 11 | * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No. | 
|  | 12 | * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin | 
|  | 13 | * Model No. U232-P9). See http://www.mct.com.tw/p_u232.html for further | 
|  | 14 | * information. The properties of this device are listed at the end of this | 
|  | 15 | * file. This device is available from various distributors. I know Hana, | 
|  | 16 | * http://www.hana.de and D-Link, http://www.dlink.com/products/usb/dsbs25. | 
|  | 17 | * | 
|  | 18 | * All of the information about the device was acquired by using SniffUSB | 
|  | 19 | * on Windows98. The technical details of the reverse engineering are | 
|  | 20 | * summarized at the end of this file. | 
|  | 21 | */ | 
|  | 22 |  | 
|  | 23 | #ifndef __LINUX_USB_SERIAL_MCT_U232_H | 
|  | 24 | #define __LINUX_USB_SERIAL_MCT_U232_H | 
|  | 25 |  | 
|  | 26 | #define MCT_U232_VID	                0x0711	/* Vendor Id */ | 
|  | 27 | #define MCT_U232_PID	                0x0210	/* Original MCT Product Id */ | 
|  | 28 |  | 
|  | 29 | /* U232-P25, Sitecom */ | 
|  | 30 | #define MCT_U232_SITECOM_PID		0x0230	/* Sitecom Product Id */ | 
|  | 31 |  | 
|  | 32 | /* DU-H3SP USB BAY hub */ | 
|  | 33 | #define MCT_U232_DU_H3SP_PID		0x0200	/* D-Link DU-H3SP USB BAY */ | 
|  | 34 |  | 
|  | 35 | /* Belkin badge the MCT U232-P9 as the F5U109 */ | 
|  | 36 | #define MCT_U232_BELKIN_F5U109_VID	0x050d	/* Vendor Id */ | 
|  | 37 | #define MCT_U232_BELKIN_F5U109_PID	0x0109	/* Product Id */ | 
|  | 38 |  | 
|  | 39 | /* | 
|  | 40 | * Vendor Request Interface | 
|  | 41 | */ | 
|  | 42 | #define MCT_U232_SET_REQUEST_TYPE	0x40 | 
|  | 43 | #define MCT_U232_GET_REQUEST_TYPE	0xc0 | 
|  | 44 |  | 
|  | 45 | #define MCT_U232_GET_MODEM_STAT_REQUEST 2  /* Get Modem Status Register (MSR) */ | 
|  | 46 | #define MCT_U232_GET_MODEM_STAT_SIZE    1 | 
|  | 47 |  | 
|  | 48 | #define MCT_U232_GET_LINE_CTRL_REQUEST  6  /* Get Line Control Register (LCR) */ | 
|  | 49 | #define MCT_U232_GET_LINE_CTRL_SIZE     1  /* ... not used by this driver */ | 
|  | 50 |  | 
|  | 51 | #define MCT_U232_SET_BAUD_RATE_REQUEST	5  /* Set Baud Rate Divisor */ | 
|  | 52 | #define MCT_U232_SET_BAUD_RATE_SIZE     4 | 
|  | 53 |  | 
|  | 54 | #define MCT_U232_SET_LINE_CTRL_REQUEST	7  /* Set Line Control Register (LCR) */ | 
|  | 55 | #define MCT_U232_SET_LINE_CTRL_SIZE     1 | 
|  | 56 |  | 
|  | 57 | #define MCT_U232_SET_MODEM_CTRL_REQUEST	10 /* Set Modem Control Register (MCR) */ | 
|  | 58 | #define MCT_U232_SET_MODEM_CTRL_SIZE    1 | 
|  | 59 |  | 
|  | 60 | /* This USB device request code is not well understood.  It is transmitted by | 
|  | 61 | the MCT-supplied Windows driver whenever the baud rate changes. | 
|  | 62 | */ | 
|  | 63 | #define MCT_U232_SET_UNKNOWN1_REQUEST   11  /* Unknown functionality */ | 
|  | 64 | #define MCT_U232_SET_UNKNOWN1_SIZE       1 | 
|  | 65 |  | 
| Dave Platt | 45b844d | 2007-05-08 11:00:12 -0700 | [diff] [blame] | 66 | /* This USB device request code appears to control whether CTS is required | 
|  | 67 | during transmission. | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 |  | 
| Dave Platt | 45b844d | 2007-05-08 11:00:12 -0700 | [diff] [blame] | 69 | Sending a zero byte allows data transmission to a device which is not | 
|  | 70 | asserting CTS.  Sending a '1' byte will cause transmission to be deferred | 
|  | 71 | until the device asserts CTS. | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | */ | 
| Dave Platt | 45b844d | 2007-05-08 11:00:12 -0700 | [diff] [blame] | 73 | #define MCT_U232_SET_CTS_REQUEST   12 | 
|  | 74 | #define MCT_U232_SET_CTS_SIZE       1 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 |  | 
|  | 76 | /* | 
|  | 77 | * Baud rate (divisor) | 
|  | 78 | * Actually, there are two of them, MCT website calls them "Philips solution" | 
|  | 79 | * and "Intel solution". They are the regular MCT and "Sitecom" for us. | 
|  | 80 | * This is pointless to document in the header, see the code for the bits. | 
|  | 81 | */ | 
| Alan Cox | d0fab0d | 2007-12-13 16:15:29 -0800 | [diff] [blame] | 82 | static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value, speed_t *result); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 |  | 
|  | 84 | /* | 
|  | 85 | * Line Control Register (LCR) | 
|  | 86 | */ | 
|  | 87 | #define MCT_U232_SET_BREAK              0x40 | 
|  | 88 |  | 
|  | 89 | #define MCT_U232_PARITY_SPACE		0x38 | 
|  | 90 | #define MCT_U232_PARITY_MARK		0x28 | 
|  | 91 | #define MCT_U232_PARITY_EVEN		0x18 | 
|  | 92 | #define MCT_U232_PARITY_ODD		0x08 | 
|  | 93 | #define MCT_U232_PARITY_NONE		0x00 | 
|  | 94 |  | 
|  | 95 | #define MCT_U232_DATA_BITS_5            0x00 | 
|  | 96 | #define MCT_U232_DATA_BITS_6            0x01 | 
|  | 97 | #define MCT_U232_DATA_BITS_7            0x02 | 
|  | 98 | #define MCT_U232_DATA_BITS_8            0x03 | 
|  | 99 |  | 
|  | 100 | #define MCT_U232_STOP_BITS_2            0x04 | 
|  | 101 | #define MCT_U232_STOP_BITS_1            0x00 | 
|  | 102 |  | 
|  | 103 | /* | 
|  | 104 | * Modem Control Register (MCR) | 
|  | 105 | */ | 
|  | 106 | #define MCT_U232_MCR_NONE               0x8     /* Deactivate DTR and RTS */ | 
|  | 107 | #define MCT_U232_MCR_RTS                0xa     /* Activate RTS */ | 
|  | 108 | #define MCT_U232_MCR_DTR                0x9     /* Activate DTR */ | 
|  | 109 |  | 
|  | 110 | /* | 
|  | 111 | * Modem Status Register (MSR) | 
|  | 112 | */ | 
|  | 113 | #define MCT_U232_MSR_INDEX              0x0     /* data[index] */ | 
|  | 114 | #define MCT_U232_MSR_CD                 0x80    /* Current CD */ | 
|  | 115 | #define MCT_U232_MSR_RI                 0x40    /* Current RI */ | 
|  | 116 | #define MCT_U232_MSR_DSR                0x20    /* Current DSR */ | 
|  | 117 | #define MCT_U232_MSR_CTS                0x10    /* Current CTS */ | 
|  | 118 | #define MCT_U232_MSR_DCD                0x08    /* Delta CD */ | 
|  | 119 | #define MCT_U232_MSR_DRI                0x04    /* Delta RI */ | 
|  | 120 | #define MCT_U232_MSR_DDSR               0x02    /* Delta DSR */ | 
|  | 121 | #define MCT_U232_MSR_DCTS               0x01    /* Delta CTS */ | 
|  | 122 |  | 
|  | 123 | /* | 
|  | 124 | * Line Status Register (LSR) | 
|  | 125 | */ | 
|  | 126 | #define MCT_U232_LSR_INDEX              1       /* data[index] */ | 
|  | 127 | #define MCT_U232_LSR_ERR                0x80    /* OE | PE | FE | BI */ | 
|  | 128 | #define MCT_U232_LSR_TEMT               0x40    /* transmit register empty */ | 
|  | 129 | #define MCT_U232_LSR_THRE               0x20    /* transmit holding register empty */ | 
|  | 130 | #define MCT_U232_LSR_BI                 0x10    /* break indicator */ | 
|  | 131 | #define MCT_U232_LSR_FE                 0x08    /* framing error */ | 
|  | 132 | #define MCT_U232_LSR_OE                 0x02    /* overrun error */ | 
|  | 133 | #define MCT_U232_LSR_PE                 0x04    /* parity error */ | 
|  | 134 | #define MCT_U232_LSR_OE                 0x02    /* overrun error */ | 
|  | 135 | #define MCT_U232_LSR_DR                 0x01    /* receive data ready */ | 
|  | 136 |  | 
|  | 137 |  | 
|  | 138 | /* ----------------------------------------------------------------------------- | 
|  | 139 | * Technical Specification reverse engineered with SniffUSB on Windows98 | 
|  | 140 | * ===================================================================== | 
|  | 141 | * | 
|  | 142 | *  The technical details of the device have been acquired be using "SniffUSB" | 
|  | 143 | *  and the vendor-supplied device driver (version 2.3A) under Windows98. To | 
|  | 144 | *  identify the USB vendor-specific requests and to assign them to terminal | 
|  | 145 | *  settings (flow control, baud rate, etc.) the program "SerialSettings" from | 
|  | 146 | *  William G. Greathouse has been proven to be very useful. I also used the | 
|  | 147 | *  Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and | 
|  | 148 | *  observations are summarized below: | 
|  | 149 | * | 
|  | 150 | *  The USB requests seem to be directly mapped to the registers of a 8250, | 
|  | 151 | *  16450 or 16550 UART. The FreeBSD handbook (appendix F.4 "Input/Output | 
|  | 152 | *  devices") contains a comprehensive description of UARTs and its registers. | 
|  | 153 | *  The bit descriptions are actually taken from there. | 
|  | 154 | * | 
|  | 155 | * | 
|  | 156 | * Baud rate (divisor) | 
|  | 157 | * ------------------- | 
|  | 158 | * | 
|  | 159 | *   BmRequestType:  0x40 (0100 0000B) | 
|  | 160 | *   bRequest:       0x05 | 
|  | 161 | *   wValue:         0x0000 | 
|  | 162 | *   wIndex:         0x0000 | 
|  | 163 | *   wLength:        0x0004 | 
|  | 164 | *   Data:           divisor = 115200 / baud_rate | 
|  | 165 | * | 
|  | 166 | *   SniffUSB observations (Nov 2003): Contrary to the 'wLength' value of 4 | 
|  | 167 | *   shown above, observations with a Belkin F5U109 adapter, using the | 
|  | 168 | *   MCT-supplied Windows98 driver (U2SPORT.VXD, "File version: 1.21P.0104 for | 
|  | 169 | *   Win98/Me"), show this request has a length of 1 byte, presumably because | 
|  | 170 | *   of the fact that the Belkin adapter and the 'Sitecom U232-P25' adapter | 
|  | 171 | *   use a baud-rate code instead of a conventional RS-232 baud rate divisor. | 
|  | 172 | *   The current source code for this driver does not reflect this fact, but | 
|  | 173 | *   the driver works fine with this adapter/driver combination nonetheless. | 
|  | 174 | * | 
|  | 175 | * | 
|  | 176 | * Line Control Register (LCR) | 
|  | 177 | * --------------------------- | 
|  | 178 | * | 
|  | 179 | *  BmRequestType:  0x40 (0100 0000B)    0xc0 (1100 0000B) | 
|  | 180 | *  bRequest:       0x07                 0x06 | 
|  | 181 | *  wValue:         0x0000 | 
|  | 182 | *  wIndex:         0x0000 | 
|  | 183 | *  wLength:        0x0001 | 
|  | 184 | *  Data:           LCR (see below) | 
|  | 185 | * | 
|  | 186 | *  Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data | 
|  | 187 | *  	   transmit/receive register (THR/RBR) and the Interrupt Enable Register | 
|  | 188 | *  	   (IER) is disabled. Any access to these ports is now redirected to the | 
|  | 189 | *  	   Divisor Latch Registers. Setting this bit, loading the Divisor | 
|  | 190 | *  	   Registers, and clearing DLAB should be done with interrupts disabled. | 
|  | 191 | *  Bit 6: Set Break. When set to "1", the transmitter begins to transmit | 
|  | 192 | *  	   continuous Spacing until this bit is set to "0". This overrides any | 
|  | 193 | *  	   bits of characters that are being transmitted. | 
|  | 194 | *  Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity | 
|  | 195 | *  	   to always be "1" or "0", based on the value of Bit 4. | 
|  | 196 | *  Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "0", | 
|  | 197 | *  	   setting this bit causes even parity to be transmitted and expected. | 
|  | 198 | *  	   Otherwise, odd parity is used. | 
|  | 199 | *  Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted | 
|  | 200 | *  	   between the last bit of the data and the Stop Bit. The UART will also | 
|  | 201 | *  	   expect parity to be present in the received data. | 
|  | 202 | *  Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words, | 
|  | 203 | *  	   1.5 Stop Bits are transmitted and expected in each data word. For | 
|  | 204 | *  	   6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected. | 
|  | 205 | *  	   When this bit is set to "0", one Stop Bit is used on each data word. | 
|  | 206 | *  Bit 1: Word Length Select Bit #1 (WLSB1) | 
|  | 207 | *  Bit 0: Word Length Select Bit #0 (WLSB0) | 
|  | 208 | *  	   Together these bits specify the number of bits in each data word. | 
|  | 209 | *  	     1 0  Word Length | 
|  | 210 | *  	     0 0  5 Data Bits | 
|  | 211 | *  	     0 1  6 Data Bits | 
|  | 212 | *  	     1 0  7 Data Bits | 
|  | 213 | *  	     1 1  8 Data Bits | 
|  | 214 | * | 
|  | 215 | *  SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs | 
|  | 216 | *  in the Win98 driver: the break does not work (bit 6 is not asserted) and the | 
|  | 217 | *  stick parity bit is not cleared when set once. The LCR can also be read | 
|  | 218 | *  back with USB request 6 but this has never been observed with SniffUSB. | 
|  | 219 | * | 
|  | 220 | * | 
|  | 221 | * Modem Control Register (MCR) | 
|  | 222 | * ---------------------------- | 
|  | 223 | * | 
|  | 224 | *  BmRequestType:  0x40  (0100 0000B) | 
|  | 225 | *  bRequest:       0x0a | 
|  | 226 | *  wValue:         0x0000 | 
|  | 227 | *  wIndex:         0x0000 | 
|  | 228 | *  wLength:        0x0001 | 
|  | 229 | *  Data:           MCR (Bit 4..7, see below) | 
|  | 230 | * | 
|  | 231 | *  Bit 7: Reserved, always 0. | 
|  | 232 | *  Bit 6: Reserved, always 0. | 
|  | 233 | *  Bit 5: Reserved, always 0. | 
|  | 234 | *  Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver | 
|  | 235 | *  	   are internally connected together to allow diagnostic operations. In | 
|  | 236 | *  	   addition, the UART modem control outputs are connected to the UART | 
|  | 237 | *  	   modem control inputs. CTS is connected to RTS, DTR is connected to | 
|  | 238 | *  	   DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD. | 
|  | 239 | *  Bit 3: OUT 2. An auxiliary output that the host processor may set high or | 
|  | 240 | *  	   low. In the IBM PC serial adapter (and most clones), OUT 2 is used | 
|  | 241 | *  	   to tri-state (disable) the interrupt signal from the | 
|  | 242 | *  	   8250/16450/16550 UART. | 
|  | 243 | *  Bit 2: OUT 1. An auxiliary output that the host processor may set high or | 
|  | 244 | *  	   low. This output is not used on the IBM PC serial adapter. | 
|  | 245 | *  Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS | 
|  | 246 | *  	   line is Low (Active). | 
|  | 247 | *  Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART | 
|  | 248 | *  	   -DTR line is Low (Active). | 
|  | 249 | * | 
|  | 250 | *  SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been | 
|  | 251 | *  seen _always_ set. | 
|  | 252 | * | 
|  | 253 | * | 
|  | 254 | * Modem Status Register (MSR) | 
|  | 255 | * --------------------------- | 
|  | 256 | * | 
|  | 257 | *  BmRequestType:  0xc0  (1100 0000B) | 
|  | 258 | *  bRequest:       0x02 | 
|  | 259 | *  wValue:         0x0000 | 
|  | 260 | *  wIndex:         0x0000 | 
|  | 261 | *  wLength:        0x0001 | 
|  | 262 | *  Data:           MSR (see below) | 
|  | 263 | * | 
|  | 264 | *  Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the | 
|  | 265 | *  	   UART. | 
|  | 266 | *  Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART. | 
|  | 267 | *  Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART. | 
|  | 268 | *  Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART. | 
|  | 269 | *  Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has | 
|  | 270 | *  	   changed state one more more times since the last time the MSR was | 
|  | 271 | *  	   read by the host. | 
|  | 272 | *  Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has | 
|  | 273 | *  	   had a low to high transition since the last time the MSR was read by | 
|  | 274 | *  	   the host. | 
|  | 275 | *  Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed | 
|  | 276 | *  	   state one more more times since the last time the MSR was read by the | 
|  | 277 | *  	   host. | 
|  | 278 | *  Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed | 
|  | 279 | *  	   state one more times since the last time the MSR was read by the | 
|  | 280 | *  	   host. | 
|  | 281 | * | 
|  | 282 | *  SniffUSB observations: the MSR is also returned as first byte on the | 
|  | 283 | *  interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB | 
|  | 284 | *  request to read MSR cannot be applied during normal device operation. | 
|  | 285 | * | 
|  | 286 | * | 
|  | 287 | * Line Status Register (LSR) | 
|  | 288 | * -------------------------- | 
|  | 289 | * | 
|  | 290 | *  Bit 7   Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero. | 
|  | 291 | *  	    This bit is set to "1" when any of the bytes in the FIFO have one or | 
|  | 292 | *  	    more of the following error conditions: PE, FE, or BI. | 
|  | 293 | *  Bit 6   Transmitter Empty (TEMT). When set to "1", there are no words | 
|  | 294 | *  	    remaining in the transmit FIFO or the transmit shift register. The | 
|  | 295 | *  	    transmitter is completely idle. | 
|  | 296 | *  Bit 5   Transmitter Holding Register Empty (THRE). When set to "1", the FIFO | 
|  | 297 | *  	    (or holding register) now has room for at least one additional word | 
|  | 298 | *  	    to transmit. The transmitter may still be transmitting when this bit | 
|  | 299 | *  	    is set to "1". | 
|  | 300 | *  Bit 4   Break Interrupt (BI). The receiver has detected a Break signal. | 
|  | 301 | *  Bit 3   Framing Error (FE). A Start Bit was detected but the Stop Bit did not | 
|  | 302 | *  	    appear at the expected time. The received word is probably garbled. | 
|  | 303 | *  Bit 2   Parity Error (PE). The parity bit was incorrect for the word received. | 
|  | 304 | *  Bit 1   Overrun Error (OE). A new word was received and there was no room in | 
|  | 305 | *  	    the receive buffer. The newly-arrived word in the shift register is | 
|  | 306 | *  	    discarded. On 8250/16450 UARTs, the word in the holding register is | 
|  | 307 | *  	    discarded and the newly- arrived word is put in the holding register. | 
|  | 308 | *  Bit 0   Data Ready (DR). One or more words are in the receive FIFO that the | 
|  | 309 | *  	    host may read. A word must be completely received and moved from the | 
|  | 310 | *  	    shift register into the FIFO (or holding register for 8250/16450 | 
|  | 311 | *  	    designs) before this bit is set. | 
|  | 312 | * | 
|  | 313 | *  SniffUSB observations: the LSR is returned as second byte on the interrupt-in | 
|  | 314 | *  endpoint 0x83 to signal error conditions. Such errors have been seen with | 
|  | 315 | *  minicom/zmodem transfers (CRC errors). | 
|  | 316 | * | 
|  | 317 | * | 
|  | 318 | * Unknown #1 | 
|  | 319 | * ------------------- | 
|  | 320 | * | 
|  | 321 | *   BmRequestType:  0x40 (0100 0000B) | 
|  | 322 | *   bRequest:       0x0b | 
|  | 323 | *   wValue:         0x0000 | 
|  | 324 | *   wIndex:         0x0000 | 
|  | 325 | *   wLength:        0x0001 | 
|  | 326 | *   Data:           0x00 | 
|  | 327 | * | 
|  | 328 | *   SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver | 
|  | 329 | *   (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request | 
|  | 330 | *   occurs immediately after a "Baud rate (divisor)" message.  It was not | 
|  | 331 | *   observed at any other time.  It is unclear what purpose this message | 
|  | 332 | *   serves. | 
|  | 333 | * | 
|  | 334 | * | 
|  | 335 | * Unknown #2 | 
|  | 336 | * ------------------- | 
|  | 337 | * | 
|  | 338 | *   BmRequestType:  0x40 (0100 0000B) | 
|  | 339 | *   bRequest:       0x0c | 
|  | 340 | *   wValue:         0x0000 | 
|  | 341 | *   wIndex:         0x0000 | 
|  | 342 | *   wLength:        0x0001 | 
|  | 343 | *   Data:           0x00 | 
|  | 344 | * | 
|  | 345 | *   SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver | 
|  | 346 | *   (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request | 
|  | 347 | *   occurs immediately after the 'Unknown #1' message (see above).  It was | 
|  | 348 | *   not observed at any other time.  It is unclear what other purpose (if | 
|  | 349 | *   any) this message might serve, but without it, the USB/RS-232 adapter | 
|  | 350 | *   will not write to RS-232 devices which do not assert the 'CTS' signal. | 
|  | 351 | * | 
|  | 352 | * | 
|  | 353 | * Flow control | 
|  | 354 | * ------------ | 
|  | 355 | * | 
|  | 356 | *  SniffUSB observations: no flow control specific requests have been realized | 
|  | 357 | *  apart from DTR/RTS settings. Both signals are dropped for no flow control | 
|  | 358 | *  but asserted for hardware or software flow control. | 
|  | 359 | * | 
|  | 360 | * | 
|  | 361 | * Endpoint usage | 
|  | 362 | * -------------- | 
|  | 363 | * | 
|  | 364 | *  SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint | 
|  | 365 | *  0x81 is used to transmit and receive characters. The second interrupt-in | 
|  | 366 | *  endpoint 0x83 signals exceptional conditions like modem line changes and | 
|  | 367 | *  errors. The first byte returned is the MSR and the second byte the LSR. | 
|  | 368 | * | 
|  | 369 | * | 
|  | 370 | * Other observations | 
|  | 371 | * ------------------ | 
|  | 372 | * | 
|  | 373 | *  Queued bulk transfers like used in visor.c did not work. | 
|  | 374 | * | 
|  | 375 | * | 
|  | 376 | * Properties of the USB device used (as found in /var/log/messages) | 
|  | 377 | * ----------------------------------------------------------------- | 
|  | 378 | * | 
|  | 379 | *  Manufacturer: MCT Corporation. | 
|  | 380 | *  Product: USB-232 Interfact Controller | 
|  | 381 | *  SerialNumber: U2S22050 | 
|  | 382 | * | 
|  | 383 | *    Length              = 18 | 
|  | 384 | *    DescriptorType      = 01 | 
|  | 385 | *    USB version         = 1.00 | 
|  | 386 | *    Vendor:Product      = 0711:0210 | 
|  | 387 | *    MaxPacketSize0      = 8 | 
|  | 388 | *    NumConfigurations   = 1 | 
|  | 389 | *    Device version      = 1.02 | 
|  | 390 | *    Device Class:SubClass:Protocol = 00:00:00 | 
|  | 391 | *      Per-interface classes | 
|  | 392 | *  Configuration: | 
|  | 393 | *    bLength             =    9 | 
|  | 394 | *    bDescriptorType     =   02 | 
|  | 395 | *    wTotalLength        = 0027 | 
|  | 396 | *    bNumInterfaces      =   01 | 
|  | 397 | *    bConfigurationValue =   01 | 
|  | 398 | *    iConfiguration      =   00 | 
|  | 399 | *    bmAttributes        =   c0 | 
|  | 400 | *    MaxPower            =  100mA | 
|  | 401 | * | 
|  | 402 | *    Interface: 0 | 
|  | 403 | *    Alternate Setting:  0 | 
|  | 404 | *      bLength             =    9 | 
|  | 405 | *      bDescriptorType     =   04 | 
|  | 406 | *      bInterfaceNumber    =   00 | 
|  | 407 | *      bAlternateSetting   =   00 | 
|  | 408 | *      bNumEndpoints       =   03 | 
|  | 409 | *      bInterface Class:SubClass:Protocol =   00:00:00 | 
|  | 410 | *      iInterface          =   00 | 
|  | 411 | *      Endpoint: | 
|  | 412 | * 	  bLength             =    7 | 
|  | 413 | * 	  bDescriptorType     =   05 | 
|  | 414 | * 	  bEndpointAddress    =   81 (in) | 
|  | 415 | * 	  bmAttributes        =   03 (Interrupt) | 
|  | 416 | * 	  wMaxPacketSize      = 0040 | 
|  | 417 | * 	  bInterval           =   02 | 
|  | 418 | *      Endpoint: | 
|  | 419 | * 	  bLength             =    7 | 
|  | 420 | * 	  bDescriptorType     =   05 | 
|  | 421 | * 	  bEndpointAddress    =   01 (out) | 
|  | 422 | * 	  bmAttributes        =   02 (Bulk) | 
|  | 423 | * 	  wMaxPacketSize      = 0040 | 
|  | 424 | * 	  bInterval           =   00 | 
|  | 425 | *      Endpoint: | 
|  | 426 | * 	  bLength             =    7 | 
|  | 427 | * 	  bDescriptorType     =   05 | 
|  | 428 | * 	  bEndpointAddress    =   83 (in) | 
|  | 429 | * 	  bmAttributes        =   03 (Interrupt) | 
|  | 430 | * 	  wMaxPacketSize      = 0002 | 
|  | 431 | * 	  bInterval           =   02 | 
|  | 432 | * | 
|  | 433 | * | 
|  | 434 | * Hardware details (added by Martin Hamilton, 2001/12/06) | 
|  | 435 | * ----------------------------------------------------------------- | 
|  | 436 | * | 
|  | 437 | * This info was gleaned from opening a Belkin F5U109 DB9 USB serial | 
|  | 438 | * adaptor, which turns out to simply be a re-badged U232-P9.  We | 
|  | 439 | * know this because there is a sticky label on the circuit board | 
|  | 440 | * which says "U232-P9" ;-) | 
|  | 441 | * | 
|  | 442 | * The circuit board inside the adaptor contains a Philips PDIUSBD12 | 
| Dave Platt | 45b844d | 2007-05-08 11:00:12 -0700 | [diff] [blame] | 443 | * USB endpoint chip and a Philips P87C52UBAA microcontroller with | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | * embedded UART.  Exhaustive documentation for these is available at: | 
|  | 445 | * | 
|  | 446 | *   http://www.semiconductors.philips.com/pip/p87c52ubaa | 
|  | 447 | *   http://www.semiconductors.philips.com/pip/pdiusbd12 | 
|  | 448 | * | 
|  | 449 | * Thanks to Julian Highfield for the pointer to the Philips database. | 
|  | 450 | * | 
|  | 451 | */ | 
|  | 452 |  | 
|  | 453 | #endif /* __LINUX_USB_SERIAL_MCT_U232_H */ | 
|  | 454 |  |