| Cedric Bregardis | 98f2a97 | 2008-02-20 12:05:13 +0100 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * |
| 3 | * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and |
| 4 | * Jean-Christian Hassler <jhassler@free.fr> |
| 5 | * |
| 6 | * This file is part of the Audiowerk2 ALSA driver |
| 7 | * |
| 8 | * The Audiowerk2 ALSA driver is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2. |
| 11 | * |
| 12 | * The Audiowerk2 ALSA driver is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with the Audiowerk2 ALSA driver; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, |
| 20 | * USA. |
| 21 | * |
| 22 | *****************************************************************************/ |
| 23 | |
| 24 | /* SAA7146 registers */ |
| 25 | #define PCI_BT_A 0x4C |
| 26 | #define IICTFR 0x8C |
| 27 | #define IICSTA 0x90 |
| 28 | #define BaseA1_in 0x94 |
| 29 | #define ProtA1_in 0x98 |
| 30 | #define PageA1_in 0x9C |
| 31 | #define BaseA1_out 0xA0 |
| 32 | #define ProtA1_out 0xA4 |
| 33 | #define PageA1_out 0xA8 |
| 34 | #define BaseA2_in 0xAC |
| 35 | #define ProtA2_in 0xB0 |
| 36 | #define PageA2_in 0xB4 |
| 37 | #define BaseA2_out 0xB8 |
| 38 | #define ProtA2_out 0xBC |
| 39 | #define PageA2_out 0xC0 |
| 40 | #define IER 0xDC |
| 41 | #define GPIO_CTRL 0xE0 |
| 42 | #define ACON1 0xF4 |
| 43 | #define ACON2 0xF8 |
| 44 | #define MC1 0xFC |
| 45 | #define MC2 0x100 |
| 46 | #define ISR 0x10C |
| 47 | #define PSR 0x110 |
| 48 | #define SSR 0x114 |
| 49 | #define PCI_ADP1 0x12C |
| 50 | #define PCI_ADP2 0x130 |
| 51 | #define PCI_ADP3 0x134 |
| 52 | #define PCI_ADP4 0x138 |
| 53 | #define LEVEL_REP 0x140 |
| 54 | #define FB_BUFFER1 0x144 |
| 55 | #define FB_BUFFER2 0x148 |
| 56 | #define TSL1 0x180 |
| 57 | #define TSL2 0x1C0 |
| 58 | |
| 59 | #define ME (1UL << 11) |
| 60 | #define LIMIT (1UL << 4) |
| 61 | #define PV (1UL << 3) |
| 62 | |
| 63 | /* PSR/ISR/IER */ |
| 64 | #define PPEF (1UL << 31) |
| 65 | #define PABO (1UL << 30) |
| 66 | #define IIC_S (1UL << 17) |
| 67 | #define IIC_E (1UL << 16) |
| 68 | #define A2_in (1UL << 15) |
| 69 | #define A2_out (1UL << 14) |
| 70 | #define A1_in (1UL << 13) |
| 71 | #define A1_out (1UL << 12) |
| 72 | #define AFOU (1UL << 11) |
| 73 | #define PIN3 (1UL << 6) |
| 74 | #define PIN2 (1UL << 5) |
| 75 | #define PIN1 (1UL << 4) |
| 76 | #define PIN0 (1UL << 3) |
| 77 | #define ECS (1UL << 2) |
| 78 | #define EC3S (1UL << 1) |
| 79 | #define EC0S (1UL << 0) |
| 80 | |
| 81 | /* SSR */ |
| 82 | #define PRQ (1UL << 31) |
| 83 | #define PMA (1UL << 30) |
| 84 | #define IIC_EA (1UL << 21) |
| 85 | #define IIC_EW (1UL << 20) |
| 86 | #define IIC_ER (1UL << 19) |
| 87 | #define IIC_EL (1UL << 18) |
| 88 | #define IIC_EF (1UL << 17) |
| 89 | #define AF2_in (1UL << 10) |
| 90 | #define AF2_out (1UL << 9) |
| 91 | #define AF1_in (1UL << 8) |
| 92 | #define AF1_out (1UL << 7) |
| 93 | #define EC5S (1UL << 3) |
| 94 | #define EC4S (1UL << 2) |
| 95 | #define EC2S (1UL << 1) |
| 96 | #define EC1S (1UL << 0) |
| 97 | |
| 98 | /* PCI_BT_A */ |
| 99 | #define BurstA1_in (1UL << 26) |
| 100 | #define ThreshA1_in (1UL << 24) |
| 101 | #define BurstA1_out (1UL << 18) |
| 102 | #define ThreshA1_out (1UL << 16) |
| 103 | #define BurstA2_in (1UL << 10) |
| 104 | #define ThreshA2_in (1UL << 8) |
| 105 | #define BurstA2_out (1UL << 2) |
| 106 | #define ThreshA2_out (1UL << 0) |
| 107 | |
| 108 | /* MC1 */ |
| 109 | #define MRST_N (1UL << 15) |
| 110 | #define EAP (1UL << 9) |
| 111 | #define EI2C (1UL << 8) |
| 112 | #define TR_E_A2_OUT (1UL << 3) |
| 113 | #define TR_E_A2_IN (1UL << 2) |
| 114 | #define TR_E_A1_OUT (1UL << 1) |
| 115 | #define TR_E_A1_IN (1UL << 0) |
| 116 | |
| 117 | /* MC2 */ |
| 118 | #define UPLD_IIC (1UL << 0) |
| 119 | |
| 120 | /* ACON1 */ |
| 121 | #define AUDIO_MODE (1UL << 29) |
| 122 | #define MAXLEVEL (1UL << 22) |
| 123 | #define A1_SWAP (1UL << 21) |
| 124 | #define A2_SWAP (1UL << 20) |
| 125 | #define WS0_CTRL (1UL << 18) |
| 126 | #define WS0_SYNC (1UL << 16) |
| 127 | #define WS1_CTRL (1UL << 14) |
| 128 | #define WS1_SYNC (1UL << 12) |
| 129 | #define WS2_CTRL (1UL << 10) |
| 130 | #define WS2_SYNC (1UL << 8) |
| 131 | #define WS3_CTRL (1UL << 6) |
| 132 | #define WS3_SYNC (1UL << 4) |
| 133 | #define WS4_CTRL (1UL << 2) |
| 134 | #define WS4_SYNC (1UL << 0) |
| 135 | |
| 136 | /* ACON2 */ |
| 137 | #define A1_CLKSRC (1UL << 27) |
| 138 | #define A2_CLKSRC (1UL << 22) |
| 139 | #define INVERT_BCLK1 (1UL << 21) |
| 140 | #define INVERT_BCLK2 (1UL << 20) |
| 141 | #define BCLK1_OEN (1UL << 19) |
| 142 | #define BCLK2_OEN (1UL << 18) |
| 143 | |
| 144 | /* IICSTA */ |
| 145 | #define IICCC (1UL << 8) |
| 146 | #define ABORT (1UL << 7) |
| 147 | #define SPERR (1UL << 6) |
| 148 | #define APERR (1UL << 5) |
| 149 | #define DTERR (1UL << 4) |
| 150 | #define DRERR (1UL << 3) |
| 151 | #define AL (1UL << 2) |
| 152 | #define ERR (1UL << 1) |
| 153 | #define BUSY (1UL << 0) |
| 154 | |
| 155 | /* IICTFR */ |
| 156 | #define BYTE2 (1UL << 24) |
| 157 | #define BYTE1 (1UL << 16) |
| 158 | #define BYTE0 (1UL << 8) |
| 159 | #define ATRR2 (1UL << 6) |
| 160 | #define ATRR1 (1UL << 4) |
| 161 | #define ATRR0 (1UL << 2) |
| 162 | #define ERR (1UL << 1) |
| 163 | #define BUSY (1UL << 0) |
| 164 | |
| 165 | #define START 3 |
| 166 | #define CONT 2 |
| 167 | #define STOP 1 |
| 168 | #define NOP 0 |