| Sagar Dharia | 4c5bef3 | 2012-03-14 17:00:29 -0600 | [diff] [blame] | 1 | Qualcomm I2C controller |
| 2 | |
| 3 | Required properties: |
| 4 | |
| 5 | - reg : Offset and length of the register region(s) for the device |
| 6 | For GSBI based controller, GSBI and QUP regions are expected |
| 7 | For BLSP based controller, QUP region offset is expected |
| 8 | - reg-names : Register region name(s) referenced in reg above |
| 9 | BLSP based controller expects QUP region name ("qup_phys_addr") |
| 10 | GSBI controller expects QUP region name and GSBI region name |
| 11 | ("gsbi_qup_i2c_addr") |
| 12 | - compatible : should be "qcom,i2c-qup" |
| 13 | - cell-index : I2C bus number used for this controller |
| 14 | - interrupts : QUP core interrupt(s). Core may have 1 error interrupt and flags |
| 15 | for input/output service, or 3 separate interrupts for the 3 services |
| 16 | - interrupt-names: QUP core interrupt name(s) referenced in interrupts above |
| 17 | Expected interrupt resource name(s) are: "qup_err_irq", "qup_in_irq", |
| 18 | and "qup_out_irq" |
| 19 | - qcom,i2c-bus-freq : desired I2C bus clock frequency is Hz |
| 20 | |
| 21 | Optional property: |
| 22 | - qcom,i2c-src-freq : Frequency of the source clocking this bus in Hz. |
| 23 | Divider value is set based on soruce-frequency and |
| 24 | desired I2C bus frequency. If this value is not |
| 25 | provided, the source clock is assumed to be running |
| 26 | at 19.2 MHz. |
| 27 | Example: |
| 28 | i2c@f9966000 { |
| 29 | cell-index = <0>; |
| 30 | compatible = "qcom,i2c-qup"; |
| 31 | reg = <0xf9966000 0x1000>; |
| 32 | reg-names = "qup_phys_addr"; |
| 33 | interrupts = <0 104 0>; |
| 34 | interrupt-names = "qup_err_intr"; |
| 35 | qcom,i2c-bus-freq = <100000>; |
| 36 | qcom,i2c-src-freq = <24000000>; |
| 37 | }; |