| Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1 | #ifndef B43_XMIT_H_ | 
|  | 2 | #define B43_XMIT_H_ | 
|  | 3 |  | 
|  | 4 | #include "main.h" | 
|  | 5 |  | 
|  | 6 | #define _b43_declare_plcp_hdr(size) \ | 
|  | 7 | struct b43_plcp_hdr##size {		\ | 
|  | 8 | union {				\ | 
|  | 9 | __le32 data;		\ | 
|  | 10 | __u8 raw[size];		\ | 
|  | 11 | } __attribute__((__packed__));	\ | 
|  | 12 | } __attribute__((__packed__)) | 
|  | 13 |  | 
|  | 14 | /* struct b43_plcp_hdr4 */ | 
|  | 15 | _b43_declare_plcp_hdr(4); | 
|  | 16 | /* struct b43_plcp_hdr6 */ | 
|  | 17 | _b43_declare_plcp_hdr(6); | 
|  | 18 |  | 
|  | 19 | #undef _b43_declare_plcp_hdr | 
|  | 20 |  | 
|  | 21 | /* TX header for v4 firmware */ | 
|  | 22 | struct b43_txhdr_fw4 { | 
|  | 23 | __le32 mac_ctl;		/* MAC TX control */ | 
|  | 24 | __le16 mac_frame_ctl;	/* Copy of the FrameControl field */ | 
|  | 25 | __le16 tx_fes_time_norm;	/* TX FES Time Normal */ | 
|  | 26 | __le16 phy_ctl;		/* PHY TX control */ | 
|  | 27 | __le16 phy_ctl_0;	/* Unused */ | 
|  | 28 | __le16 phy_ctl_1;	/* Unused */ | 
|  | 29 | __le16 phy_ctl_rts_0;	/* Unused */ | 
|  | 30 | __le16 phy_ctl_rts_1;	/* Unused */ | 
|  | 31 | __u8 phy_rate;		/* PHY rate */ | 
|  | 32 | __u8 phy_rate_rts;	/* PHY rate for RTS/CTS */ | 
|  | 33 | __u8 extra_ft;		/* Extra Frame Types */ | 
|  | 34 | __u8 chan_radio_code;	/* Channel Radio Code */ | 
|  | 35 | __u8 iv[16];		/* Encryption IV */ | 
|  | 36 | __u8 tx_receiver[6];	/* TX Frame Receiver address */ | 
|  | 37 | __le16 tx_fes_time_fb;	/* TX FES Time Fallback */ | 
|  | 38 | struct b43_plcp_hdr6 rts_plcp_fb;	/* RTS fallback PLCP */ | 
|  | 39 | __le16 rts_dur_fb;	/* RTS fallback duration */ | 
|  | 40 | struct b43_plcp_hdr6 plcp_fb;	/* Fallback PLCP */ | 
|  | 41 | __le16 dur_fb;		/* Fallback duration */ | 
|  | 42 | __le16 mm_dur_time;	/* Unused */ | 
|  | 43 | __le16 mm_dur_time_fb;	/* Unused */ | 
|  | 44 | __le32 time_stamp;	/* Timestamp */ | 
|  | 45 | PAD_BYTES(2); | 
|  | 46 | __le16 cookie;		/* TX frame cookie */ | 
|  | 47 | __le16 tx_status;	/* TX status */ | 
|  | 48 | struct b43_plcp_hdr6 rts_plcp;	/* RTS PLCP */ | 
|  | 49 | __u8 rts_frame[16];	/* The RTS frame (if used) */ | 
|  | 50 | PAD_BYTES(2); | 
|  | 51 | struct b43_plcp_hdr6 plcp;	/* Main PLCP */ | 
|  | 52 | } __attribute__ ((__packed__)); | 
|  | 53 |  | 
|  | 54 | /* MAC TX control */ | 
|  | 55 | #define B43_TX4_MAC_KEYIDX		0x0FF00000	/* Security key index */ | 
|  | 56 | #define B43_TX4_MAC_KEYIDX_SHIFT	20 | 
|  | 57 | #define B43_TX4_MAC_KEYALG		0x00070000	/* Security key algorithm */ | 
|  | 58 | #define B43_TX4_MAC_KEYALG_SHIFT	16 | 
|  | 59 | #define B43_TX4_MAC_LIFETIME	0x00001000 | 
|  | 60 | #define B43_TX4_MAC_FRAMEBURST	0x00000800 | 
|  | 61 | #define B43_TX4_MAC_SENDCTS		0x00000400 | 
|  | 62 | #define B43_TX4_MAC_AMPDU		0x00000300 | 
|  | 63 | #define B43_TX4_MAC_AMPDU_SHIFT	8 | 
|  | 64 | #define B43_TX4_MAC_5GHZ		0x00000080 | 
|  | 65 | #define B43_TX4_MAC_IGNPMQ		0x00000020 | 
|  | 66 | #define B43_TX4_MAC_HWSEQ		0x00000010	/* Use Hardware Sequence Number */ | 
|  | 67 | #define B43_TX4_MAC_STMSDU		0x00000008	/* Start MSDU */ | 
|  | 68 | #define B43_TX4_MAC_SENDRTS		0x00000004 | 
|  | 69 | #define B43_TX4_MAC_LONGFRAME	0x00000002 | 
|  | 70 | #define B43_TX4_MAC_ACK		0x00000001 | 
|  | 71 |  | 
|  | 72 | /* Extra Frame Types */ | 
|  | 73 | #define B43_TX4_EFT_FBOFDM		0x0001	/* Data frame fallback rate type */ | 
|  | 74 | #define B43_TX4_EFT_RTSOFDM		0x0004	/* RTS/CTS rate type */ | 
|  | 75 | #define B43_TX4_EFT_RTSFBOFDM	0x0010	/* RTS/CTS fallback rate type */ | 
|  | 76 |  | 
|  | 77 | /* PHY TX control word */ | 
|  | 78 | #define B43_TX4_PHY_OFDM		0x0001	/* Data frame rate type */ | 
|  | 79 | #define B43_TX4_PHY_SHORTPRMBL	0x0010	/* Use short preamble */ | 
|  | 80 | #define B43_TX4_PHY_ANT		0x03C0	/* Antenna selection */ | 
|  | 81 | #define  B43_TX4_PHY_ANT0		0x0000	/* Use antenna 0 */ | 
|  | 82 | #define  B43_TX4_PHY_ANT1		0x0100	/* Use antenna 1 */ | 
|  | 83 | #define  B43_TX4_PHY_ANTLAST	0x0300	/* Use last used antenna */ | 
|  | 84 |  | 
|  | 85 | void b43_generate_txhdr(struct b43_wldev *dev, | 
|  | 86 | u8 * txhdr, | 
|  | 87 | const unsigned char *fragment_data, | 
|  | 88 | unsigned int fragment_len, | 
|  | 89 | const struct ieee80211_tx_control *txctl, u16 cookie); | 
|  | 90 |  | 
|  | 91 | /* Transmit Status */ | 
|  | 92 | struct b43_txstatus { | 
|  | 93 | u16 cookie;		/* The cookie from the txhdr */ | 
|  | 94 | u16 seq;		/* Sequence number */ | 
|  | 95 | u8 phy_stat;		/* PHY TX status */ | 
|  | 96 | u8 frame_count;		/* Frame transmit count */ | 
|  | 97 | u8 rts_count;		/* RTS transmit count */ | 
|  | 98 | u8 supp_reason;		/* Suppression reason */ | 
|  | 99 | /* flags */ | 
|  | 100 | u8 pm_indicated;	/* PM mode indicated to AP */ | 
|  | 101 | u8 intermediate;	/* Intermediate status notification (not final) */ | 
|  | 102 | u8 for_ampdu;		/* Status is for an AMPDU (afterburner) */ | 
|  | 103 | u8 acked;		/* Wireless ACK received */ | 
|  | 104 | }; | 
|  | 105 |  | 
|  | 106 | /* txstatus supp_reason values */ | 
|  | 107 | enum { | 
|  | 108 | B43_TXST_SUPP_NONE,	/* Not suppressed */ | 
|  | 109 | B43_TXST_SUPP_PMQ,	/* Suppressed due to PMQ entry */ | 
|  | 110 | B43_TXST_SUPP_FLUSH,	/* Suppressed due to flush request */ | 
|  | 111 | B43_TXST_SUPP_PREV,	/* Previous fragment failed */ | 
|  | 112 | B43_TXST_SUPP_CHAN,	/* Channel mismatch */ | 
|  | 113 | B43_TXST_SUPP_LIFE,	/* Lifetime expired */ | 
|  | 114 | B43_TXST_SUPP_UNDER,	/* Buffer underflow */ | 
|  | 115 | B43_TXST_SUPP_ABNACK,	/* Afterburner NACK */ | 
|  | 116 | }; | 
|  | 117 |  | 
|  | 118 | /* Transmit Status as received through DMA/PIO on old chips */ | 
|  | 119 | struct b43_hwtxstatus { | 
|  | 120 | PAD_BYTES(4); | 
|  | 121 | __le16 cookie; | 
|  | 122 | u8 flags; | 
|  | 123 | u8 count; | 
|  | 124 | PAD_BYTES(2); | 
|  | 125 | __le16 seq; | 
|  | 126 | u8 phy_stat; | 
|  | 127 | PAD_BYTES(1); | 
|  | 128 | } __attribute__ ((__packed__)); | 
|  | 129 |  | 
|  | 130 | /* Receive header for v4 firmware. */ | 
|  | 131 | struct b43_rxhdr_fw4 { | 
|  | 132 | __le16 frame_len;	/* Frame length */ | 
|  | 133 | PAD_BYTES(2); | 
|  | 134 | __le16 phy_status0;	/* PHY RX Status 0 */ | 
|  | 135 | __u8 jssi;		/* PHY RX Status 1: JSSI */ | 
|  | 136 | __u8 sig_qual;		/* PHY RX Status 1: Signal Quality */ | 
|  | 137 | __le16 phy_status2;	/* PHY RX Status 2 */ | 
|  | 138 | __le16 phy_status3;	/* PHY RX Status 3 */ | 
|  | 139 | __le32 mac_status;	/* MAC RX status */ | 
|  | 140 | __le16 mac_time; | 
|  | 141 | __le16 channel; | 
|  | 142 | } __attribute__ ((__packed__)); | 
|  | 143 |  | 
|  | 144 | /* PHY RX Status 0 */ | 
|  | 145 | #define B43_RX_PHYST0_GAINCTL	0x4000	/* Gain Control */ | 
|  | 146 | #define B43_RX_PHYST0_PLCPHCF	0x0200 | 
|  | 147 | #define B43_RX_PHYST0_PLCPFV	0x0100 | 
|  | 148 | #define B43_RX_PHYST0_SHORTPRMBL	0x0080	/* Received with Short Preamble */ | 
|  | 149 | #define B43_RX_PHYST0_LCRS		0x0040 | 
|  | 150 | #define B43_RX_PHYST0_ANT		0x0020	/* Antenna */ | 
|  | 151 | #define B43_RX_PHYST0_UNSRATE	0x0010 | 
|  | 152 | #define B43_RX_PHYST0_CLIP		0x000C | 
|  | 153 | #define B43_RX_PHYST0_CLIP_SHIFT	2 | 
|  | 154 | #define B43_RX_PHYST0_FTYPE		0x0003	/* Frame type */ | 
|  | 155 | #define  B43_RX_PHYST0_CCK		0x0000	/* Frame type: CCK */ | 
|  | 156 | #define  B43_RX_PHYST0_OFDM		0x0001	/* Frame type: OFDM */ | 
|  | 157 | #define  B43_RX_PHYST0_PRE_N	0x0002	/* Pre-standard N-PHY frame */ | 
|  | 158 | #define  B43_RX_PHYST0_STD_N	0x0003	/* Standard N-PHY frame */ | 
|  | 159 |  | 
|  | 160 | /* PHY RX Status 2 */ | 
|  | 161 | #define B43_RX_PHYST2_LNAG		0xC000	/* LNA Gain */ | 
|  | 162 | #define B43_RX_PHYST2_LNAG_SHIFT	14 | 
|  | 163 | #define B43_RX_PHYST2_PNAG		0x3C00	/* PNA Gain */ | 
|  | 164 | #define B43_RX_PHYST2_PNAG_SHIFT	10 | 
|  | 165 | #define B43_RX_PHYST2_FOFF		0x03FF	/* F offset */ | 
|  | 166 |  | 
|  | 167 | /* PHY RX Status 3 */ | 
|  | 168 | #define B43_RX_PHYST3_DIGG		0x1800	/* DIG Gain */ | 
|  | 169 | #define B43_RX_PHYST3_DIGG_SHIFT	11 | 
|  | 170 | #define B43_RX_PHYST3_TRSTATE	0x0400	/* TR state */ | 
|  | 171 |  | 
|  | 172 | /* MAC RX Status */ | 
|  | 173 | #define B43_RX_MAC_BEACONSENT	0x00008000	/* Beacon send flag */ | 
|  | 174 | #define B43_RX_MAC_KEYIDX		0x000007E0	/* Key index */ | 
|  | 175 | #define B43_RX_MAC_KEYIDX_SHIFT	5 | 
|  | 176 | #define B43_RX_MAC_DECERR		0x00000010	/* Decrypt error */ | 
|  | 177 | #define B43_RX_MAC_DEC		0x00000008	/* Decryption attempted */ | 
|  | 178 | #define B43_RX_MAC_PADDING		0x00000004	/* Pad bytes present */ | 
|  | 179 | #define B43_RX_MAC_RESP		0x00000002	/* Response frame transmitted */ | 
|  | 180 | #define B43_RX_MAC_FCSERR		0x00000001	/* FCS error */ | 
|  | 181 |  | 
|  | 182 | /* RX channel */ | 
|  | 183 | #define B43_RX_CHAN_GAIN		0xFC00	/* Gain */ | 
|  | 184 | #define B43_RX_CHAN_GAIN_SHIFT	10 | 
|  | 185 | #define B43_RX_CHAN_ID		0x03FC	/* Channel ID */ | 
|  | 186 | #define B43_RX_CHAN_ID_SHIFT	2 | 
|  | 187 | #define B43_RX_CHAN_PHYTYPE		0x0003	/* PHY type */ | 
|  | 188 |  | 
|  | 189 | u8 b43_plcp_get_ratecode_cck(const u8 bitrate); | 
|  | 190 | u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); | 
|  | 191 |  | 
|  | 192 | void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, | 
|  | 193 | const u16 octets, const u8 bitrate); | 
|  | 194 |  | 
|  | 195 | void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); | 
|  | 196 |  | 
|  | 197 | void b43_handle_txstatus(struct b43_wldev *dev, | 
|  | 198 | const struct b43_txstatus *status); | 
|  | 199 |  | 
|  | 200 | void b43_handle_hwtxstatus(struct b43_wldev *dev, | 
|  | 201 | const struct b43_hwtxstatus *hw); | 
|  | 202 |  | 
|  | 203 | void b43_tx_suspend(struct b43_wldev *dev); | 
|  | 204 | void b43_tx_resume(struct b43_wldev *dev); | 
|  | 205 |  | 
|  | 206 | #define B43_NR_QOSPARMS		22 | 
|  | 207 | enum { | 
|  | 208 | B43_QOSPARM_TXOP = 0, | 
|  | 209 | B43_QOSPARM_CWMIN, | 
|  | 210 | B43_QOSPARM_CWMAX, | 
|  | 211 | B43_QOSPARM_CWCUR, | 
|  | 212 | B43_QOSPARM_AIFS, | 
|  | 213 | B43_QOSPARM_BSLOTS, | 
|  | 214 | B43_QOSPARM_REGGAP, | 
|  | 215 | B43_QOSPARM_STATUS, | 
|  | 216 | }; | 
|  | 217 | void b43_qos_init(struct b43_wldev *dev); | 
|  | 218 |  | 
|  | 219 | /* Helper functions for converting the key-table index from "firmware-format" | 
|  | 220 | * to "raw-format" and back. The firmware API changed for this at some revision. | 
|  | 221 | * We need to account for that here. */ | 
|  | 222 | static inline int b43_new_kidx_api(struct b43_wldev *dev) | 
|  | 223 | { | 
|  | 224 | /* FIXME: Not sure the change was at rev 351 */ | 
|  | 225 | return (dev->fw.rev >= 351); | 
|  | 226 | } | 
|  | 227 | static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) | 
|  | 228 | { | 
|  | 229 | u8 firmware_kidx; | 
|  | 230 | if (b43_new_kidx_api(dev)) { | 
|  | 231 | firmware_kidx = raw_kidx; | 
|  | 232 | } else { | 
|  | 233 | if (raw_kidx >= 4)	/* Is per STA key? */ | 
|  | 234 | firmware_kidx = raw_kidx - 4; | 
|  | 235 | else | 
|  | 236 | firmware_kidx = raw_kidx;	/* TX default key */ | 
|  | 237 | } | 
|  | 238 | return firmware_kidx; | 
|  | 239 | } | 
|  | 240 | static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) | 
|  | 241 | { | 
|  | 242 | u8 raw_kidx; | 
|  | 243 | if (b43_new_kidx_api(dev)) | 
|  | 244 | raw_kidx = firmware_kidx; | 
|  | 245 | else | 
|  | 246 | raw_kidx = firmware_kidx + 4;	/* RX default keys or per STA keys */ | 
|  | 247 | return raw_kidx; | 
|  | 248 | } | 
|  | 249 |  | 
|  | 250 | #endif /* B43_XMIT_H_ */ |