)]}' { "log": [ { "commit": "411e23dbe9c5867045f34ba83ee84b31b5b9950c", "tree": "bbdf0ce4244c52e1256082711da17c8775a2f48f", "parents": [ "4b119e21d0c66c22e8ca03df05d9de623d0eb50f" ], "author": { "name": "Zhang Wei", "email": "wei.zhang@freescale.com", "time": "Thu Apr 17 20:17:25 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:22:15 2008 -0700" }, "message": "fsldma: Remove CONFIG_FSL_DMA_SELFTEST, keep fsl_dma_self_test() running always.\n\nAlways enabling the fsl_dma_self_test() to ensure the DMA controller\nshould works well after the driver probed.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "173acc7ce8538f1f3040791dc622a92aadc12cf4", "tree": "f408e415851cf3343af6077287984169958951ad", "parents": [ "976dde010e513a9c7c3117a32b7b015f84b37430" ], "author": { "name": "Zhang Wei", "email": "wei.zhang@freescale.com", "time": "Sat Mar 01 07:42:48 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 04 10:16:46 2008 -0700" }, "message": "dmaengine: add driver for Freescale MPC85xx DMA controller\n\nThe driver implements DMA engine API for Freescale MPC85xx DMA controller,\nwhich could be used by devices in the silicon. The driver supports the\nBasic mode of Freescale MPC85xx DMA controller. The MPC85xx processors\nsupported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on.\n\nThe MPC83xx(MPC8349, MPC8360) are also supported.\n\n[kamalesh@linux.vnet.ibm.com: build fix]\n[dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25]\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Ebony Zhu \u003cebony.zhu@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@gate.crashing.org\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54", "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e", "parents": [ "d909b347591a23c5a2c324fbccd4c9c966f31c67" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:57 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead. Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses. In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses. This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *). As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n" }, { "commit": "6d4f5879b6f4da50bde94e1cae73755978ed048f", "tree": "149340866e3a7d65fca49763ce7caa56ada370c4", "parents": [ "e593f070b40887dc0415646a4c0720eb8630c722" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Nov 28 16:21:43 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Nov 29 09:24:53 2007 -0800" }, "message": "dmaengine: correct invalid assumptions in the Kconfig text\n\nThis patch corrects recently changed (and now invalid) Kconfig descriptions\nfor the DMA engine framework:\n\n - Non-Intel(R) hardware also has DMA engines;\n - DMA is used for more than memcpy and RAID offloading.\n\nIn fact, on most platforms memcpy and RAID aren\u0027t factors, and DMA\nexists so that peripherals can transfer data to/from memory while\nthe CPU does other work.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "4138f08d1c2783a28df2af6ed81aa180462ec374", "tree": "11b9d3b4cbafe4c9d1dd7c9b7ef934dee2bafdb4", "parents": [ "bc2a3f86f46569fb091792867ce67c9ab24dfd0f" ], "author": { "name": "Andi Kleen", "email": "ak@suse.de", "time": "Mon Oct 29 14:37:18 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Tue Oct 30 08:06:55 2007 -0700" }, "message": "Remove bogus default y for DMAR and NET_DMA\n\nNo reason I can think of of making them default y Most people don\u0027t have\nthe hardware and with default y they just pollute lots of configs during\nmake oldconfig.\n\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nAcked-by: Jeff Garzik \u003cjeff@garzik.org\u003e\nAcked-by: \"Nelson, Shannon\" \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "2ed6dc34f9ed39bb8e4c81ea1056f0ba56315841", "tree": "e3f6ca7961f9c4e34453d06e584c0bc98ec630d7", "parents": [ "7589670f37736bcc119ebfbd69aafea6d585d1d4" ], "author": { "name": "Shannon Nelson", "email": "shannon.nelson@intel.com", "time": "Tue Oct 16 01:27:42 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Tue Oct 16 09:43:09 2007 -0700" }, "message": "I/OAT: Add DCA services\n\nAdd code to connect to the DCA driver and provide cpu tags for use by\ndrivers that would like to use Direct Cache Access hints.\n\n [Adrian Bunk] Several Kconfig cleanup items\n [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when\n\t\t\t built for uni-processor\n\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1b0fac45878bb88759eec347c273285195649ff7", "tree": "a9871a47ef98c90bac3f65a7f9309e87420c694c", "parents": [ "9e7bf24b1b979db256ddc84d0d4ac6040d706da6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Jul 15 23:40:26 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Jul 16 09:05:45 2007 -0700" }, "message": "dma-mapping: prevent dma dependent code from linking on !HAS_DMA archs\n\nContinuing the work started in 411f0f3edc141a582190d3605cadd1d993abb6df ...\n\nThis enables code with a dma path, that compiles away, to build without\nrequiring additional code factoring. It also prevents code that calls\ndma_alloc_coherent and dma_free_coherent from linking whereas previously\nthe code would hit a BUG() at run time. Finally, it allows archs that set\n!HAS_DMA to delete their asm/dma-mapping.h file.\n\nCc: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Heiko Carstens \u003cheiko.carstens@de.ibm.com\u003e\nCc: John W. Linville \u003clinville@tuxdriver.com\u003e\nCc: Kyle McMartin \u003ckyle@parisc-linux.org\u003e\nCc: James Bottomley \u003cJames.Bottomley@SteelEye.com\u003e\nCc: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: \u003cgeert@linux-m68k.org\u003e\nCc: \u003czippel@linux-m68k.org\u003e\nCc: \u003cspyro@f2s.com\u003e\nCc: \u003cysato@users.sourceforge.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "c211092313b90f898dec61f35207fc282d1eadc3", "tree": "30df0c81f207d0babb3fe56a17419f37e71e973a", "parents": [ "f6dff381af01006ffae3c23cd2e07e30584de0ec" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 13:52:26 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:18 2007 -0700" }, "message": "dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines\n\nThe Intel(R) IOP series of i/o processors integrate an Xscale core with\nraid acceleration engines. The capabilities per platform are:\n\niop219:\n (2) copy engines\niop321:\n (2) copy engines\n (1) xor and block fill engine\niop33x:\n (2) copy and crc32c engines\n (1) xor, xor zero sum, pq, pq zero sum, and block fill engine\niop34x (iop13xx):\n (2) copy, crc32c, xor, xor zero sum, and block fill engines\n (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine\n\nThe driver supports the features of the async_tx api:\n* asynchronous notification of operation completion\n* implicit (interupt triggered) handling of inter-channel transaction\n dependencies\n\nThe driver adapts to the platform it is running by two methods.\n1/ #include \u003casm/arch/adma.h\u003e which defines the hardware specific\n iop_chan_* and iop_desc_* routines as a series of static inline\n functions\n2/ The private platform data attached to the platform_device defines the\n capabilities of the channels\n\n20070626: Callbacks are run in a tasklet. Given the recent discussion on\nLKML about killing tasklets in favor of workqueues I did a quick conversion\nof the driver. Raid5 resync performance dropped from 50MB/s to 30MB/s, so\nthe tasklet implementation remains until a generic softirq interface is\navailable.\n\nChangelog:\n* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few\nslots to be requested eventually leading to data corruption\n* enabled the slot allocation routine to attempt to free slots before\nreturning -ENOMEM\n* switched the cleanup routine to solely use the software chain and the\nstatus register to determine if a descriptor is complete. This is\nnecessary to support other IOP engines that do not have status writeback\ncapability\n* make the driver iop generic\n* modified the allocation routines to understand allocating a group of\nslots for a single operation\n* added a null xor initialization operation for the xor only channel on\niop3xx\n* support xor operations on buffers larger than the hardware maximum\n* split the do_* routines into separate prep, src/dest set, submit stages\n* added async_tx support (dependent operations initiation at cleanup time)\n* simplified group handling\n* added interrupt support (callbacks via tasklets)\n* brought the pending depth inline with ioat (i.e. 4 descriptors)\n* drop dma mapping methods, suggested by Chris Leech\n* don\u0027t use inline in C files, Adrian Bunk\n* remove static tasklet declarations\n* make iop_adma_alloc_slots easier to read and remove chances for a\n corrupted descriptor chain\n* fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt\n* convert capabilities over to dma_cap_mask_t\n* fixup sparse warnings\n* add descriptor flush before iop_chan_enable\n* checkpatch.pl fixes\n* gpl v2 only correction\n* move set_src, set_dest, submit to async_tx methods\n* move group_list and phys to async_tx\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9bc89cd82d6f88fb0ca39b30445c329a430fd66b", "tree": "7bd0e856abd359f84edea1bacfd1dd32edd93fbb", "parents": [ "685784aaf3cd0e3ff5e36c7ecf6f441cdbf57f73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 11:10:44 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:14 2007 -0700" }, "message": "async_tx: add the async_tx api\n\nThe async_tx api provides methods for describing a chain of asynchronous\nbulk memory transfers/transforms with support for inter-transactional\ndependencies. It is implemented as a dmaengine client that smooths over\nthe details of different hardware offload engine implementations. Code\nthat is written to the api can optimize for asynchronous operation and the\napi will fit the chain of operations to the available offload resources. \n \n\tI imagine that any piece of ADMA hardware would register with the\n\t\u0027async_*\u0027 subsystem, and a call to async_X would be routed as\n\tappropriate, or be run in-line. - Neil Brown\n\nasync_tx exploits the capabilities of struct dma_async_tx_descriptor to\nprovide an api of the following general format:\n\nstruct dma_async_tx_descriptor *\nasync_\u003coperation\u003e(..., struct dma_async_tx_descriptor *depend_tx,\n\t\t\tdma_async_tx_callback cb_fn, void *cb_param)\n{\n\tstruct dma_chan *chan \u003d async_tx_find_channel(depend_tx, \u003coperation\u003e);\n\tstruct dma_device *device \u003d chan ? chan-\u003edevice : NULL;\n\tint int_en \u003d cb_fn ? 1 : 0;\n\tstruct dma_async_tx_descriptor *tx \u003d device ?\n\t\tdevice-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_en) : NULL;\n\n\tif (tx) { /* run \u003coperation\u003e asynchronously */\n\t\t...\n\t\ttx-\u003etx_set_dest(addr, tx, index);\n\t\t...\n\t\ttx-\u003etx_set_src(addr, tx, index);\n\t\t...\n\t\tasync_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);\n\t} else { /* run \u003coperation\u003e synchronously */\n\t\t...\n\t\t\u003coperation\u003e\n\t\t...\n\t\tasync_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);\n\t}\n\n\treturn tx;\n}\n\nasync_tx_find_channel() returns a capable channel from its pool. The\nchannel pool is organized as a per-cpu array of channel pointers. The\nasync_tx_rebalance() routine is tasked with managing these arrays. In the\nuniprocessor case async_tx_rebalance() tries to spread responsibility\nevenly over channels of similar capabilities. For example if there are two\ncopy+xor channels, one will handle copy operations and the other will\nhandle xor. In the SMP case async_tx_rebalance() attempts to spread the\noperations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor\nchannel0 while cpu1 gets copy channel 1 and xor channel 1. When a\ndependency is specified async_tx_find_channel defaults to keeping the\noperation on the same channel. A xor-\u003ecopy-\u003exor chain will stay on one\nchannel if it supports both operation types, otherwise the transaction will\ntransition between a copy and a xor resource.\n\nCurrently the raid5 implementation in the MD raid456 driver has been\nconverted to the async_tx api. A driver for the offload engines on the\nIntel Xscale series of I/O processors, iop-adma, is provided in a later\ncommit. With the iop-adma driver and async_tx, raid456 is able to offload\ncopy, xor, and xor-zero-sum operations to hardware engines.\n \nOn iop342 tiobench showed higher throughput for sequential writes (20 - 30%\nimprovement) and sequential reads to a degraded array (40 - 55%\nimprovement). For the other cases performance was roughly equal, +/- a few\npercentage points. On a x86-smp platform the performance of the async_tx\nimplementation (in synchronous mode) was also +/- a few percentage points\nof the original implementation. According to \u0027top\u0027 on iop342 CPU\nutilization drops from ~50% to ~15% during a \u0027resync\u0027 while the speed\naccording to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.\n \nThe tiobench command line used for testing was: tiobench --size 2048\n--block 4096 --block 131072 --dir /mnt/raid --numruns 5\n* iop342 had 1GB of memory available\n\nDetails:\n* if CONFIG_DMA_ENGINE\u003dn the asynchronous path is compiled away by making\n async_tx_find_channel a static inline routine that always returns NULL\n* when a callback is specified for a given transaction an interrupt will\n fire at operation completion time and the callback will occur in a\n tasklet. if the the channel does not support interrupts then a live\n polling wait will be performed\n* the api is written as a dmaengine client that requests all available\n channels\n* In support of dependencies the api implicitly schedules channel-switch\n interrupts. The interrupt triggers the cleanup tasklet which causes\n pending operations to be scheduled on the next channel\n* Xor engines treat an xor destination address differently than a software\n xor routine. To the software routine the destination address is an implied\n source, whereas engines treat it as a write-only destination. This patch\n modifies the xor_blocks routine to take a an explicit destination address\n to mirror the hardware.\n\nChangelog:\n* fixed a leftover debug print\n* don\u0027t allow callbacks in async_interrupt_cond\n* fixed xor_block changes\n* fixed usage of ASYNC_TX_XOR_DROP_DEST\n* drop dma mapping methods, suggested by Chris Leech\n* printk warning fixups from Andrew Morton\n* don\u0027t use inline in C files, Adrian Bunk\n* select the API when MD is enabled\n* BUG_ON xor source counts \u003c\u003d 1\n* implicitly handle hardware concerns like channel switching and\n interrupts, Neil Brown\n* remove the per operation type list, and distribute operation capabilities\n evenly amongst the available channels\n* simplify async_tx_find_channel to optimize the fast path\n* introduce the channel_table_initialized flag to prevent early calls to\n the api\n* reorganize the code to mimic crypto\n* include mm.h as not all archs include it in dma-mapping.h\n* make the Kconfig options non-user visible, Adrian Bunk\n* move async_tx under crypto since it is meant as \u0027core\u0027 functionality, and\n the two may share algorithms in the future\n* move large inline functions into c files\n* checkpatch.pl fixes\n* gpl v2 only correction\n\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-By: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "9556fb73edfc37410cab3b47ae5e94bcecd8edf2", "tree": "dbe5fed3ab9f58f8ab804cb3f243b9259867cf3f", "parents": [ "e25df1205f37c7bff3ab14fdfc8a5249f3c69c82" ], "author": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Thu May 10 15:45:58 2007 +0200" }, "committer": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Thu May 10 15:46:07 2007 +0200" }, "message": "[S390] Kconfig: unwanted menus for s390.\n\nDisable some more menus in the configuration files that are of no\ninterest to a s390 machine.\n\nSigned-off-by: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\n" }, { "commit": "db21733488f84a596faaad0d05430b3f51804692", "tree": "a2c1f6d39ce27d2e86b395f2bf536c1ab7396411", "parents": [ "57c651f74cd8383df10a648e677902849de1bc0b" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Sat Jun 17 21:24:58 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Jun 17 21:24:58 2006 -0700" }, "message": "[I/OAT]: Setup the networking subsystem as a DMA client\n\nAttempts to allocate per-CPU DMA channels\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0bbd5f4e97ff9c057b385a1886b4aed1fb0300f1", "tree": "0c3d8528c31e8291fb78c2e7a287910987ed2888", "parents": [ "c13c8260da3155f2cefb63b0d1b7dcdcb405c644" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:35:34 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:46 2006 -0700" }, "message": "[I/OAT]: Driver for the Intel(R) I/OAT DMA engine\n\nAdds a new ioatdma driver\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644", "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402", "parents": [ "427abfa28afedffadfca9dd8b067eb6d36bac53f" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:18:44 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:43 2006 -0700" }, "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }